RPI

Rensselaer Polytechnic Institute Advanced Computer Hardware Design ECSE 4780 Computer Architecture Prototyping ECSE 6700

Design of an 8-bit bus-oriented computer

Written By Sung-Gon Lee Rev. B Modified By Jon Riehl

A. Objectives
This laboratory assignment is an introduction to a complete 8-bit bus-oriented computer design using Alteras Quartus software. Students are expected to construct and to implement McCallas 8-bit computer on the Altera FPGA Hardware. Possible use of a logic analyzer may be required to debug when implementing.

B. Preparatory reading and other References

1. Thomas R. McCalla. Digital Logic and Computer Design, Ch 12 (Macmillan, 1992) 2. Thomas R. McCalla. Digital Logic and Computer Design, Ch 14 (Macmillan, 1992) 3. Altera Quartus II Tutorial, http://www2.uic.edu/~wahmad1/quartus_ii_tutorial.pdf 4. Manual of Logic Analyzer

C. General Description of McCallas 8-bit bus-oriented computer

As described in McCallas book on Ch 12, a simple computer can be divided into two major components: a processor and an I/O subsystem. The Input to a system can be realized by an external HEXKEY switch or by VHDL code programmed for a program-load facility. The processor can be also divided into two major modules: a CPU and a Memory Subsystem. In the Memory Subsystem, a RAM is required to store a specified set of instructions. There are various ways to design a RAM in Xinlix software. Even though there is no limit to choosing a size of the RAM, the size may affect implementing the system onto a FPGA chip since the RAM normally consumes a large amount of resources in the chip. This may result in timing conflicts among the control signals when routing. Then, the CPU is composed of a Data Path Subsystem and a Control Unit Subsystem. The Data Path Subsystem is also known as Arithmetic Logic Unit (ALU), whose main job is to add and subtract two binary words stored in Registers A and B. The Control Unit Subsystem fetches program instruction from a single bus and generates logic control signals that are used in other modules such as
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Data Path Subsystem and Memory Subsystem. system is illustrated in <Figure 1>.

The hierarchical view of the McCallas

Computer

Processor

CPU

Data Path Subsystem (ALU)

Control Unit Subsystem

Memory Subsystem

I/O Subsystem

<Figure 1> Hierarchical view of a computer system

D. Functional Descriptions of each subsystem

1. I/O Subsystem This Subsystem is necessary to load a given set of instructions into a memory so that a computer executes each instruction every cycle. It is possible to install a VHDL coded STARTUP module to perform this function, but it is more ideal to construct a preprogrammed RAM module using the MegaWizard plug-in manager. This option will be described in the memory subsystem section.
When implementing your design into an Altera FPGA board, you need to add IPAD or OPAD to interface your software design with an external signal for clocking. attached to the board to verify your output. provided in lab. You may use a function generator as an external clock and use the seven-segment LED display Pin layouts for the LED display will be

2. Memory Subsystem There are various ways to design a memory subsystem using Altera. A memory subsystem can have a RAM or a ROM which holds a set of instructions such as LOAD, ADD, SUB, STORE etc. For a real computer system simulation, it is possible to upload instructions into the memory before running the entire system. To accomplish this, you may create a HDL coded module, which loads the instructions into a RAM by giving
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LD_MA and LD_MW signals at an appropriate time.

However, it is cumbersome work Hence, a

to design a system with the HDL editor since it is harder to debug later on. McCallas 8-bit bus-oriented computer. accumulators, multiplexers, and counters. schematic editor. manager.

pre-programmed RAM module using MegaWizard plug-in manager is ideal for the The MegaWizard plug-in manager is a It is located under the tool option in the graphical interactive tool that a designer can create high-level modules such as The following section describes how to use the MegaWizard plug-in

MegaWizard Plug-In Manager 1. Select MegaWizard Plug-In Manager in the tools menu.
2. 3. 4.

Select the option to Create a new custom megafunction variation and hit Next. Select LP_RAM_DQ from the megafunction list (under the storage directory). Make sure the device family is set to FLEX10K, and select the HDL of your choice for the output file. (xxx.vhd for VHDL outputs). Modify the output file name as desired Click next.

5. 6.

Set Data Bus Width to 8 (this is an 8-bit bus-oriented computer). Select the Memory Depth: 32, 64, 128, 256, etc. and click next.

<Figure 2> Altera MegaWizard Plug-In Manager for steps 5 and 6

7.

Select which ports should be registered (most likely you only want the two input ports to be registered) and hit next. Select yes to specify a file for pre-loaded memory content data.
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8.

Select the

included init.hex file (you can modify this later).

9.

Click next.

Finally, select all of the desired output files (the bsf file is recommended) and click finish. You may now use your memory block the same as any other chip.

<Figure 3> shows the .hex file editor, which allows you to insert a set of instructions. Make sure that the word size is 8 when you open the .hex file. Each box in the window holds an instruction, so that there are eight instructions per line.

<Figure 3> .hex File Window The following segment of data must be inserted after DATA field in the Data Section. A binary number representation has been used to describe the memory addresses and data values. The four digits on the left field represent 4-bit memory addresses. If you look at the schematic of the memory subsystem, you can easily find that I used 4-bit bus going into RAM module. field. The eight bits on the right represent data value. For example, the first data value is composed of 3-bit opcode and 5-bit direct address Only if you use the RAM with depth 32 and width 8, your memory However, since I use RAM16x8, I The instruction subsystem must utilize 5-bit direct address field.

am only required to have four bits for the direct memory address. A.

LDA executes loading the content stored in the memory address 01000 into Register One thing noticeable in filling out the data values is that you can have two data In other words, you can specify the memory address for the first data This is only a simple set of instructions that have been used for Instructions that you can add fields, 00000110 and 00000010, given a specified memory address as shown in the last line. value, and the value followed by comma is stored in the next memory address 10001 in this example. demonstrating a simple 8-bit bus-oriented computer.

into pre-designed computer are illustrated in <Figure 4> from the McCalla text.

<Figure 4> Instruction Repertoire

3. Control Unit Subsystem A control unit subsystem is composed of a next-state generator and an output decoder. The next-state generator generates a process control algorithm for the next-state table and the output decoder generates the logic for data path control signals. A simple computer uses 3-bit opcode to develop 8 instructions using a decoder. It is not required to design a complicted 8-bit computer, but if you want to add more than 8 instructions, you may have to use more bits for the opcode. A control unit subsystem traces the control flow for each instruction and can be constructed by a help of an instruction-time (or p-term) event table as shown in <Figure 5>. You dont have to create a new table for your instructions but just manipulate them if you add more instructions.

<Figure 5> p-term event table

<Figure6> p-term/control point activation table An careful examination of the instruction (p-term) event table to identify each control point leads to the construction of a p-term/control point activation table, as shown in <Figure 6>. You can verify the entries by tracing each instructions micro-operations This figure illustrates the memory and data path of A 3-state buffer interfaces the shared bus (Z-bus) with data through the data path in <Figure 7>. a bus-oriented computer. path and memory.

<Figure 7>

Memory and Data Path of a bus-oriented computer Based on the figures

You are not required to create a new 8-bit bus-oriented computer. of system.

and explanations discussed in the above, use and modify them to adjust your own design The control unit subsystem generates control signals required to perform You will be each instruction and hence it is important to check and trace those signals that are needed to carry out each instruction such as LOAD, ADD, SUBTRACT, etc. expected to build the subsystem as a Macro and you will also need to verify that the subsystem works properly by performing the Simulate Current Macro from the tool option with a specific set of inputs to the Macro.
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4. Data Path Subsystem (ALU) A data path subsystem is a computing device that supports a variety of arithmetic and logic operations. A simple computer can add and subtract by using AND and XOR operations, but is not limited to complementing, incrementing and negating the stable value stored in the Register A. You may use two parallel 4-bit adders to perform this operation or just use an 8-bit adder for your convenience. A sample data path subsystem is drawn at the end of this lab. As implementing data path subsystem with control unit subsystem, a CPU has been realized. A CPU and a memory subsystem realize a storedprogram computer processor which fetches an instruction from memory, decodes and executes each program instruction. A step-by-step procedure to accomplish the fetch is done by incrementing a program counter that traces a memory address from zero. 5. Program Counter (PC) A program counter is an incrementing device for a step-by-step procedure to fetch an instruction or an address in each instruction cycle. In the McCallas book, the program counter is designed with two parallel 4-bit counters used to fetch an instruction from memory address 00H (Hex). The program counter must be set to zero before the clock starts running. Therefore, as the clock starts, it tries to fetch an instruction stored in memory address, 00H, and the three bits of the instruction will be fetched onto an output decoder in control unit subsystem to generate control signals to drive the data path subsystem. This program counter macro takes four major inputs: DATA, LD_PC, PCO and T1.
T1 PC DATA The program counter is incremented every T1 in the instruction cycle. Controls the program counter output to the Z-bus. Loads the PC with the value of 8-bit DATA when JMP instruction 8-bit wide address fetched from memory by JMP instruction

LD_PC

JMP is an absolute jump instruction which directs the process control to a specified address without incrementing the program counter. It is different from BRA instruction since the BRA instruction is a conditional jump instruction, and thus you are required to design a simple program counter to perform both incrementing a PC by one when a normal operation and jumping to a specified address when JMP or BRA instruction. For detailed information on the structure of a computer system, read carefully on Ch. 12 and Ch.14 of the McCallas Digital Logic and Hardware Design.

E. Design Requirements
It is a good practice to divide the system into several subsystems depending on their functions. Once each of these subsystems is constructed, a computer can be assembled by a bottom-up procedure implementation. schematic editor. VHDL code. Each subsystem can be built as a macro with a Quartus II Also, the Quartus II Student Edition supports designing a system with The micro-operations are well This table is very useful to

For example, the control unit subsystem can be built by a sequence of micro-

operations at specific times within an instruction cycle. described in Ch 14 with an instruction-time event table. instruction. input.

understand the ways that each control signal is constructed with when processing each Each macro can be verified by a functional simulation using an example set of

The objective of this lab is to design a simple 8-bit bus-oriented computer as described in McCallas book. This lab provides basic structures of system and guides you to follow the The advanced objective of this lab is to modify the simple This requires some Furthermore, you may need to restep-by-step procedures.

computer you have initially designed by adding more instructions. changes in the schematic of Control Unit subsystem. design the RAM to hold more instructions.

The step-by-step procedures to accomplish your

design implementation are described in the section, Design with Altera Foundation Series 2.1i. After you have completely implemented your design onto Altera FPGA board, you are required to change your system design with extended capability as described in <Figure 8>. Unlike the instructions for a simple computer, this table includes additional types of instructions in the basic categories. The additional instructions include subroutine jump, This type of design jump indirect, multiply and divide, and conditional branch instructions. additional time T4 in Ring Counter Clock.

requires a different cycle period for each instruction, i.e. another D-Flip Flop to generate an

<Figure 8> Instructions Table with extended capability

F. Summary of an 8-bit bus-oriented computer

The individual operation involved in fetching, decoding, and executing an instruction is referred to as a micro-operation. The execution of each operation requires a finite amount A memory read operation is initiated at the time T0, The of time, which is one instruction cycle.

and causes an addressed memory location to be read out onto the bus after some propagation delays (propagation delay must be carefully considered when doing verification!). processing (fetch, decode, execute) of each instruction is accomplished in the next cycle, T1. The 3-bit opcode is sent to an output decoder in the control unit subsystem. The 5-bit direct address field is used to read out the content stored in that address and the program counter is automatically incremented to fetch the next instruction for the subsequent operation. Depending on the instruction, the addressed memory puts out the content onto the Z-bus and other module such as Data path subsystem is ready to load the value that exists in the bus at time T2. For example, the addressed value existing in the bus is loaded into Register B for When a simple arithmetic operation is executed, the resulting The instruction execution for a simple 8-bit addition or subtraction.

output is placed into Register A at time T3. clock cycles for an instruction cycle. is illustrated in <Figure 9>.

computer is completed within four clock cycles. More complicated system may require five An example of timing diagram for an instruction cycle

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<Figure 9> Timing Diagram for a simple computer The McCallas computer utilizes a shared bus structure and devices with 3-state outputs to make the design of digital system much simpler. bus at the same time. Since the computer is designed with a single Z-bus structure, a bus conflict arises when more than one bus driver tries to drive the Since more than one module feeds the bus, each device driving the This would functionally prevent bus contention However, you may still encounter a For this kind bus must be interfaced by a 3-state buffer.

from being taken place among devices feeding the bus.

bus conflict error when you verify the system after implementation in Altera. bus at the same time.

of error, you need to come out with a distinctive logic to ensure that no two devices feed the

G. Design with Altera Quartus II

1. Divide a computer into subsystems 2. Design each subsystem as a Macro: Datapath, Control unit, Memory subsystems 3. Draw a schematic for each subsystem or use the HDL editor 4. Test each macro with the Simulator tool (you need to supply a set of input to each macro) 5. Once all the subsystems work properly, then assemble them as one system 6. Test the entire system in the Simulator. in the project you created are ACTIVE. the HDL macro before you simulate it.
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Make sure that all the macros or schematics For example, if you design a subsystem You will need to update

with the HDL Editor, it might not have an updated Netlist.

7. If the functional diagram works without an error, run the Implementation. generate a .sof file downloadable to the FPGA board. 8. Use the Timing Analyzer tool to verify that your design should work. array.

This will

If the timing

verification works without an error, your design should work properly on the gate If the timing verification is not successful, you need to debug and adjust your design to fix the timing errors. 9. Once the verification is successful, you are ready to download the .sof file into Altera FPGA board and check if the system works as what you have designed.

H. Grading Requirements
There are three graded parts to this lab. The lab is worth 30% of your final grade in ACHD.

1. Prelab A (5% of final grade) Due in Lab Week 6

1. Read Chapters 12 and 14 of the McCalla text. 2. Install Altera Quartus II Web Edition from https://www.altera.com/support/software/download/sof-download_center.html and familiarize yourself with the tools by looking at the given design. Write a brief summary of the functionality of the basic McCalla machine. 3. Write a one to two page summary of the functionality of the basic McCalla machine (Describe each subsystem). 4. Analyze the init.hex file included in the zip file. Write down a table with the following information (the first one is done for you) : Address 0 1 2 3 4 5 6 Hex 10 31 52 73 08 13 E0 Binary 00010000 Command LDADIR $10 RTL for Reg A A <- 44H Result A:44H 0100

2. Prelab B (5% of final grade) Due in Lab Week 7

1. The given design includes 5 instructions (LDADIR, ADDIR, SUBDIR, STADIR, and JMP). Each lab member is to choose one new instruction, implementing the hardware changes required. Each student is also required to implement the BRA0 instruction. Choose instructions from the following list: ADDIND, SUBIND, CLA, COMP, INP, OUT, CMPIMM, BREQ. process.
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Include a one page report of your design

3. Postlab (20% of final grade) Due Friday of Week 8 (before Spring Break)
1. Complete the modified McCalla machine (with all students instructions and BRA0). 2. Display Register As value on the seven segment display on the FPGA. 3. Show complete instruction sets and code. 4. Write up a final report including detailed design functionality, debugging process. You should also include the schematics/HDL files and a functional waveform. Grading will be based on both functionality and students knowledge of the design. A separate report is required by each team member. 5. Grading Breakdown for postlab: i. Describe your design in detail, including each subsystem (30%) ii. Debugging Issues (10%) iii. Schematics (10%) iv. Functional Waveform (20%) v. Timing Diagram (10%) vi. Final Implementation on FPGA as verified by TA (20%)

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