RC3 PIC 18F452(B) RC4

RC3 PIC 18F452 (A) RC5

Figure ( ) interfacing between 2 PIC's We use SPI connection between PIC's, where its faster than serial connection .

2.2.1.2 Synchronization of digital ,SPI, Serial

communication Synchronization of digital:systems mean that every component in the digital system work with the main clock and the system keep track with all events happened inside the system this is a type of synch. Sometimes the synchronization is very important when you are working with transmitting and receiving data there must be synch between the sender and the receiver.

SPI (Serial Peripheral Interface Bus)

The Serial Peripheral Interface Bus or is a synchronous serial data link that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select lines. Sometimes SPI is called a "four-wire" serial bus, contrasting with three-, two-, and one-wire serial buses.

Figure(

):- SPI bus: single master and single slave

INTERFACING: The SPI bus specifies four logic signals

SCK; CLK: Serial Clock (output from master) SDI; DI, SI: Serial Data In; Data In, Serial In SDO; DO, SO: Serial Data Out; Data Out, Serial Out nCS, CS, CSB, CSN, nSS, STE: Chip Select, Slave Transmit Enable (active low, output from master

OPERATION:

The SPI bus can operate with a single master device and with one or more slave devices.

If a single slave device is used, the SS pin may be fixed to logic low if the slave permits it. Some slaves require the falling edge (highlow transition) of the slave select to initiate an action such as the Maxim MAX1242 ADC, which starts conversion on said transition. With multiple slave devices, an independent SS signal is required from the master for each slave device.

Most slave devices have tri-state outputs so their MISO signal becomes high

impedance ("disconnected") when the device is not selected. Devices without tristate outputs can't share SPI bus segments with other devices; only one such slave could talk to the master, and only its chip select could be activated.

DATA TRANSMISSION:To begin a communication, the master first configures the clock, using a frequency less than or equal to the maximum frequency the slave device supports. Such frequencies are commonly in the range of 170 MHz.

The master then pulls the slave select low for the desired chip. If a waiting period is required (such as for analog-to-digital conversion) then the master must wait for at least that period of time before starting to issue clock cycles. During each SPI clock cycle, a full duplex data transmission occurs:

the master sends a bit on the MOSI line; the slave reads it from that same line the slave sends a bit on the MISO line; the master reads it from that same line

Not all transmissions require all four of these operations to be meaningful but they do happen. Transmissions normally involve two shift registers of some given word size, such as eight bits, one in the master and one in the slave; they are connected in a ring. Data is usually shifted out with the most significant bit first, while shifting a new least significant bit into the same register. After that register has been shifted out, the master and slave have exchanged register values. Then each device takes that value and does something with it, such as writing it to memory. If there is more data to exchange, the shift registers are loaded with new data and the process repeats. Transmissions may involve any number of clock cycles. When there are no more data to be transmitted, the master stops toggling its clock. Normally, it then deselects the slave. Transmissions often consist of 8-bit words, and a master can initiate multiple such transmissions if it wishes/needs. However, other word sizes are also common, such as 16-bit words for touch screen controllers or audio codecs, like the TSC2101 from Texas Instruments; or 12-bit words for many digital-to-analog or analog-to-digital converters. Every slave on the bus that hasn't been activated using its slave select line must disregard the input clock and MOSI signals, and must not drive MISO. The master must select only one slave at a time.

Figure (

):- A typical hardware setup using two shift registers to form an inter-chip circular buffer

SPI devices sometimes use another signal line to send an interrupt signal to a host CPU.

SERIAL COMUNICATION
In telecommunication and computer science, the concept of serial communication is the process of sending data one bit at a time, sequentially, over a communication channel or computer bus. This is in contrast to parallel communication, where several bits are sent as a whole, on a link with several parallel channels. Serial communication is used for all long-haul communication and most computer networks, where the cost of cable and synchronization difficulties make parallel communication impractical. Serial computer buses are becoming more common even at shorter distances, as improved signal integrity and transmission speeds in newer serial technologies have begun to outweigh the parallel bus's advantage of simplicity (no need for serializer and deserializer, or SerDes) and to outstrip its disadvantages (clock skew, interconnect density). The migration from PCI to PCI Express is an example.

Serial buses Integrated circuits are more expensive when they have more pins. To reduce the number of
pins in a package, many ICs use a serial bus to transfer data when speed is not important. Some examples of such low-cost serial buses include SPI, IC, UNI/O, and 1-Wire. So we see that using SPI is better than using serial communication,from calculation the speed of clock cycle is 2.5 MHz,and the clock speed for one byte is 0.3125 MHZ.So the T=3 .

One of the problem that accur in our design is how we can keep the ratio between volatage and frequency constant. In induction motor we must keep this ratio constant sice the equation satisfies that

So if this ratio changes the flux will change also the current and circuit will break down. The solution was to let the controller PIC generate an DC voltage at maximum 12 V,and this voltage connected as reference voltage to the DAC which is connected to inverter PIC. The flow chart for controller PIC shown in section 2.3.

Vr+ DAC0808

V0

DAC0808

Figure ( ) design for keep the ratio between v and f constant

2.2.3 INVERTER PIC

This PIC contain sine table called look up table, this values found experimentally depend on resolution, we will explain this We know that the sine wave is 3600, we can choose values depend on this, For example. If we want to choose 4 samples /second, which means sample each 900 360/90 = 4, this means that for each 90 degree there is a value , the sine wave will be close to continues pure sine wave when number of samples is largest (more resolution) In first experiment we choose 600 values in table and the result as follows:

Figure ( ) vo using 60 values But for this value a problem will occur this problem optimized by the resolution of the frequency that comes from controller, for more understanding. If the frequency comes from controller change by small value of delay, the frequency of sine wave from inverter change by great value. The resolution of frequency very high and this make it hard to control, we have to minimize this resolution. By testing 30 values and the result as follows (next page).

figure ( ) vo using 30 vlue Finally we adopt to use 16 values for sine table and the result is

Figure ( ) vo using 16 value

By using 15 values the resolution becomes small and this is good for controlling the frequency ,we notice that for changing the time delay from controller by small change,

frequency in inverter output changes by fraction of hertz using these value we get small resolution but we losses the accuracy for pure sine wave and we have to use filtering circuit for this purpose.

The output sine wave has no negative part because the PIC is digital devise and we cannot get negative values for this., and DAC didnt output negative voltages , although we used negative VREF(-), So we designed signal conditioning circiut to solve this problem. Each value for sine wave (output from inverter ) consists 8- bit binary value , this come from that port D from PIC contains 8-pin so 8-bit output . Each 8-bit values is a one value for sine wave amplitude , so we use the DAC convert these digital values to analog values ,and to move from digital to analog, between 2 conversion process there is a delay time by (T) , and the loop repeats until interrupt occur and the value of (T) changes.

2.2.1.4 Digital -to- analog converter (DAC)

a digital-to-analog converter (DAC or D-to-A) is a device that converts a digital (usually binary) code to an analog signal (current, voltage, or electric charge). A DAC converts an abstract finite-precision number (usually a fixed-point binary number) into a concrete physical quantity (e.g., a voltage or a pressure). In particular, DACs are often used to convert finite-precision time series data to a continually varying physical

signal.
A typical DAC converts the abstract numbers into a concrete sequence of impulses that are then processed by a reconstruction filter using some form of interpolation to fill in data between the impulses. Other DAC methods (e.g., methods based on Delta-sigma

modulation) produce a pulse-density modulated signal that can then be filtered in a similar
way to produce a smoothly varying signal. Instead of impulses, usually the sequence of numbers update the analogue voltage at uniform

sampling intervals.
These numbers are written to the DAC, typically with a clock signal that causes each number to be latched in sequence, at which time the DAC output voltage changes rapidly from the previous value to the value represented by the currently latched number. The effect of this is that the output voltage is held in time at the current value until the next input number is latched resulting in a piecewise constant or 'staircase' shaped output. This is equivalent to a

zero-order hold operation and has an effect on the frequency response of the reconstructed
signal.

Figure ( ) constant output of a conventional practical DAC The fact that practical DACs output a sequence of piecewise constant values (known as zero-

order hold in sample data textbooks) or rectangular pulses causes multiple harmonics above
the Nyquist frequency. However, these are typically removed with a low pass filter acting as a reconstruction filter. The V0 from DAC is given by:

Note:

also depending on the V0 that comes from DAC which connected to

inverter,which controls the

for inverter DAC then it controls the