D D D D D D D D D: MSP430C13x1 Mixed Signal Microcontroller

MSP430C13x1 MIXED SIGNAL MICROCONTROLLER
SLAS341C SEPTEMBER 2001 REVISED DECEMBER 2008
D Low Supply-Voltage Range, 1.8 V to 3.6 V D Ultralow Power Consumption:
D D D D D
Active Mode: 160 A at 1 MHz, 2.2 V Standby Mode: 0.9 A Off Mode (RAM Retention) : 0.1 A Five Power-Saving Modes Wake-Up From Standby Mode in Less Than 6 s 16-Bit RISC Architecture, 125-ns Instruction Cycle Time 16-Bit Timer_B With Three Capture/Compare-With-Shadow Registers 16-Bit Timer_A With Three Capture/Compare Registers
D On-Chip Comparator D Serial Communication Interface (USART), D D D D D

Software Selects Asynchronous UART or Synchronous SPI Programmable Code Protection With Security Fuse Family Members Include: MSP430C1331: 8KB ROM, 256B RAM MSP430C1351: 16KB ROM, 512B RAM Available in 64-Pin Quad Flat Pack (QFP) Emulation: Use MSP430F13xIPM For Complete Module Descriptions, See the MSP430x1xx Family Users Guide, Literature Number SLAU049
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 s. The MSP430C13x1 is a microcontroller configuration with two built-in 16-bit timers, one universal serial synchronous/asynchronous communication interfaces (USART), and 48 I/O pins. Typical applications include sensor systems that capture analog signals, convert them to digital values, and process and transmit the data to a host system. The timers make the configurations ideal for industrial control applications, hand-held meters, etc.
AVAILABLE OPTIONS PACKAGED DEVICES TA PLASTIC 64-PIN QFP (PM) MSP430C1331IPM MSP430C1351IPM
40C to 85C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2001 2008, Texas Instruments Incorporated
POST OFFICE BOX 655303
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pin designation, MSP430C1331, MSP430C1351

AVCC DVSS AV SS P6.2 P6.1 P6.0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH DVCC P6.3 P6.4 P6.5 P6.6 P6.7 NC XIN XOUT NC NC P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK P5.6/ACLK P5.5/SMCLK
47 46 45 44 43 42 41 40 39 38 37 36 35 34 PM PACKAGE (TOP VIEW)
1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48
10 11 12 13 14 15
33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P5.4/MCLK P5.3 P5.2 P5.1 P5.0 P4.7/TBCLK P4.6 P4.5 P4.4 P4.3 P4.2/TB2 P4.1/TB1 P4.0/TB0 P3.7 P3.6 P3.5/URXD0
NC No internal connection
P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK P2.1/TAINCLK P2.2/CAOUT/TA0 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/Rosc P2.6 P2.7/TA0 P3.0/STE0 P3.1/SIMO0 P3.2/SOMI0 P3.3/UCLK0 P3.4/UTXD0
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functional block diagrams

MSP430C13x1
XIN XOUT/TCLK DVCC DVSS AVCC AVSS RST/NMI P1 P2 P3 P4 P5 P6
8 ROSC XT2IN XT2OUT Oscillator System Clock ACLK SMCLK 16KB ROM 8KB ROM 512B RAM 256B RAM
8 I/O Port 3/4 16 I/Os
I/O Port 1/2 16 I/Os, with Interrupt Capability
I/O Port 5/6 16 I/Os
MCLK MAB, 4 Bit MCB
Test JTAG CPU Incl. 16 Reg.
MAB,MAB, 16-Bit 16 Bit
MDB, 16-Bit MDB, 16 Bit
Bus Conv
MDB, 8 Bit
4 TMS TCK TDI TDO/TDI Watchdog Timer 15/16-Bit Timer_B3 3 CC Reg Shadow Reg Timer_A3 3 CC Reg POR Comparator A USART0 UART Mode SPI Mode
Terminal Functions
TERMINAL NAME AVCC AVSS DVCC DVSS P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK P2.1/TAINCLK P2.2/CAOUT/TA0 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/ROSC P2.6 P2.7/TA0 P3.0/STE0 NO. 64 62 1 63 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O DESCRIPTION Supply voltage, positive terminal. AVCC and DVCC are internally connected together. Supply voltage, negative terminal. AVSS and DVSS are internally connected together. Supply voltage, positive terminal. AVCC and DVCC are internally connected together. Supply voltage, negative terminal. AVSS and DVSS are internally connected together. General-purpose digital I/O pin/Timer_A, clock signal TACLK input General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output General-purpose digital I/O pin/SMCLK signal output General-purpose digital I/O pin/Timer_A, compare: Out0 output General-purpose digital I/O pin/Timer_A, compare: Out1 output General-purpose digital I/O pin/Timer_A, compare: Out2 output General-purpose digital I/O pin/ACLK output General-purpose digital I/O pin/Timer_A, clock signal at INCLK General-purpose digital I/O pin/Timer_A, capture: CCI0B input/Comparator_A output General-purpose digital I/O pin/Timer_A, compare: Out1 output/Comparator_A input General-purpose digital I/O pin/Timer_A, compare: Out2 output/Comparator_A input General-purpose digital I/O pin/input for external resistor defining the DCO nominal frequency General-purpose digital I/O pin General-purpose digital I/O pin/Timer_A, compare: Out0 output General-purpose digital I/O pin/slave transmit enable USART0/SPI mode
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Terminal Functions (Continued)

TERMINAL NAME P3.1/SIMO0 P3.2/SOMI0 P3.3/UCLK0 P3.4/UTXD0 P3.5/URXD0 P3.6 P3.7 P4.0/TB0 P4.1/TB1 P4.2/TB2 P4.3 P4.4 P4.5 P4.6 P4.7/TBCLK P5.0 P5.1 P5.2 P5.3 P5.4/MCLK P5.5/SMCLK P5.6/ACLK P5.7/TBOUTH P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 P6.7 RST/NMI TCK TDI/TCLK TDO/TDI TMS NC XIN XOUT XT2IN XT2OUT NO. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 59 60 61 2 3 4 5 6 58 57 55 54 56 7, 10, 11 8 9 53 52 I O I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I/O I DESCRIPTION General-purpose digital I/O pin/slave in/master out of USART0/SPI mode General-purpose digital I/O pin/slave out/master in of USART0/SPI mode General-purpose digital I/O pin/external clock input USART0/UART or SPI mode, clock output USART0/SPI mode General-purpose digital I/O pin/transmit data out USART0/UART mode General-purpose digital I/O pin/receive data in USART0/UART mode General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin/Timer_B, capture: CCI0A/B input, compare: Out0 output General-purpose digital I/O pin/Timer_B, capture: CCI1A/B input, compare: Out0 output General-purpose digital I/O pin/Timer_B, capture: CCI2A/B input, compare: Out0 output General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin/Timer_B, clock signal TBCLK input General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin/main system clock MCLK output General-purpose digital I/O pin/submain system clock SMCLK output General-purpose digital I/O pin/auxiliary clock ACLK output General-purpose digital I/O pin/switch all PWM digital output ports to high impedance Timer_B7 TB0 to TB2 General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin Reset input, nonmaskable interrupt input port Test clock. TCK is the clock input port for device programming test. Test data input or test clock input. TDI is used as a data input port. The device protection fuse is connected to TDI. Test data output port. TDO/TDI data output Test mode select. TMS is used as an input port for device test. No internal connection Input port for crystal oscillator XT1. Standard or watch crystals can be connected. Output terminal of crystal oscillator XT1 Input port for crystal oscillator XT2. Only standard crystals can be connected. Output terminal of crystal oscillator XT2
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short-form description
CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. instruction set The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 1 shows examples of the three types of instruction formats; Table 2 lists the address modes.
Program Counter Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register PC/R0 SP/R1 SR/CG1/R2 CG2/R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
Table 1. Instruction Word Formats

Dual operands, source-destination Single operands, destination only Relative jump, un/conditional e.g., ADD R4,R5 e.g., CALL e.g., JNE R8 R4 + R5 > R5 PC >(TOS), R8> PC Jump-on-equal bit = 0
Table 2. Address Mode Descriptions

ADDRESS MODE Register Indexed Symbolic (PC relative) Absolute Indirect Indirect autoincrement Immediate NOTE: S = source S D SYNTAX MOV Rs,Rd MOV X(Rn),Y(Rm) MOV EDE,TONI MOV &MEM,&TCDAT MOV @Rn,Y(Rm) MOV @Rn+,Rm MOV #X,TONI MOV @R10,Tab(R6) MOV @R10+,R11 MOV #45,TONI EXAMPLE MOV R10,R11 MOV 2(R5),6(R6) OPERATION R10 > R11 M(2+R5)> M(6+R6) M(EDE) > M(TONI) M(MEM) > M(TCDAT) M(R10) > M(Tab+R6) M(R10) > R11 R10 + 2> R10 #45 > M(TONI)
D D D D D D D
D D D D
D = destination
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operating modes The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software:
D Active mode AM
All clocks are active.
D Low-power mode 0 (LPM0)

CPU is disabled. ACLK and SMCLK remain active. MCLK is disabled.

CPU is disabled. ACLK and SMCLK remain active. MCLK is disabled. DCOs dc generator is disabled if DCO not used in active mode.

CPU is disabled. MCLK and SMCLK are disabled. DCOs dc generator remains enabled. ACLK remains active

CPU is disabled. MCLK and SMCLK are disabled. DCOs dc generator is disabled. ACLK remains active.

CPU is disabled. ACLK is disabled. MCLK and SMCLK are disabled. DCOs dc generator is disabled. Crystal oscillator is stopped.
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interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE Power-up External reset Watchdog NMI Oscillator fault Timer_B3 INTERRUPT FLAG WDTIFG (see Note 1) NMIIFG (see Notes 1 & 4) OFIFG (see Notes 1 & 4) TBCCR0 CCIFG (see Note 2) TBCCR1 and TBCCR2 CCIFGs, TBIFG (see Notes 1 & 2) CAIFG WDTIFG URXIFG0 UTXIFG0 TACCR0 CCIFG (see Note 2) TACCR1 and TACCR2 CCIFGs, TAIFG (see Notes 1 & 2) P1IFG.0 to P1IFG.7 (see Notes 1 & 2) SYSTEM INTERRUPT Reset WORD ADDRESS 0FFFEh PRIORITY 15, highest
(Non)maskable (Non)maskable Maskable
0FFFCh 0FFFAh
14 13
Timer_B3 Comparator_A Watchdog timer USART0 receive USART0 transmit Timer_A3
Maskable Maskable Maskable Maskable Maskable Maskable
0FFF8h 0FFF6h 0FFF4h 0FFF2h 0FFF0h 0FFEEh 0FFECh
12 11 10 9 8 7 6
Timer_A3
Maskable
0FFEAh
I/O port P1 (eight flags)
Maskable
0FFE8h 0FFE6h 0FFE4h
4 3 2 1 0, lowest
I/O port P2 (eight flags)
P2IFG.0 to P2IFG.7 (see Notes 1 & 2)
Maskable
0FFE2h 0FFE0h
NOTES: 1. 2. 3. 4.
Multiple source flags Interrupt flags are located in the module. Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable it.
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special function registers

Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access.
interrupt enable 1 and 2

Address 0h 7 UTXIE0 rw-0 6 URXIE0 rw-0 5 4 NMIIE rw-0 3 2 1 OFIE rw-0 0 WDTIE rw-0
WDTIE: OFIE: NMIIE: URXIE0: UTXIE0:

Address 01h 7
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in interval timer mode. Oscillator-fault-interrupt enable Nonmaskable-interrupt enable USART0: UART and SPI receive-interrupt enable USART0: UART and SPI transmit-interrupt enable
6 5 4 3 2 1 0
interrupt flag register 1 and 2

Address 02h 7 UTXIFG0 rw-1 6 URXIFG0 rw-0 5 4 NMIIFG rw-0 3 2 1 OFIFG rw-1 0 WDTIFG rw-(0)
WDTIFG: OFIFG: NMIIFG:
Set on Watchdog Timer overflow (in watchdog mode) or security key violation. Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode. Flag set on oscillator fault Set via RST/NMI pin
URXIFG0: USART0: UART and SPI receive flag UTXIFG0: USART0: UART and SPI transmit flag
Address 03h 7 6 5 4 3 2 1 0
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module enable registers 1 and 2

Address 04h 7 UTXE0 rw-0 6 URXE0 USPIE0 rw-0 5 4 3 2 1 0
URXE0: UTXE0: USPIE0:

Address 05h Legend: rw: rw-0,1: rw-(0,1): 7
USART0: UART receive enable USART0: UART transmit enable USART0: SPI (synchronous peripheral interface) transmit and receive enable
6 5 4 3 2 1 0
Bit Can Be Read and Written Bit Can Be Read and Written. It Is Reset or Set by PUC. Bit Can Be Read and Written. It Is Reset or Set by POR. SFR Bit Not Present in Device
memory organization
MSP430C1331 Memory Interrupt vector Code memory RAM Peripherals Size ROM ROM Size 16-bit 8-bit 8-bit SFR 8KB 0FFFFh 0FFE0h 0FFFFh 0E000h 256 Byte 02FFh 0200h 01FFh 0100h 0FFh 010h 0Fh 00h MSP430C1351 16KB 0FFFFh 0FFE0h 0FFFFh 0C000h 512 Byte 03FFh 0200h 01FFh 0100h 0FFh 010h 0Fh 00h
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, see the MSP430x1xx Family Users Guide, literature number SLAU049.
digital I/O
There are six 8-bit I/O ports implementedports P1 through P6:
D D D D
All individual I/O bits are independently programmable. Any combination of input, output, and interrupt conditions is possible. Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2. Read/write access to port-control registers is supported by all instructions.
oscillator and system clock

The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 s. The basic clock module provides the following clock signals:
D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal. D Main clock (MCLK), the system clock used by the CPU. D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
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watchdog timer (WDT)

The primary function of WDT module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.
USART0
The MSP430C13x1 devices have one hardware universal synchronous/asynchronous receive transmit (USART0) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels.
Comparator_A
The primary function of the comparator_A module is to support precision slope analogtodigital conversions, batteryvoltage supervision, and monitoring of external analog signals.
Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
TIMER_A3 SIGNAL CONNECTIONS INPUT PIN NUMBER 12 - P1.0 DEVICE INPUT SIGNAL TACLK ACLK SMCLK 21 - P2.1 13 - P1.1 22 - P2.2 TAINCLK TA0 TA0 DVSS DVCC 14 - P1.2 TA1 CAOUT (internal) DVSS DVCC 15 - P1.3 TA2 ACLK (internal) DVSS DVCC MODULE INPUT NAME TACLK ACLK SMCLK INCLK CCI0A CCI0B GND VCC CCI1A CCI1B GND VCC CCI2A CCI2B GND VCC CCR2 TA2 15 - P1.3 19 - P1.7 24 - P2.4 CCR1 TA1 14 - P1.2 18 - P1.6 23 - P2.3 CCR0 TA0 13 - P1.1 17 - P1.5 27 - P2.7 Timer NA MODULE BLOCK MODULE OUTPUT SIGNAL OUTPUT PIN NUMBER
10
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Timer_B3
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
TIMER_B3 SIGNAL CONNECTIONS INPUT PIN NUMBER 43 - P4.7 DEVICE INPUT SIGNAL TBCLK ACLK SMCLK 43 - P4.7 36 - P4.0 36 - P4.0 TBCLK TB0 TB0 DVSS DVCC 37 - P4.1 37 - P4.1 TB1 TB1 DVSS DVCC 38 - P4.2 38 - P4.2 TB2 TB2 DVSS DVCC MODULE INPUT NAME TBCLK ACLK SMCLK INCLK CCI0A CCI0B GND VCC CCI1A CCI1B GND VCC CCI2A CCI2B GND VCC CCR2 TB2 38 - P4.2 CCR1 TB1 37 - P4.1 CCR0 TB0 36 - P4.0 Timer NA MODULE BLOCK MODULE OUTPUT SIGNAL OUTPUT PIN NUMBER
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peripheral file map

PERIPHERALS WITH WORD ACCESS Watchdog Timer_B3 _ Watchdog Timer control Timer_B interrupt vector Timer_B control Capture/compare control 0 Capture/compare control 1 Capture/compare control 2 Reserved Reserved Reserved Reserved Timer_B register Capture/compare register 0 Capture/compare register 1 Capture/compare register 2 Reserved Reserved Reserved Reserved Timer_A3 _ Timer_A interrupt vector Timer_A control Capture/compare control 0 Capture/compare control 1 Capture/compare control 2 Reserved Reserved Reserved Reserved Timer_A register Capture/compare register 0 Capture/compare register 1 Capture/compare register 2 Reserved Reserved Reserved Reserved PERIPHERALS WITH BYTE ACCESS USART0 Transmit buffer Receive buffer Baud rate Baud rate Modulation control Receive control Transmit control USART control U0TXBUF U0RXBUF U0BR1 U0BR0 U0MCTL U0RCTL U0TCTL U0CTL 077h 076h 075h 074h 073h 072h 071h 070h TAR TACCR0 TACCR1 TACCR2 TAIV TACTL TACCTL0 TACCTL1 TACCTL2 TBR TBCCR0 TBCCR1 TBCCR2 WDTCTL TBIV TBCTL TBCCTL0 TBCCTL1 TBCCTL2 0120h 011Eh 0180h 0182h 0184h 0186h 0188h 018Ah 018Ch 018Eh 0190h 0192h 0194h 0196h 0198h 019Ah 019Ch 019Eh 012Eh 0160h 0162h 0164h 0166h 0168h 016Ah 016Ch 016Eh 0170h 0172h 0174h 0176h 0178h 017Ah 017Ch 017Eh
12
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peripheral file map (continued)

PERIPHERALS WITH BYTE ACCESS (CONTINUED) Comparator_A p _ Comparator_A port disable Comparator_A control2 Comparator_A control1 Basic Clock Basic clock system control2 Basic clock system control1 DCO clock frequency control Port P6 Port P6 selection Port P6 direction Port P6 output Port P6 input Port P5 Port P5 selection Port P5 direction Port P5 output Port P5 input Port P4 Port P4 selection Port P4 direction Port P4 output Port P4 input Port P3 Port P3 selection Port P3 direction Port P3 output Port P3 input Port P2 Port P2 selection Port P2 interrupt enable Port P2 interrupt-edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input Port P1 Port P1 selection Port P1 interrupt enable Port P1 interrupt-edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input Special Functions p SFR module enable 2 SFR module enable 1 SFR interrupt flag 2 SFR interrupt flag 1 SFR interrupt enable 2 SFR interrupt enable 1 CAPD CACTL2 CACTL1 BCSCTL2 BCSCTL1 DCOCTL P6SEL P6DIR P6OUT P6IN P5SEL P5DIR P5OUT P5IN P4SEL P4DIR P4OUT P4IN P3SEL P3DIR P3OUT P3IN P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN ME2 ME1 IFG2 IFG1 IE2 IE1 05Bh 05Ah 059h 058h 057h 056h 037h 036h 035h 034h 033h 032h 031h 030h 01Fh 01Eh 01Dh 01Ch 01Bh 01Ah 019h 018h 02Eh 02Dh 02Ch 02Bh 02Ah 029h 028h 026h 025h 024h 023h 022h 021h 020h 005h 004h 003h 002h 001h 000h
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absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to + 4.1 V Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to VCC+0.3 V Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA Storage temperature (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55C to 150C Storage temperature (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40C to 85C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TDI/TCLK pin when blowing the JTAG fuse.
recommended operating conditions

PARAMETER Supply voltage during program execution, VCC (AVCC = DVCC = VCC) Supply voltage, VSS (AVSS = DVSS = VSS) Operating free-air temperature range, TA LF selected, XTS=0 LFXT1 crystal frequency, f(LFXT1) t lf (see Notes 1 and 2) XT1 selected, XTS=1 XT1 selected, XTS=1 XT2 crystal frequency, f(XT2) frequency Processor frequency (signal MCLK), f(System) MCLK) Watch crystal Ceramic resonator Crystal Ceramic resonator Crystal VCC = 1.8 V VCC = 3.6 V 450 1000 450 1000 DC DC MIN 1.8 0.0 40 32768 8000 8000 8000 8000 4.15 8 MHz kHz NOM MAX 3.6 0.0 85 UNITS V V C Hz kHz kHz
NOTES: 1. In LF mode, the LFXT1 oscillator requires a watch crystal and the LFXT1 oscillator requires a 5.1-M resistor from XOUT to VSS when VCC < 2.5 V. In XT1 mode, the LFXT1. and XT2 oscillators accept a ceramic resonator or a 4-MHz crystal frequency at VCC 2.2 V. In XT1 mode, the LFXT1 and XT2 oscillators accept a ceramic resonator or an 8-MHz crystal frequency at VCC 2.8 V. 2. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, FXT1 accepts a ceramic resonator or a crystal.
f(System) MHz 8.0 MHz
4.15 MHz
1.8 V
2.7 V 3 V Supply Voltage V
3.6 V
Figure 1. Frequency vs Supply Voltage
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electrical characteristics over recommended operating free-air temperature (unless otherwise noted)
supply current into AVCC + DVCC excluding external current
PARAMETER Active mode, (see Note 1) f(MCLK) = f(SMCLK) = 1 MHz, MHz f(ACLK) = 32,768 Hz, XTS=0, SELM=(0,1) I(AM) Active mode, (see Note 1) f(MCLK) = f(SMCLK) = 4 096 Hz, f(ACLK) = 4,096 Hz XTS=0, SELM=(0,1), XTS=0, SELM=3 Low-power mode, Low power mode (LPM0) (see Note 1) Low-power mode, (LPM2), f(MCLK) = f (SMCLK) = 0 MHz, MHz f(ACLK) = 32.768 Hz, SCG0 = 0 TEST CONDITIONS VCC = 2.2 V TA = 40C to 85C 40C VCC = 3 V VCC = 2.2 V TA = 40C to 85C 40C VCC = 3 V TA = 40C to 85C 40C VCC = 2.2 V VCC = 3 V VCC = 2.2 V TA = 40C to 85C 40C TA = 40C Low-power mode (LPM3) mode, f(MCLK) = f(SMCLK) = 0 MHz, f(ACLK) = 32,768 Hz, SCG0 = 1 (see N t 2) Note ( TA = 25C TA = 85C TA = 40C TA = 25C TA = 85C TA = 40C TA = 25C I(LPM4) Low-power mode, (LPM4) MHz, MHz, f(MCLK) = 0 MHz f(SMCLK) = 0 MHz f(ACLK) = 0 Hz, SCG0 = 1 TA = 85C TA = 40C TA = 25C TA = 85C VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V 2.5 32 55 11 17 0.8 0.9 1.6 1.8 1.8 2.3 0.1 0.1 0.8 0.1 0.1 0.8 7 45 70 14 22 1.5 1.5 2.8 2.2 2.2 3.9 0.5 0.5 2.5 0.5 0.5 2.5 A A A A A A A A MIN TYP 160 240 2.5 MAX 200 300 7 A A A A UNIT
I(LPM0)
I(LPM2)
I(LPM3)
NOTES: 1. Timer_B is clocked by f(DCOCLK) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. 2. Timer_B is clocked by f(ACLK) = 32,768 Hz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The current consumption in LPM2 and LPM3 are measured with ACLK selected.
Current consumption of active mode versus system frequency I(AM) = I(AM) [1 MHz] f(System) [MHz] Current consumption of active mode versus supply voltage I(AM) = I(AM) [3 V] + 175 A/V (VCC 3 V)
DALLAS, TEXAS 75265
15

electrical characteristics over recommended operating free-air temperature (unless otherwise noted)
Schmitt-trigger inputs Ports P1, P2, P3, P4, P5, and P6
PARAMETER VIT+ VIT Vhys Positive-going Positive going input threshold voltage Negative-going Negative going input threshold voltage Input voltage hysteresis (VIT+ VIT) TEST CONDITIONS VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V MIN 1.1 1.5 0.4 0.90 0.3 0.4 TYP MAX 1.5 1.9 0.9 1.3 1.1 1 V V V UNIT
standard inputs RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)

PARAMETER VIL VIH Low-level input voltage High-level input voltage TEST CONDITIONS VCC = 2.2 V / 3 V 22 MIN VSS 0.8VCC TYP MAX VSS+0.6 VCC UNIT V V
input frequency Ports P1, P2, P3, P4, P5, and P6

PARAMETER f(IN) t(h) = t(L) TEST CONDITIONS VCC = 2.2 V VCC = 3 V MIN TYP MAX 8 10 UNIT MHz
capture timing Timer_A3 (TA0, TA1, TA2), Timer_B3 (TB0, TB1, TB2)
PARAMETER Ports P2, P4: P t P2 P4 External trigger signal for the interrupt flag (see Notes 1 and 2) TEST CONDITIONS VCC = 2.2 V/3 V VCC = 2.2 V VCC = 3 V MIN 1.5 62 50 ns TYP MAX UNIT Cycle
t(int)
NOTES: 1. The external signal sets the interrupt flag every time t(int) is met. It may be set even with trigger signals shorter than t(int). The conditions to set the flag must be met independently of this timing constraint. t(int) is defined in MCLK cycles. 2. The external signal needs additional timing because of the maximum input-frequency constraint.
external interrupt timing

PARAMETER Ports P1, P2: P t P1 P2 External trigger signal for the interrupt flag (see Notes 1 and 2) TEST CONDITIONS VCC = 2.2 V/3 V VCC = 2.2 V VCC = 3 V MIN 1.5 62 50 ns TYP MAX UNIT Cycle
t(int)
NOTES: 1. The external signal sets the interrupt flag every time t(int) is met. It may be set even with trigger signals shorter than t(int). The conditions to set the flag must be met independently of this timing constraint. t(int) is defined in MCLK cycles. 2. The external signal needs additional timing because of the maximum input-frequency constraint.
leakage current (see Note 1)

PARAMETER Ilkg(P1.x) Ilkg(P2.x) Leakage current Port P1 Port P2 V(P1.x) (see Note 2) V(P2.3) V(P2.4) (see Note 2) TEST CONDITIONS VCC = 2.2 V/3 V 22 MIN TYP MAX 50 50 UNIT nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 2. The port pin must be selected as input and there must be no optional pullup or pulldown resistor.
16
DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
outputs Ports P1, P2, P3, P4, P5, and P6
PARAMETER TEST CONDITIONS IOH(max) = 1.5 mA, VOH High-level High level output voltage IOH(max) = 6 mA, IOH(max) = 1.5 mA, IOH(max) = 6 mA, IOL(max) = 1.5 mA, VOL Low-level Low level output voltage IOL(max) = 6 mA, IOL(max) = 1.5 mA, IOL(max) = 6 mA, VCC = 2.2 V, VCC = 2.2 V, VCC = 3 V, VCC = 3 V, VCC = 2.2 V, VCC = 2.2 V, VCC = 3 V, VCC = 3 V, See Note 1 See Note 2 See Note 1 See Note 2 See Note 1 See Note 2 See Note 1 See Note 2 MIN VCC0.25 VCC0.6 VCC0.25 VCC0.6 VSS VSS VSS VSS TYP MAX VCC VCC VCC VCC VSS+0.25 VSS+0.6 VSS+0.25 VSS+0.6 V V UNIT
NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed 12 mA to satisfy the maximum specified voltage drop. 2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed 48 mA to satisfy the maximum specified voltage drop.
output frequency
PARAMETER fTAx, fTBx fACLK, fMCLK, fSMCLK TA0..2, TB0..2 Internal clock source, SMCLK signal applied (see Note 1) P5.6/ACLK, P5.4/MCLK, P5.5/SMCLK CL = 20 pF TEST CONDITIONS MIN DC TYP MAX fSystem MHz CL = 20 pF P2.0/ACLK CL = 20 pF, VCC = 2.2 V / 3 V tXdc Duty cycle of output frequency P1.4/SMCLK, P1 4/SMCLK CL = 20 pF, VCC = 2.2 V / 3 V fACLK = fLFXT1 = fXT1 fACLK = fLFXT1 = fLF fACLK = fLFXT1/n fSMCLK = fLFXT1 = fXT1 fSMCLK = fLFXT1 = fLF fSMCLK = fLFXT1/n fSMCLK = fDCOCLK 40% 35% 50% 15 ns 50% 15 ns 50% 50% 40% 30% 50% 60% 65% 50% 15 ns 50% 15 ns fSystem 60% 70% UNIT
NOTE 1: The limits of the system clock MCLK has to be met; the system (MCLK) frequency should not exceed the limits. MCLK and SMCLK frequencies can be different.
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outputs Ports P1, P2, P3, P4, P5, and P6 (continued)
TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE
30 VCC = 2.2 V I OL Low-Level Output Current mA 25 40C 25C 85C 20 I OL Low-Level Output Current mA 50 45 40 35 30 25 20 15 10 5 0 0 0.5 1 1.5 2 2.5 0 0 0.5 1 1.5 2 2.5 3 VOL Low-Level Output Voltage V 3.5 VCC = 3 V 40C 25C 85C
TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE
15
10
VOL Low-Level Output Voltage V
Figure 2
TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE
35 VCC = 2.2 V I OH High-Level Output Current mA 30 25 85C 20 15 25C 40C I OH High-Level Output Current mA 50 85C 40 60
Figure 3
TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE
40C VCC = 3 V
25C 30
20
10 5 0
10
0.5
1.5
2.5
0.5
1.5
2.5
3.5
VOH High-Level Output Voltage V
VOH High-Level Output Voltage V
Figure 4
Figure 5
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DALLAS, TEXAS 75265

wake-up LPM3
PARAMETER TEST CONDITIONS f = 1 MHz t(LPM3) Delay time f = 2 MHz f = 3 MHz VCC = 2.2 V/3 V MIN TYP MAX 6 6 6 s UNIT
RAM
PARAMETER VRAMh TEST CONDITIONS CPU HALTED (see Note 1) MIN 1.6 TYP MAX UNIT V
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution should take place during this supply voltage condition.
Comparator_A (see Note 1)

PARAMETER I(DD) TEST CONDITIONS CAON=1, CARSEL=0 CAON=1 CARSEL=0, CAREF=0 CAON=1, CARSEL=0, CAREF 1/2/3 no load at CAREF=1/2/3, P2.3/CA0/TA1 and P2.4/CA1/TA2 CAON =1 PCA0=1, CARSEL=1, CAREF=1, no load at P2.3/CA0/TA1 and P2.4/CA1/TA2 PCA0=1, CARSEL=1, CAREF=2, no load at P2.3/CA0/TA1 and P2.4/CA1/TA2 PCA0=1, CARSEL=1, CAREF=3, P2 3/CA0/TA1 no load at P2.3/CA0/TA1 and P2.4/CA1/TA2 TA = 85C See Note 2 CAON=1 TA = 25 C, Overdrive 10 mV, 25C, Without filter: CAF=0 t(response LH) TA = 25 C, Overdrive 10 mV, 25C, With filter: CAF=1 TA = 25 C, Overdrive 10 mV, 25C, Without filter: CAF=0 t(response HL) TA = 25 C, Overdrive 10 mV, 25C, With filter: CAF=1 VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V 0 MIN TYP 30 55 40 60 MAX 47 74 57 87 VCC1 0.24 0.25 UNIT A A V
I(Refladder/Refdiode) V(IC) V(Ref025) Common-mode input voltage Voltage at 0.25 V V CC CC node CC node
0.23
V(Ref050)
Voltage at 0.5V V CC
VCC = 2.2 V/3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V
0.47 390 400 30 0 130 80 1.4 0.9 130 80 1.4 0.9
0.48 480 490
0.5 540 mV 550 30 mV mV ns s ns s
V(RefVT) V(offset) Vhys
(see Figure 6 and Figure 7) Offset voltage Input hysteresis
0.7 210 150 1.9 1.5 210 150 1.9 1.5
1.4 300 240 3.4 2.6 300 240 3.4 2.6
NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification. 2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The two successive measurements are then summed together.
DALLAS, TEXAS 75265
19

650 VCC = 3 V V(REFVT) Reference Volts mV V(REFVT) Reference Volts mV 600 Typical 550 600 Typical 550 650 VCC = 2.2 V
500
500
450
450
400 45
25
15
35
55
75
95
400 45
25
15
35
55
75
95
TA Free-Air Temperature C
TA Free-Air Temperature C
Figure 6. V(RefVT) vs Temperature, VCC = 3 V

0V 0 VCC 1 CAON
Figure 7. V(RefVT) vs Temperature, VCC = 2.2 V
CAF
Low Pass Filter + _ 0 1 0 1
To Internal Modules
V+ V
CAOUT Set CAIFG Flag 2.0 s
Figure 8. Block Diagram of Comparator_A Module
Overdrive V
VCAOUT
400 mV V+ t(response)
Figure 9. Overdrive Definition
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DALLAS, TEXAS 75265

PUC/POR
PARAMETER t(POR_Delay) Internal time delay to release POR VCC threshold at which POR release delay time begins (see Note 1) VCC threshold required to generate a POR (see Note 2) RST/NMI low time for PUC/POR TA = 40C TA = 25C TA = 85C VCC |dV/dt| 1V/ms Reset is accepted internally VCC = 2.2 V/3 V 1.4 1.1 0.8 0.2 2 TEST CONDITIONS MIN TYP 150 MAX 250 1.8 1.5 1.2 UNIT s V V V V s
VPOR
V(min) t(reset)
NOTES: 1. VCC rise time dV/dt 1V/ms. 2. When driving VCC low in order to generate a POR condition, VCC should be driven to 200mV or lower with a dV/dt equal to or less than 1V/ms. The corresponding rising VCC must also meet the dV/dt requirement equal to or greater than +1V/ms. V Vcc V
POR POR No POR POR
V (min)
Figure 10. Power-On Reset (POR) vs Supply Voltage

2 1.8 1.6 V POR V 1.4 1.2 1 0.8 0.6 0.4 0.2 0 40 20 0 20 40 60 80 TA Temperature C 25C 0.8 1.2 1.4 1.8 1.5 1.2
Figure 11. VPOR vs Temperature
DALLAS, TEXAS 75265
21

DCO (see Note 1)
PARAMETER f(DCO03) f(DCO13) f(DCO23) f(DCO33) f(DCO43) f(DCO53) f(DCO63) f(DCO73) f(DCO47) f(DCO77) S(Rsel) S(DCO) Dt DV TEST CONDITIONS Rsel = 0, DCO = 3, MOD = 0, DCOR = 0, TA = 25C Rsel = 1, DCO = 3, MOD = 0, DCOR = 0, TA = 25C Rsel = 2, DCO = 3, MOD = 0, DCOR = 0, TA = 25C Rsel = 3, DCO = 3, MOD = 0, DCOR = 0, TA = 25C Rsel = 4, DCO = 3, MOD = 0, DCOR = 0, TA = 25C Rsel = 5, DCO = 3, MOD = 0, DCOR = 0, TA = 25C Rsel = 6, DCO = 3, MOD = 0, DCOR = 0, TA = 25C Rsel = 7, DCO = 3, MOD = 0, DCOR = 0, TA = 25C VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V Rsel = 4, DCO = 7, MOD = 0, DCOR = 0, TA = 25C Rsel = 7 DCO = 7 MOD = 0 DCOR = 0 TA = 25C 7, 7, 0, 0, SR = fRsel+1 / fRsel SDCO = fDCO+1 / fDCO Temperature drift, Rsel = 4, DCO = 3, MOD = 0 (see Note 2) Drift with VCC variation, Rsel = 4, DCO = 3, MOD = 0 (see Note 2) VCC = 2.2 V/3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V/3 V MIN 0.08 0.08 0.14 0.14 0.22 0.22 0.37 0.37 0.61 0.61 1 1 1.6 1.69 2.4 2.7 fDCO40 1.7 4 4.4 1.35 1.07 0.31 0.33 0 TYP 0.12 0.13 0.19 0.18 0.30 0.28 0.49 0.47 0.77 0.75 1.2 1.3 1.9 2.0 2.9 3.2 fDCO40 2.1 4.5 4.9 1.65 1.12 0.36 0.38 5 MAX 0.15 0.16 0.23 0.22 0.36 0.34 0.59 0.56 0.93 0.90 1.5 1.5 2.2 2.29 3.4 3.65 fDCO40 2.5 4.9 5.4 2 1.16 0.40 0.43 10 %/C %/V MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz UNIT
NOTES: 1. The DCO frequency may not exceed the maximum system frequency defined by parameter processor frequency, f(System). 2. This parameter is not production tested. 1 f DCOCLK
Frequency Variance
2.2
22
Max f DCO_0 Min

VCC V
Max f DCO_7 Min
DCO
Figure 12. DCO Characteristics
DALLAS, TEXAS 75265

main DCO characteristics D Individual devices have a minimum and maximum operation frequency. The specified parameters for f(DCOx0) to f(DCOx7) are valid for all devices. D All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps Rsel1, ... Rsel6 overlaps Rsel7. D DCO control bits DCO0, DCO1, and DCO2 have a step size as defined by parameter SDCO. D Modulation control bits MOD0 to MOD4 select how often f(DCO+1) is used within the period of 32 DCOCLK cycles. The frequency f(DCO) is used for the remaining cycles. The frequency is an average equal to: f average + MOD 32 f (DCO) f (DCO)1) f (DCO))(32*MOD) f (DCO)1)
VCC 2.2 V 3V 2.2 V/3 V 2.2 V/3 V MIN TYP 2.015% 2.115% 0.1 10 MAX UNIT MHz MHz %/C %/V
DCO when using ROSC (see Note 1)

PARAMETER fDCO, DCO output frequency Dt, Temperature drift Dv, Drift with VCC variation TEST CONDITIONS Rsel = 4, DCO = 3, MOD = 0, DCOR = 1, TA = 25C Rsel = 4, DCO = 3, MOD = 0, DCOR = 1 Rsel = 4, DCO = 3, MOD = 0, DCOR = 1
NOTES: 1. ROSC = 100k. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and TK = 50ppm/C.
crystal oscillator, LFXT1 oscillator (see Note 1)

PARAMETER CXIN CXOUT VIL VIH Integrated input capacitance Integrated output capacitance Input levels at XIN TEST CONDITIONS XTS=0; LF oscillator selected VCC = 2.2 V/3 V XTS=1; XT1 oscillator selected VCC = 2.2 V/3 V XTS=0; LF oscillator selected VCC = 2.2 V/3 V XTS=1; XT1 oscillator selected VCC = 2.2 V/3 V VCC = 2 2 V/3 V (see Note 2) 2.2 VSS 0.8 VCC MIN TYP 12 2 12 2 0.2 VCC VCC pF V V MAX UNIT pF
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer. 2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
crystal oscillator, XT2 oscillator (see Note 1)

PARAMETER CXIN CXOUT VIL VIH Integrated input capacitance Integrated output capacitance Input levels at XT2IN TEST CONDITIONS VCC = 2.2 V/3 V VCC = 2.2 V/3 V VCC = 2 2 V/3 V (see Note 2) 2.2 VSS 0.8 VCC MIN TYP 2 2 0.2 VCC VCC MAX UNIT pF pF V V
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer. 2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
USART0 (see Note 1)

PARAMETER t( ) () USART0: deglitch time VCC = 2.2 V VCC = 3 V TEST CONDITIONS MIN 200 150 TYP 430 280 MAX 800 500 UNIT ns
NOTE 1: The signal applied to the USART0 receive signal/terminal (URXD0) should meet the timing requirements of t() to ensure that the URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(). The operating conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the URXD0 line.
DALLAS, TEXAS 75265
23

JTAG Interface
PARAMETER fTCK RInternal TCK input frequency Internal pull-up resistance on TMS, TCK, TDI/TCLK TEST CONDITIONS see Note 1 see Note 2 VCC 2.2 V 3V 2.2 V/ 3 V MIN 0 0 25 60 TYP MAX 5 10 90 UNIT MHz MHz k
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected. 2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG Fuse (see Note 1)

PARAMETER VFB IFB tFB Voltage level on TDI/TCLK for fuse-blow Supply current into TDI/TCLK during fuse blow Time to blow fuse TEST CONDITIONS VCC 3.6V MIN 5 TYP MAX 5.5 100 20 UNIT V mA ms
NOTES: 1. Once the fuse is blown, no further access to the MSP430 via JTAG/Test is possible. The JTAG block is switched to bypass mode.
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DALLAS, TEXAS 75265

APPLICATION INFORMATION input/output schematic

port P1, P1.0 to P1.7, input/output with Schmitt trigger
P1SEL.x P1DIR.x Direction Control From Module 0 1 Pad Logic P1OUT.x Module X OUT 0 1 P1.7/TA2 P1.0/TACLK ..
P1IN.x EN Module X IN P1IRQ.x D P1IE.x Q P1IFG.x EN Set Interrupt Edge Select
Interrupt Flag
P1IES.x P1SEL.x
PnSel.x P1Sel.0 P1Sel.1 P1Sel.2 P1Sel.3 P1Sel.4 P1Sel.5 P1Sel.6 P1Sel.7
PnDIR.x P1DIR.0 P1DIR.1 P1DIR.2 P1DIR.3 P1DIR.4 P1DIR.5 P1DIR.6 P1DIR.7
Dir. CONTROL FROM MODULE P1DIR.0 P1DIR.1 P1DIR.2 P1DIR.3 P1DIR.4 P1DIR.5 P1DIR.6 P1DIR.7
PnOUT.x P1OUT.0 P1OUT.1 P1OUT.2 P1OUT.3 P1OUT.4 P1OUT.5 P1OUT.6 P1OUT.7
MODULE X OUT DVSS Out0 signal Out1 signal Out2 signal SMCLK Out0 signal Out1 signal Out2 signal
PnIN.x P1IN.0 P1IN.1 P1IN.2 P1IN.3 P1IN.4 P1IN.5 P1IN.6 P1IN.7
MODULE X IN TACLK CCI0A CCI1A CCI2A unused unused unused unused
PnIE.x P1IE.0 P1IE.1 P1IE.2 P1IE.3 P1IE.4 P1IE.5 P1IE.6 P1IE.7
PnIFG.x P1IFG.0 P1IFG.1 P1IFG.2 P1IFG.3 P1IFG.4 P1IFG.5 P1IFG.6 P1IFG.7
PnIES.x P1IES.0 P1IES.1 P1IES.2 P1IES.3 P1IES.4 P1IES.5 P1IES.6 P1IES.7
Signal from or to Timer_A
DALLAS, TEXAS 75265
25

port P2, P2.0 to P2.2, P2.6, and P2.7 input/output with Schmitt trigger
P2SEL.x P2DIR.x Direction Control From Module P2OUT.x Module X OUT 0 1 0 1 P2.0/ACLK P2.1/TAINCLK P2.2/CAOUT/TA0 P2.6 P2.7/TA0 Bus Keeper 0: Input 1: Output
Pad Logic P2IN.x EN Module X IN P2IRQ.x D P2IE.x P2IFG.x Q EN Set Interrupt Edge Select P2IES.x P2SEL.x CAPD.X
Interrupt Flag
x: Bit Identifier 0 to 2, 6, and 7 for Port P2 Dir. CONTROL FROM MODULE P2DIR.0 P2DIR.1 P2DIR.2 P2DIR.6 P2DIR.7
PnSel.x P2Sel.0 P2Sel.1 P2Sel.2 P2Sel.6 P2Sel.7

PnDIR.x P2DIR.0 P2DIR.1 P2DIR.2 P2DIR.6 P2DIR.7
PnOUT.x P2OUT.0 P2OUT.1 P2OUT.2 P2OUT.6 P2OUT.7
MODULE X OUT ACLK DVSS CAOUT DVSS Out0 signal
PnIN.x P2IN.0 P2IN.1 P2IN.2 P2IN.6 P2IN.7
MODULE X IN unused INCLK CCI0B unused unused
PnIE.x P2IE.0 P2IE.1 P2IE.2 P2IE.6 P2IE.7
PnIFG.x P2IFG.0 P2IFG.1 P2IFG.2 P2IFG.6 P2IFG.7
PnIES.x P2IES.0 P2IES.1 P2IES.2 P2IES.6 P2IES.7
Signal from Comparator_A Signal to Timer_A Signal from Timer_A
26
DALLAS, TEXAS 75265


P2SEL.3 P2DIR.3 Direction Control From Module P2OUT.3 Module X OUT 0 1 0 1 0: Input 1: Output Pad Logic P2.3/CA0/TA1
P2IN.3 EN Module X IN P2IRQ.3 D P2IE.3 P2IFG.3 Q EN Set

Interrupt Edge Select
Bus Keeper
CAPD.3 Comparator_A CAREF CAF + CAEX P2CA
Interrupt Flag P2IES.3 P2SEL.3 CCI1B To Timer_A3 P2SEL.4 P2IES.4 Interrupt Flag P2IFG.4 P2IRQ.4 Module X IN P2IE.4 D EN P2IN.4 Q Set EN
Edge Select Interrupt
CAREF Reference Block
CAPD.4
Bus Keeper
Module X OUT P2OUT.4 From Module Direction Control P2DIR.4 P2SEL.4 DIRECTION CONTROL FROM MODULE P2DIR.3 P2DIR.4
1 0 1 0 Pad Logic 1: Output 0: Input P2.4/CA1/TA2
PnSel.x P2Sel.3 P2Sel.4
PnDIR.x P2DIR.3 P2DIR.4
PnOUT.x P2OUT.3 P2OUT.4
MODULE X OUT Out1 signal Out2 signal
PnIN.x P2IN.3 P2IN.4
MODULE X IN unused unused
PnIE.x P2IE.3 P2IE.4
PnIFG.x P2IFG.3 P2IFG.4
PnIES.x P2IES.3 P2IES.4
Signal from Timer_A
DALLAS, TEXAS 75265
27

port P2, P2.5, input/output with Schmitt trigger and Rosc function for the basic clock module
P2SEL.5 P2DIR.5 Direction Control From Module P2OUT.5 Module X OUT 0 1 0 1 P2.5/Rosc 0: Input 1: Output Pad Logic
Bus Keeper P2IN.5 EN Module X IN P2IRQ.5 D P2IE.5 Q P2IFG.5 EN Set Edge Select Interrupt VCC Internal to Basic Clock Module 0
Interrupt Flag
P2IES.5 P2SEL.5
To DC Generator DCOR CAPD.5
DCOR: Control Bit From Basic Clock Module If it Is Set, P2.5 Is Disconnected From P2.5 Pad DIRECTION CONTROL FROM MODULE P2DIR.5
PnSel.x P2Sel.5
PnDIR.x P2DIR.5
PnOUT.x P2OUT.5
MODULE X OUT DVSS
PnIN.x P2IN.5
MODULE X IN unused
PnIE.x P2IE.5
PnIFG.x P2IFG.5
PnIES.x P2IES.5
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DALLAS, TEXAS 75265

port P3, P3.0 and P3.4 to P3.7, input/output with Schmitt trigger
P3SEL.x P3DIR.x Direction Control From Module 0 1 Pad Logic P3OUT.x Module X OUT 0 1 P3.0/STE0 0: Input 1: Output
P3.4/UTXD0 P3.5/URXD0 P3.6 P3.7
P3IN.x EN Module X IN D
x: Bit Identifier, 0 and 4 to 7 for Port P3 DIRECTION CONTROL FROM MODULE DVSS DVCC DVSS DVCC DVSS
PnSel.x P3Sel.0 P3Sel.4 P3Sel.5 P3Sel.6 P3Sel.7
PnDIR.x P3DIR.0 P3DIR.4 P3DIR.5 P3DIR.6 P3DIR.7
PnOUT.x P3OUT.0 P3OUT.4 P3OUT.5 P3OUT.6 P3OUT.7
MODULE X OUT DVSS UTXD0 DVSS DVSS DVSS
PnIN.x P3IN.0 P3IN.4 P3IN.5 P3IN.6 P3IN.7
MODULE X IN STE0 Unused URXD0 Unused Unused
Output from USART0 module Input to USART0 module
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port P3, P3.1, input/output with Schmitt trigger

P3SEL.1 SYNC MM STC STE P3DIR.1 DCM_SIMO P3OUT1 (SI)MO0 From USART0 0 1 Pad Logic 0 1 P3.1/SIMO0 0: Input 1: Output
P3IN.1 EN SI(MO)0 To USART0 D

P3SEL.2 SYNC MM STC STE P3DIR.2 DCM_SOMI P3OUT.2 SO(MI)0 From USART0 0 1 Pad Logic 0 1 P3.2/SOMI0 0: Input 1: Output
P3IN.2 EN (SO)MI0 To USART0 D
port P3, P3.3, input/output with Schmitt-trigger

P3SEL.3 SYNC MM STC STE P3DIR.3 DCM_UCLK P3OUT.3 UCLK.0 From USART0 0 1 Pad Logic 0 1 P3.3/UCLK0 0: Input 1: Output
P3IN.3 EN UCLK0 D To USART0 NOTE: UART mode: The UART clock can only be an input. If UART mode and UART function are selected, the P3.3/UCLK0 is always an input. SPI, slave mode: The clock applied to UCLK0 is used to shift data in and out. SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave mode).
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P4SEL.x P4DIR.x Direction Control From Module TBOUTHiZ P4OUT.x Module X OUT 0 1 Pad Logic 0 1 0: Input 1: Output
P4.0/TB0 P4.1/TB1 P4.2/TB2 P4.3 P4.4 P4.5 P4.6 Bus Keeper
x: bit identifier, 0 to 6 for Port P4 DIRECTION CONTROL FROM MODULE P4DIR.0 P4DIR.1 P4DIR.2 P4DIR.3 P4DIR.4 P4DIR.5 P4DIR.6
PnSel.x P4Sel.0 P4Sel.1 P4Sel.2 P4Sel.3 P4Sel.4 P4Sel.5 P4Sel.6
PnDIR.x P4DIR.0 P4DIR.1 P4DIR.2 P4DIR.3 P4DIR.4 P4DIR.5 P4DIR.6
PnOUT.x P4OUT.0 P4OUT.1 P4OUT.2 P4OUT.3 P4OUT.4 P4OUT.5 P4OUT.6
MODULE X OUT Out0 signal Out1 signal Out2 signal DVSS DVSS DVSS DVSS
PnIN.x P4IN.0 P4IN.1 P4IN.2 P4IN.3 P4IN.4 P4IN.5 P4IN.6
MODULE X IN CCI0A / CCI0B CCI1A / CCI1B CCI2A / CCI2B Unused Unused Unused Unused
Signal from Timer_B Signal to Timer_B NOTE: TBoutHiZ signal is used by port module P4, pins P4.0 to P4.6. The function TBoutHiZ is mainly used with Timer_B. Port pins P4.3 to P4.6 have the TBoutHiZ function, but no Timer_B output is available for secondary functions. The port selection function can be used to get the port pin to high impedance and to use the P4DIR.x bits.
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P4SEL.7 P4DIR.7 0 1 Pad Logic P4OUT.7 DVSS 0 1 P4.7/TBCLK 0: Input 1: Output
P4IN.7 EN Timer_B, TBCLK D

P5SEL.x P5DIR.x Direction Control From Module 0 1 Pad Logic P5OUT.x Module X OUT 0 1 P5.0 P5.1 P5.2 P5.3 P5.4/MCLK P5.5/SMCLK P5.6/ACLK/ TBOUTH 0: Input 1: Output
x: Bit Identifier, 0 to 7 for Port P5 PnSel.x P5Sel.0 P5Sel.1 P5Sel.2 P5Sel.3 P5Sel.4 P5Sel.5 P5Sel.6 P5Sel.7 PnDIR.x P5DIR.0 P5DIR.1 P5DIR.2 P5DIR.3 P5DIR.4 P5DIR.5 P5DIR.6 P5DIR.7 Dir. CONTROL FROM MODULE DVSS DVCC DVCC DVCC DVCC DVCC DVCC DVSS PnOUT.x P5OUT.0 P5OUT.1 P5OUT.2 P5OUT.3 P5OUT.4 P5OUT.5 P5OUT.6 P5OUT.7 MODULE X OUT DVSS DVSS DVSS DVSS MCLK SMCLK ACLK DVSS PnIN.x P5IN.0 P5IN.1 P5IN.2 P5IN.3 P5IN.4 P5IN.5 P5IN.6 P5IN.7 MODULE X IN unused unused unused unused unused unused unused TBOUTHiZ
NOTE: TBOUTHiZ signal is used by port module P4, pins P4.0 to P4.6. The function of TBOUTHiZ is mainly useful when used with Timer_B.
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P6SEL.x P6DIR.x Direction Control From Module 0 1 0 1 0: Input 1: Output Pad Logic P6.0 .. P6.7 P6OUT.x Module X OUT
Bus Keeper P6IN.x EN Module X IN D
x: Bit Identifier, 0 to 7 for Port P6 DIR. CONTROL FROM MODULE P6DIR.0 P6DIR.1 P6DIR.2 P6DIR.3 P6DIR.4 P6DIR.5 P6DIR.6 P6DIR.7
PnSel.x P6Sel.0 P6Sel.1 P6Sel.2 P6Sel.3 P6Sel.4 P6Sel.5 P6Sel.6 P6Sel.7
PnDIR.x P6DIR.0 P6DIR.1 P6DIR.2 P6DIR.3 P6DIR.4 P6DIR.5 P6DIR.6 P6DIR.7
PnOUT.x P6OUT.0 P6OUT.1 P6OUT.2 P6OUT.3 P6OUT.4 P6OUT.5 P6OUT.6 P6OUT.7
MODULE X OUT DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS
PnIN.x P6IN.0 P6IN.1 P6IN.2 P6IN.3 P6IN.4 P6IN.5 P6IN.6 P6IN.7
MODULE X IN unused unused unused unused unused unused unused unused
NOTE: Direction control bits P6DIR.x and P6SEL.x control whether the port function is active (P6DIR.x=0) or whether the input P6.x is in the high-impedance state. This is identical to the port P6 function in the MSP430F13x devices (used for emulation/prototyping), but different from other digital-only ports such as P5.
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JTAG pins TMS, TCK, TDI, TDO/TDI, input/output with Schmitt trigger
TDO Controlled by JTAG Controlled by JTAG JTAG Controlled by JTAG TDI DVCC TDO/TDI
Fuse Burn & Test Fuse TDI/TCLK DVCC TMS TMS DVCC TCK TCK During Blowing of the Fuse, Pin TDO/TDI Is Used to Apply the Test Input Data for JTAG Circuitry
JTAG fuse check mode MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, ITF , of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated. The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see Figure 13). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition).
Time TMS Goes Low After POR TMS
ITDI/TCLK
ITF
Figure 13. Fuse Check Mode Current
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PACKAGE OPTION ADDENDUM

www.ti.com
5-Dec-2008
PACKAGING INFORMATION
Orderable Device MSP430C1331IPM
(1)
Status (1) ACTIVE
Package Type
Package Drawing
Pins Package Eco Plan (2) Qty TBD
Lead/Ball Finish Call TI
MSL Peak Temp (3) Call TI
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
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MSP430C13x1 MIXED SIGNAL MICROCONTROLLER

SLAS341C SEPTEMBER 2001 REVISED DECEMBER 2008

D Low Supply-Voltage Range, 1.8 V to 3.6 V D Ultralow Power Consumption:

D On-Chip Comparator D Serial Communication Interface (USART), D D D D D

Copyright 2001 2008, Texas Instruments Incorporated

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MSP430C13x1 MIXED SIGNAL MICROCONTROLLER

pin designation, MSP430C1331, MSP430C1351

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MSP430C13x1 MIXED SIGNAL MICROCONTROLLER

functional block diagrams

8 I/O Port 3/4 16 I/Os

I/O Port 1/2 16 I/Os, with Interrupt Capability

I/O Port 5/6 16 I/Os

MCLK MAB, 4 Bit MCB

Test JTAG CPU Incl. 16 Reg.

MAB,MAB, 16-Bit 16 Bit

MDB, 16-Bit MDB, 16 Bit

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MSP430C13x1 MIXED SIGNAL MICROCONTROLLER

Terminal Functions (Continued)

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MSP430C13x1 MIXED SIGNAL MICROCONTROLLER

Table 1. Instruction Word Formats

Table 2. Address Mode Descriptions

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MSP430C13x1 MIXED SIGNAL MICROCONTROLLER

D Low-power mode 0 (LPM0)

D Low-power mode 1 (LPM1)

D Low-power mode 2 (LPM2)

D Low-power mode 3 (LPM3)

D Low-power mode 4 (LPM4)

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MSP430C13x1 MIXED SIGNAL MICROCONTROLLER

(Non)maskable (Non)maskable Maskable

Timer_B3 Comparator_A Watchdog timer USART0 receive USART0 transmit Timer_A3

Maskable Maskable Maskable Maskable Maskable Maskable

0FFF8h 0FFF6h 0FFF4h 0FFF2h 0FFF0h 0FFEEh 0FFECh

I/O port P1 (eight flags)

0FFE8h 0FFE6h 0FFE4h

I/O port P2 (eight flags)

P2IFG.0 to P2IFG.7 (see Notes 1 & 2)

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MSP430C13x1 MIXED SIGNAL MICROCONTROLLER

special function registers

interrupt enable 1 and 2

WDTIE: OFIE: NMIIE: URXIE0: UTXIE0:

interrupt flag register 1 and 2

WDTIFG: OFIFG: NMIIFG:

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MSP430C13x1 MIXED SIGNAL MICROCONTROLLER

module enable registers 1 and 2

URXE0: UTXE0: USPIE0:

oscillator and system clock

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