Analog Testing 02

2
In this chapter...
Analog In-Circuit Testing

Revision Date: 10/07

Introduction To Analog In-Circuit Testing, 2-2 System Sources and Detectors for In-Circuit Testing, 2-5 Basic Analog In-Circuit Measurements, 2-7 Special Analog In-Circuit Measurements, 2-11 Solving In-Circuit Measurement Problems, 2-16 Analog Test Blocks, 2-29 In-Circuit Test Statement Summary, 2-33 The Measuring Operational Amplifier (MOA), 2-36
Know which test statements can be used in analog in-circuit tests. Understand the purpose of the Measuring Operational Amplifier (MOA).
Objectives
This chapter contains information to help you:
Understand how sources and detectors are used for analog in-circuit testing. Have a general understanding of analog in-circuit measurement techniques. Be able correct the following types of measurement errors: source voltage, source loading, guard offset, and current splitting. Understand the process to discharge capacitors. Understand the structure and purpose of analog test blocks.
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Agilent Medalist ICT Systems : Analog Testing
2-1
Introduction To Analog In-Circuit Testing
Analog in-circuit (unpowered) testing verifies that:
analog components are properly loaded on the PC board component values are within specified tolerances.
Block Example provides an example of an analog test blocks.
Basic Hardware for In-Circuit Tests

Figure 2-1 is a block diagram of the basic system hardware used to make analog in-circuit tests. This measurement hardware consists of stimulus sources, a measuring operational amplifier (MOA) circuit, and response detectors. This hardware is located on the ASRU card. There must be an ASRU card in the first slot of each testhead module that is used. The MOA, sources, and detectors are discussed in detail at the end of this chapter. Figure 2-1 Block diagram for an in-circuit test
Device Under Test PC Board Test Fixture Control Card Pin Card
Analog components that can be tested in-circuit include:

capacitors connectors diodes FETs fuses inductors jumpers potentiometers resistors switches transistors zeners
All the analog in-circuit device tests must pass before power is applied to the board under test. The development software automatically generates individual in-circuit tests based on a boards device characteristics and circuit topology. The software compiles the individual tests, called blocks, and places them in the analog directory of the local board directory. During test execution, each test block is executed from the analog subroutine of the testplan. Basic Hardware for In-Circuit Tests shows a block diagram of the measurement hardware and Basic Test
Stimulus Sources I or E AC or DC ASRU Card
Measuring Operational Amplifier Circuit
Response Detectors (A/D) AC / DC or Phase Sync.
2-2
The Control Card manages each in-circuit test by closing the proper testhead relays to connect the device under test into the MOA circuit. Passive and reactive devices, such as resistors and capacitors, are connected into the input path of the MOA. Active devices, such as diodes and transistors, are connected into the feedback loop of the MOA. A test for each type of device is shown in detail in Chapter 3, Analog Tests: Reference. The stimulus sources and response detectors, selected by the test program, are also connected by the Control Card. As the stimulus is applied to the MOA circuit, the response detector measures the output of the MOA and sends the results to the Control Card for evaluation. Depending on the results, the Control Card sends either a pass or fail condition back to the test program.
Basic Test Block Example

An example of a basic analog test block for a resistor test is shown in Example 2-1, and a fragment of the testplan in Example 2-2. This test block, written by the test development software, resides in the analog directory, and is executed from the analog subroutine in the testplan. Each test statement in the Analog_Tests subroutine executes the specified analog test block. The analog test block consists of at least: a connection statement (clear connect or connect), and a measurement statement such as resistor or inductor. The connection statement closes the appropriate relays, and the measurement statement defines the type of measurement, expected value, limits, and measurement options.
Example 2-1
Testplan fragment
! Start of Analog Tests subroutine. ! Execute an analog test block.
sub Analog_Tests test "analog/A24C1" test "analog/A24C2" test "analog/A24L1" test "analog/A24R1" test "analog/A24R2" test "analog/A24Q1" test "analog/A24CR1" subend
! End of Analog Tests subroutine.
2-3
Example 2-2
Analog test block
clear connect s to "R1-1"; i to "R1-2"; g to "R3-1" resistor 10k, 10, 10, re5, wb
By default, the system writes analog in-circuit tests in the following format
disconnect all connect s to "<node name>" connect i to "<node name>" connect g to "<node name>" resistor 10k, 10, 10, re5, wb
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System Sources and Detectors for In-Circuit Testing
This section explains the system sources and detectors for in-circuit testing. The ASRU Card supplies all needed sources and detectors. You can, however, use external instruments by connecting them to the system through the functional ports.
Sources for In-Circuit Testing
Table 2-1 Source DC voltage sources AC voltage sources
ASRU card sources Use Test resistors, channel resistance of FETs, fuses, jumpers, potentiometers, switches. Test capacitors and inductors. Frequencies of the AC sources: 128/1024/8192 Hz. When selecting 128 Hz, always use the ed option, which integrated the measurement over a complete line cycle (normal integration time is insufficient for making valid measurements). Test diodes, zeners, and npn or pnp transistors.
The ASRU Card sources provide stimuli for analog in-circuit and analog functional testing. The sources used for in-circuit testing are listed in Table 2-1. The other ASRU Card sources are used in analog functional (powered) testing. (See Chapter 4, Analog Functional and Mixed Testing.) When the test development software generates a test for a device, it automatically selects the proper stimulus source for that test and sets up the source parameters. These parameters include:

DC current sources
the type of source (AC or DC) the source amplitude in the case of an AC source, the frequency
Detectors for In-Circuit Testing
The output of the MOA must be measured to determine the value of the component being tested. This measurement is accomplished by either the AC voltmeter or the DC voltmeter on the ASRU Card. Other detectors may be used for analog functional (powered) testing as explained in Chapter 4, Analog Functional and Mixed Testing. When the test development software generates a test for a component, it automatically selects the detector needed for the test, and the detector range. Two of the
2-5
detectors are synchronized to the AC sine wave sources. These two detectors are used together to determine the values of reactive components. These synchronized sources and detectors form a phase synchronous detector.
2-6
Basic Analog In-Circuit Measurements
To test analog components, the tester uses a system of measurement buses and relay matrices to connect the component under test into the MOA circuit. The following sections explain these connections:
Guarding (G Bus) Wideband Operation of the MOA
Figure 2-2 illustrates the basic bus and relay arrangement for a simple in-circuit test.
The Source (S) and Input (I) Buses Basic measurement circuit elements for an in-circuit test
Rref S Bus Relay Switchable Reference Resistors I Bus Relay
DC AC
Figure 2-2
Rx I Bus
V Sources S Rx = Rref ( Vs ) -Vmoa
MOA
Vmoa
Detector
To Controller
The Source (S) and Input (I) Buses

In Figure 2-7 on page 2-15, the component under test, Rx, is connected into the input path of the MOA with testhead relays and measurement bus I. For simplification, only one set of relay contacts per bus is shown. ASRU stimulus source Vs, is connected to the other end of the component with the S bus. This connection is made through a second set of relays. Input current, I, flows from the source, Vs, through the component under test to the input of the MOA. Ideally, the input current is limited only by the resistance (or reactance) of the component under test. Because the
Agilent Technologies 2007 Agilent Medalist ICT Systems : Analog Testing
input impedance of an operational amplifier is characteristically very high, most of the input current is forced to flow through reference feedback resistor, Rref. This develops an output voltage, Vmoa, at the output of the MOA, proportional to the values of I and Rref. From the known values of Rref, Vs, and Vmoa, the unknown component value, Rx, can be calculated. The system equation used to calculate the value of the component under test, Rx, is: Vs R x = R ref ------------- V moa
2-7
Even though the output voltage from the MOA is limited by its power supply, a wide range of Rx values can be measured. This is accomplished by switching different values of the reference resistor, Rref, into the feedback path of the MOA. Six different values of precision reference resistors are available on the ASRU card. These resistors are illustrated in Figure 2-2 on page 2-7. By using an AC stimulus source, and an AC detector, reactive components (inductors and capacitors) can also be measured by this technique. Reactive component measurement, called Phase Synchronous Detection, is explained next. Phase Synchronous Detection Phase synchronous detection is used to compensate for the phase shifts that occur in combination resistive/reactive circuits. When the MOA measures a circuit containing resistive and reactive components, the MOA's output contains both a resistive and a reactive component. The real component of the MOA output is directly proportional to the resistive part of the circuit, and the imaginary component is directly proportional to the reactive part of the circuit. The phase synchronous detector is able to distinguish between the real and imaginary parts of the output. This explanation is somewhat simplified, but this is basically the way reactive measurements are made.
under test. These parallel impedance paths cause measurement errors by providing current paths around the component under test. Zsg and Zig, in Figure 2-3, represent the components forming parallel impedance paths around the component under test, Rx. When such parallel paths are formed, parallel current, Ip, flows around Rx and through the MOA feedback path. The added current through the feedback paths cause Rx to appear as a smaller impedance than it actually is.
Guarding (G Bus)
The device under test may have one or more parallel impedance paths due to the circuit topology of the board
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Figure 2-3
S Bus
Parallel resistance paths cause measurement errors

Rx I Rref I+Ip
Vs Zsg Zig Ip MOA Vmoa
The G bus is used to guard the component under test by breaking parallel impedance paths. Figure 2-4 shows where the G bus is connected in the circuit when the component under test is shunted by a parallel impedance path. By connecting the G bus as shown, the current that would flow through both Zsg and Zig becomes insignificant. When the non-inverting input to the MOA is grounded as shown in Figure 2-4, the inverting input becomes a virtual ground due to characteristics of the op amp. This also places the I bus connection at virtual ground. With the G bus also at ground potential, no difference of potential exists across Zig, and no current flows through the parallel path around Rx and through the MOA feedback path. Vs does, however, supply current to Zsg. This current does not affect the measurement as long as the Vs output impedance is very low compared to Zsg. Because there may be one or more parallel paths around the device under test, there may be one or more G bus connections.
2-9
Figure 2-4
S Bus
The G Bus breaks parallel resistance paths

Rx I
Zi g g Zs
I Bus Virtual Ground
Rref
Vs
G Bus Relay MOA Vmoa
Wideband Operation of the MOA

There are two bandwidths, narrow and wide, which affect the gain of the MOA. If no bandwidth is specified, the system uses narrow band. However, wideband can be specified in some measurement situations. Use of wideband increases the amplification bandwidth of the MOA. To implement the wideband feature, the wb option is added to the options field of the appropriate component test statement. For example:
clear connect s to "R1-1"; i to "R1-2" resistor 2k, 1.4, 1.4, wb
Figure 2-5
Wideband (wb) versus narrowband frequency responses
Gain
Wide Band Narrow Band
Frequency
Figure 2-5 illustrates how narrowband and wideband relate to the gain and frequency response of the MOA. Note that the wideband option should not be used when the test includes both the sb option and the re1 or re2 option.
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Special Analog In-Circuit Measurements
Testing devices which are connected in a circuit can require special measurement techniques. The effects of other devices connected to the device under test (DUT) can cause errors in the basic measurement using the S and I buses as described above. Guarding can also introduce measurement error. The three types of errors are:

chapter. To invoke enhancement you must specify the en option in addition to the sa option. The added buses provide the system with a six-wire, in-circuit measurement technique. The extra buses are used only when the measurement situation requires them. Figure 2-6 illustrates the location of these buses in the measurement circuit.
Source Voltage Error Guard Offset Error or Guard Gain Error Current Splitting
There are two techniques that can eliminate or reduce the effect of in-circuit measurement errors. The two techniques are:

Sensing Enhancement
Sensing
Three-wire measurements, using the S, I, and G buses, provide the basic configuration for analog in-circuit testing on the Agilent In-Circuit Test system. However, the addition of three more buses, A, B, and L, help overcome the measurement problems associated with in-circuit testing. Each of the three additional buses is paired with one of the three basic measurement buses, S, I, and G. The buses are paired as follows:
S to A I to B G to L
Sensing the source requires enhancement measurements. Enhancement is explained later in this
2-11
Figure 2-6
Six-wire measurement technique

A Bus Rs
g Zs
Rx
Zi g
Ri B Bus
Rref
Vs L Bus Rg MOA
Any combination of the additional buses, A, B, and L, may be needed for a measurement. This depends on the value of the device under test, measurement accuracy desired (according to the tolerance multiplier that you specified), and circuit topology around the device under test. The basic idea is to eliminate the effects of wire and relay resistance and thermal offset of relay contacts in the measurement circuit. Sensing requires that the appropriate wires be included in the test fixture, the appropriate connections are specified in the test block, and that the appropriate measurement options are included in the measurement statement. The development software includes the sense bus wires in the fixture building files and reports, and adds the appropriate connections and measurement options to the test block. The measurement options are described in Table 2-2.
Table 2-2 Option sa
Measurement options Instructs the test to Sense the source (S bus) with the A bus. The en option must also be used when the sa option is specified. Sense the detector (I bus) with the B bus. Sense the guard (G bus) with the L bus. Use enhancement. This is mandatory when using sa.
sb sl en
The example test block in Example 2-3 shows the connections and the measurement options.
2-12
Example 2-3
Connections and measurement options
clear connect s to "Node_1"; a to "Node_1"; i to "Node_2", b to "Node_2" connect g to "Node_3"; l to "Node_3" resistor 10, 10, 10, sa, sb, sl, en
Sense Methods This section describes the sense methods that can be used on the system to generate more accurate measurements for some in-circuit tests. If you turn on Remote Sensing, the development software determines the sensing needs of each test. Depending on the device under test, topology of the circuitry, and the accuracy of the test desired (according to the tolerance multiplier that you specified when entering board data), any combination of the A, B, and L buses may be required. Example 2-4
If sensing is required, the sense connections can be made in the scanner or they can be made by seperate wires to the board under test. If the remote sensing flag is turned on and the development software determines that they are necessary, seperate sense wires will be used. If adequate sensing can be performed in the sanner, then seperate wires are not required. Example 2-4 shows the differenece between the two sense methods. Notice that the only difference between the G and L sensing levels is in the way that the clear connect statement is constructed.
! This test uses seperate wire S bus sensing. clear connect s to "R1_1"; a to "R1_1"; i to "R1_2"; g to "Q5e" resistor "R1", 10.1k, 2.5, 2.5, sa, en ! This test uses seperate wire S and I bus sensing. clear connect s to "R1_1"; a to "R1_1"; i to "R1_2"; b to "R1_2"; g to "Q5e" resistor "R1", 10.1k, 2.5, 2.5, sa, sb, en ! This test uses testhead level L bus sensing (remote sensing). clear connect s to "R1_1"; i to "R1_2"; gl to "Q5e" resistor "R1", 10.1k, 2.5, 2.5, sl ! This test uses separate wire L bus sensing (remote sensing). clear connect s to "R1_1"; i to "R1_2"; g to "Q5e"; l to "Q5e" resistor "R1", 10.1k, 2.5, 2.5, sl
2-13
Depending on the sensitivity of the measurement, when a seperate sense wire is required you can either connect both the signal and sense wire to the same probe receptacle, or use separate probes. Most of the time, especially with the short wire lengths of the Express test fixtures, you need only a single probe. The development software always assumes a single probe and automatically assigns a resource and fixture wire for the sense bus. If you want to use separate probes, you must add the second probe location manually. Note that when sensing the S bus, you must also use the en (enhancement) option, except for the diode and zener tests.
Enhancement
In difficult situations, you can use a measurement technique known as enhancement. Enhancement makes use of a more complex system measurement equation to compensate for:
The measurement errors caused by the component topology of the board under test. The non-ideal characteristics of the operational amplifier. The thermal offsets of bus and testhead relays.
Enhancement is invoked with the en option in the measurement statement.
Example 2-5
en option example
clear connect s to "R1-1"; a to "R1-1"; i to "R1-2"; b to "R1-2" connect g to "GND"; l to "GND" resistor 100, 2, 2, wb, sa, sb, sl, en
Note that sense a (sa) requires enhancement (en), but enhancement can be used by itself. When enhancement is specified, voltages are measured at the device under test and the reference resistor of the MOA. These measured values, instead of the default values, are used in the formula that determines the value of the device under test. This compensates for the voltage drop across the measurement buses, for thermal offsets created by the system relays, and for DC offsets in an AC measurement.
Figure 2-7 on page 2-15 shows the measurements taken when enhancement is used. For DC measurements, voltages are measured at the four points shown with the source set to zero, and again with the source set to the needed level (eight extra measurements). For AC measurements, voltages are measured at the four points shown with the source signal at zero degrees, again with the source at +90 degrees, and again with the source at -90 degrees (12 extra measurements). The extra measurements of enhancement cause the device test to require significantly more time. If test
2-14
time is a concern, use enhancement only where necessary. Figure 2-7 Enhancement
A Bus B Bus Reference MOA Out Enhancement uses voltage measurements taken at these points.
S Bus
Rx
I Bus
Rref
Vs MOA Vmoa
2-15
Solving In-Circuit Measurement Problems
This section describes how to solve the in-circuit measurement problems discussed earlier. The basic difficulty with in-circuit testing is measuring the actual value of a device on a board under test, when that device is affected by other components in the circuit. In the explanation of the basic measurement circuit, guarding with the G bus was shown to minimize the measurement problems caused by parallel impedance paths. Guarding, however, does not correct all in-circuit measurement errors. In fact, guarding can create problems which must be considered. Additionally, Figure 2-8
Rs I+I1 Vs
fixture wiring, system relays, etc. that connect the component under test into the MOA circuit may also cause measurement problems. The bus wires represent impedances in series with the component to be tested, and testhead relays can appear as temperaturedependent voltage sources. The bimetallic contacts of a relay form a basic thermocouple device. When these contacts are heated, either by current flow or by other heat sources within the system, a temperature dependent output voltage (thermal offset) is generated. Figure 2-8 shows an equivalent circuit, showing bus impedances and thermal offsets generated by the relays.
Bus impedances and thermal offsets cause measurement errors

E Device Under Test Rx
Zi g I 2 g Zs I 1
Ri
Rref I+I2
Vmoa E Rg MOA Too Large
Three major types of measurement errors are caused by the problems illustrated in Figure 2-8. These errors are: source loading (or source voltage error), guard offset error, and current splitting. They are summarized in Table 2-3.
2-16
Table 2-3 Error
Measurement errors Cause Is caused by the thermally induced offset voltages of relay contacts, impedances of the measurement buses, and loading of the stimulus source by small parallel impedances on the board under test. See Source Voltage Error and Solution on page 2-18 and Guard Offset Error and Solution on page 2-21. Is caused by the voltage drop across the impedance of the G bus. This voltage drop appears as an offset voltage at the input terminals of the MOA. Guard offset error is sometimes called guard gain. See Guard Offset Error and Solution on page 2-21. Is caused by a small impedance path in parallel with the input to the MOA, and by an apparent increase in the input impedance of the MOA when AC stimulus sources are used. MOA input impedance increases as the frequency of the source is increased. A large value reference resistor in the MOA feedback path also contributes to current splitting. See Current-Splitting Error and Solution on page 2-24.
Source Voltage Error Guard Offset Error Current Splitting
See also: Discharge Capacitors on page 2-26
2-17
Source Voltage Error and Solution

When measuring a component on the board under test, the stimulus voltage is applied to the component through the series resistance of relay contacts, system cabling, and fixture wiring. All of these resistances Figure 2-9
result in voltage drops that prevent the full value of the stimulus voltage from being applied to the component under test. Figure 2-8 on page 2-16 is a simplified schematic diagram illustrating these impedances.
Bus impedances and thermal offsets cause measurement errors

Rs and Ri are the S and I Bus Impedances Rs Rx Device Under Test Vapplied Source Voltage Error = Vs - Vapplied Ri Rref
Vs
Vmoa MOA Too Small
In Figure 2-9, resistors RS and RI represent the impedances of the S and the I bus, respectively. The voltage drops across these resistances subtract from VS and the remaining voltage is applied across the component under test. This smaller source voltage, Vapplied, across the device under test, results in less feedback current, i, through the feedback resistor, Rref. With less feedback current, the output voltage, Vmoa, is also smaller than expected. This causes the measured value of the component under test to be higher than its actual value. Source voltage error can be reduced by sensing the source with the A bus. Sensing the source also requires enhancement (en). When the A bus is connected and the
measurement options sa and en are specified, the value of the source is measured at the device under test. The measured value, instead of the default value, is used in the formula that determines the value of the device under test. This compensates for the voltage drop across the S bus, for thermal offsets created by the system relays, and for DC offsets in an AC measurement.
2-18
Example 2-6
clear connect s to "R1-1"; a to "R1-1"; i to "R1-2" resistor 2k, 1.4, 1.4, wb, sa, en
Note that the use of the sa option alone does not improve the accuracy of the measurement. The sa option must be accompanied by the enhancement option, en. Source voltage error correction can also be improved by sensing the I bus with the B bus. The B bus connection, shown in Figure 2-10, moves the virtual ground of the MOA to the component under test. This places the Example 2-7 Option sb
impedance of the I bus in series with the reference resistor, Rref. The inverting (-) input to the MOA can no longer sense the voltage drop across the I bus. To incorporate the B bus in an in-circuit test, it must be included in the clear connect or connect statement and the option sb must be specified in the options field of the analog in-circuit test statement.
clear connect s to "R1-1"; a to "R1-1"; i to "R1-2"; b to "R1-2" resistor 2k, 1.4, 1.4, wb, sa, sb, en
Figure 2-10
Use of the B Bus (sb) reduces source voltage error

A/D1
S Bus
A Bus
Rx B Bus Relay
I Bus
Rref
Vs
B Bus MOA Vmoa
2-19
Source Loading and Solution

Source loading, another type of source voltage error, is illustrated in Figure 2-11. When the device under test, Rx, is a small value and is shunted by a small impedance, Zsg, the stimulus source is loaded. The voltage drop across its own internal resistance, represented by Rvs, prevents the full value of Vs from being applied to the component under test. Source Figure 2-11
Rvs
loading error causes the output voltage of the MOA to be too low, just as source voltage error in Figure 2-9 on page 2-18. The resulting MOA output causes a larger measured resistance value than the actual resistance value for the component under test. Because source loading is a source voltage error, you can compensate for source loading the same way as for source voltage error.
Source loading causes a source voltage error

Rs I+I1 Device Under Test Ri Rx
g Zs
Rref I
Vs Rg MOA Vmoa Too Small
2-20
Guard Offset Error and Solution

Use of the G bus was discussed at the beginning of this chapter as a method of breaking parallel resistance paths. Guarding, however, can create a problem of its own called guard offset error. This error is illustrated in Figure 2-12 and Figure 2-13 on page 2-22. The S and I buses have already been shown to exhibit an impedance Figure 2-12 The G Bus causes guard offset error
Rs I+I 1 Vs Device Under Test Rx I
Zi g I 2 g Zs I1
that causes a source voltage error. In a similar manner, the G bus, when connected into the measurement circuit, exhibits an impedance. This impedance is represented by Rg in Figure 2-12. The current through the impedance Zsg causes a voltage drop across Rg. The G bus relay also exhibits a thermal offset which can contribute to measurement errors.
Ri
Rref I+I 2
Verror Vg MOA Rg
Vmoa
Vg = Voltage Drop Across Rg
The voltage drop across Rg causes most of current I2 to flow through Zig as shown. The voltage is multiplied by the ratio of Rref to Zig and appears as an error voltage at the output of the MOA. The equivalent circuit showing how this error voltage appears to the MOA input is illustrated in Figure 2-13. The increase in current through Rref makes the measured value of Rx smaller than its actual value (Vmoa too large).
2-21
Figure 2-13
Equivalent circuit showing Verror caused by the G Bus

Rref
Rx I I+I 2
Vs
Zig I2 Ve Vs = Source Voltage Ve = Error Voltage MOA Vmoa Too Large
The L bus is used to correct for guard offset error. The L bus connects the non-inverting input of the MOA to the G bus connection. This eliminates the offset voltage (the voltage drop across the G bus) normally sensed by the non-inverting input of the MOA. The development software uses the L bus, when it is needed, with the sl Figure 2-14
S Bus
g Zs
option in the statement's measurement option field. Figure 2-14 illustrates the electrical connection of the L bus. If you turned Remote Sensing on, the software determines which tests require sensing of the G bus. The fixture reports include the extra L bus wires.
The L Bus (sl) corrects for guard offset error

Rx
Zi g
I Bus
Rref
Vs
MOA L Bus G Bus
Vmoa
2-22
Unlike the A and B buses, you can use testhead level sensing with the L bus. That is, connect gl to <node> connects the G and L buses together inside the testhead and there is no additional wiring required in the fixture. You can still connect the L bus to the board under test with:
"connect g to <node>; l to <node>"
As with the A and B buses, you can use one probe for both wires or separate probes with the L bus. The software always assumes a single probe, and automatically assigns the resource and fixture wire. To use the L bus in a component test, you must include it in the clear connect, or connect statement, and you must add the sl option to the component test statement:
The development software determines the level of sensing necessary based on device values and topology of the circuit. See the examples below. Example 2-8
! This test uses testhead level sensing. clear connect s to "R1-1"; i to "R1-2"; gl to "R3-2" resistor 2k, 1.4, 1.4, wb, sl ! This test uses separate wires to sense at the device under test. clear connect s to "R1-1"; i to "R1-2"; g to "R3-2"; l to "R3-2" resistor 2k, 1.4, 1.4, wb, sl
2-23
Current-Splitting Error and Solution

Current splitting is another measurement error associated with in-circuit testing. Current splitting is caused when the impedance from the I bus to the G bus, Zig (Figure 2-15) is small compared to the impedance of the I bus and the input of the MOA, Zin. When Zig is small, some of the current that should flow through the feedback resistor, Rref, flows through Zig. The shunted current through Zig causes the MOA output to be too low, causing the measured value of the component under test to be larger than its true value. The reference element, Rref, can contribute to current splitting as well. When a large reference element is used, this increases the resistance of the MOA feedback path. The increase in resistance in the feedback path can cause more current to be shunted through Zig and cause a measurement error. Figure 2-15 Current splitting error
Device Under Test Rs Rx I Vs
Zi g
Current splitting also increases when the frequency of the stimulus source increases. Because the input impedance of an operational amplifier increases as frequency increases, more current is shunted by a small value of Zig, thus increasing the measurement error. There are several methods of reducing or eliminating current splitting error. The first of these is to move virtual ground to the component under test via the B bus, as shown in Figure 2-16. This connection places the impedance of the I bus in series with reference resistor Rref, and prevents the MOA from sensing the voltage drop across the I bus. You can use the B bus by including it in the connect statement and specifying testing option sb in the component test statement, as shown in Example 2-9.
Ri
I 2
Rref I+I 2
Rg MOA
Vmoa
2-24
Example 2-9
Example of the sb option
clear connect s to "R1-1"; a to "R1-1"; i to "R1-2"; b to "R1-2" resistor 2k, 1.4, 1.4, wb, sa, sb, en
Another method of minimizing current splitting is to maximize the MOA input-to-ground impedance. This impedance is represented in Figure 2-16 as Zig. You can modify the connect statement to place the I and G Figure 2-16
S Bus
buses such that the circuit impedance between them is as large as possible. Figure 2-16 illustrates the B bus sense point, as well as the parallel impedance, Zig.
The B Bus (sb) and maximum moa input-to-ground impedance (Zig) reduces current splitting
Rx I I Bus Rref
Vs Maximize Zig
Zig B Bus MOA G Bus Vmoa
Other steps that you can take to reduce current splitting error are: use an AC source, lower the frequency of the source, and change the bandwidth of the MOA. In summary, refer to Figure 2-17. To reduce the effects of current splitting:
increase the gain of the MOA by changing the bandwidth. lower the frequency of the AC source.
minimize Ierr by placing the S and I buses such that maximum circuit impedance is between the I and G buses. minimize the voltage drop across the I bus by using the B bus.
2-25
Figure 2-17
Current splitting solution

Rx I Ierr R I Bus Vs Rref A+1 I
Discharge Capacitors
The discharge capacitors feature lets you discharge capacitors that can affect analog in-circuit tests. Capacitors may already be charged when the board is placed on the fixture, or they may charge as a result of applying sources during in-circuit tests, or applying the DUT power supplies during powered testing. The test development software determines which capacitors need discharging and writes an analog test block that discharges them with the S and G buses. The discharge algorithm attempts to discharge the board to 0.1 volt or less. The maximum voltage that can be discharged is 100 volts. The discharge algorithm returns a variable to indicate its status as shown in Table 2-4. Table 2-4 Value 0 1 2 3 4 5 6 Discharge status Status No discharge needed Discharge successful Voltage too high to discharge (> 100 volts) Charge not decreasing Charge decreasing but did not reach the exit level Unable to make measurement: hardware problem Discharge not executed: over-voltage error
2-26
The discharge algorithm is executed up to four times by these statements:

unpowered All statements that turn on vacuum, such as faon, fbon, and fabon, when executed in the unpowered mode.
necessary depends on the number of nodes that need discharging, the RC time constant of the discharge circuit, and the level of the charge on the board. For tests developed for multiple-board panels, all boards of one type on a panel are discharged as one board. You can add discharge blocks for problem areas. The discharge block is very similar to an analog test block. It is executed by the test (BT-BASIC) statement in the testplan:
test "analog/discharge_C1"; Return
The dps statement executes the discharge algorithm once to remove excess trapped charge from the board. The board might not be discharged all the way to 0.1 volt. These statements execute a dps which includes a single discharge:
All statements that turn on vacuum, such as faon, fbon, and fabon, when executed in the unpowered mode.
scratch board fixture lock cps
As shown in Example 2-10, the discharge block contains a clear connect statement to connect the S and G buses across the capacitor to be discharged, and the discharge statement. The discharge statement includes an optional name, an entry voltage level, an exit voltage level, and an optional return variable. Example 2-10 A typical discharge block
test analog; Return clear connect s to "C1-1"; g to "C1-2" discharge "C1", entry 0.1, exit 0.1, Return end test
and load board
and fixture unlock
and dps and unpowered and learn fixture
powered
autoadjust, confirm, timing
Any statement during which an overvoltage error occurs.

testhead is, testhead power on, testhead power off
and
The discharge requires 0.1 to 0.5 seconds if no discharge is necessary. The time required if a discharge is
Note that the block name must be unique and that if you want to evaluate the result of the discharge test, you must include a return variable. To pass the return variable from the discharge block to the testplan, you must use an explicit block. An explicit block is delimited by the test analog and end test statements.
2-27
The entry voltage level specifies the voltage above which to start discharging (.1 minimum). If the voltage detected on the capacitor is not above this level, no discharging takes place. The exit voltage level specifies the voltage below which to stop discharging (0.005 minimum). If you do not specify the entry and exit voltage levels, the system uses an entry level of 0.1 volt and an exit level of 0.05 volt. A capacitor may discharge, and then, due to dielectric absorption or the circuitry around the capacitor, become charged again. To make sure the capacitor is discharged, you can loop the discharge block until the return variable of the discharge statement is less than or equal to 1:
loop test "analog/discharge_C1"; Return exit if Return <= 1 end loop
To be sure this does not cause an infinite loop, limit the number of times the loop can be executed. If the discharge is still not successful after the maximum number of loops, stop the test:
Count = 1 loop test "analog/discharge_C1"; Return exit if Return <= 1 exit if Count > 10 Count = Count + 1 end loop if Count > 10 then goto Cleanup
Note that the entry voltage level must be greater than or equal to the exit voltage level.
2-28
Analog Test Blocks
Analog Test Blocks
The analog test blocks contain the statements used to connect the device under test into the MOA circuit and execute the measurement. They may also contain an on failure loop to report a failure message, and possibly exit the test. These test blocks reside in the analog directory under the local board directory. For example:
/test_board/analog/r1
Example 2-11 Explicit test block

test analog clear connect s to "R1-1"; i to "R1-2" resistor 10K, 1.4, 1.4, re5, wb end test
Example 2-12 Implicit test block

clear connect s to "R1-1"; i to "R1-2" resistor 10K, 1.4, 1.4, re5, wb
Every test block contains at least a clear connect statement and a measure statement such as resistor or capacitor. Additional statements may be:

test analog end test on failure end on failure report print exit test
The test development software writes only implicit test blocks.
Passing Parameters
Note that implicit test blocks can only use local variables. If you want to pass parameters either into, or out of, the test block you must use an explicit test block. You might want to pass a parameter into a test block to programmatically control some of the measurement options, or pass a parameter from the test block to the testplan to evaluate the result of a measurement. See Example 2-13.
This section describes: Explicit and Implicit Test Blocks Passing Parameters Multiple Measurement Test Blocks Failure and Parallel-Device Reporting
Explicit and Implicit Test Blocks

There are two types of test blocks: explicit and implicit. The explicit blocks are delimited by the test analog and end test statements; the implicit blocks are not delimited.
2-29
Analog Test Blocks
Example 2-13 Passing a parameter to the test block Testplan:

Ed_Flag = 0 test "analog/R1"; Ed_Flag
block. Each measurement must have a unique sub-designator.

Potentiometer Test Block
Test Block:
test analog; Ed_Flag clear connect s to "R1-1"; i to "R1-2" resistor 10K, 1.4, 1.4, re5, wb, ed Ed_Flag end test
Passing a parameter to the testplan: Testplan:

test "analog/R1"; R if R < 7000 then print "R1 Failed"
This is an example of an analog test block for a potentiometer. The 10K ohm potentiometer is measured twice. The first measurement checks the resistance from one leg to the wiper using the ad (adjust) option to allow the operator to center the wiper. The second measurement checks the resistance from the other leg to the wiper without the ad option. The result of both measurements are compared to half the nominal value. The second measurement wider tolerances to accommodate any inaccuracy in the adjustment. Example 2-14 Potentiometer test block
clear connect potentiometer clear connect potentiometer s to "Pin_1"; i to "Leg_1", 5k, 13.2, s to "Wiper"; i to "Leg_2", 5k, 26.3, "Wiper" 12.5, wb, ad "Pin_3" 24.4, wb, ed
Test Block:
test analog; Return clear connect s to "R1-1"; i to "R1-2" resistor 10K, 1.4, 1.4, re5, wb, Return end test
Multiple Measurement Test Blocks

The test development software writes implicit test blocks containing one measurement per block. This is the way all analog in-circuit test blocks should be written, including blocks for elements of a package, such as a resistor pack. The only exception is a test that requires more than one measurement, where one measurement depends on the results of one prior to it. Such is the case for a potentiometer or switch test. In this case, all measurements are included in one test
Notice that each measurement has a unique sub-designator.

Switch Test Block
This is an example of a switch test for a dual single-pole-double-throw switch. One side of each switch is measured for less than 5 ohms with the ad option to allow the operator to set the switch. The other side of each switch is measured to be greater than 100K ohms.
2-30
Analog Test Blocks
Example 2-15 Switch test block

clear connect s switch "Pos_A", clear connect s switch "Pos_B", clear connect s switch "Pos_C", clear connect s switch "Pos_D", to "Node_A"; 5, ad1 to "Node_A"; 100K, op to "Node_D"; 5, ad1 to "Node_D"; 100K, op i to "Node_B" i to "Node_C" i to "Node_E" i to "Node_F"
Example 2-16 Test block with failure report:

on failure report "PART NUM:1145-0916;LOCATION:L2" clear connect s to "R1-1"; i to "R1-2" resistor 10K, 1.4, 1.4, re5, wb
Test block with failure and parallel devices report:

on failure report "PART NUM: 1145-0916; LOCATION: L2" report parallel devices end on failure clear connect s to "R1-1"; i to "R1-2" resistor 10K, 1.4, 1.4, re5, wb
Notice that each measurement has a unique sub-designator.
Failure and Parallel-Device Reporting

You can specify a failure message from within the test block with the on failure loop. If your on failure statement is on one line, you do not need the end on failure; if your on failure statement requires more than one line, you must use the end on failure statement. The test development software places the contents of the failure message field into a report statement in the analog test block. The software also adds a parallel devices report, if the device under test has devices in parallel.
Notice that the one-line on failure statement does not use the end on failure statement. You can have one or more print and report statements, each one cancels the previous one. This is also true for on failure loops.
Exiting the Test on a Failure
Sometimes a test block contains more than one measurement, and each one depends on the results of the one before it. In this case, if the first measurement fails, all following measurements also fail. You can use the exit test statement to exit the test block after the first measurement that fails. This avoids executing all following measurements. Consider Example 2-17.
2-31
Analog Test Blocks
Example 2-17
on failure report "Device failed." exit test end on failure clear connect s to "Node_1"; i to "Node_2" resistor "Div_1", 5k, 13.2, 12.5, wb, R clear connect s to "Node_2"; i to "Node_3" resistor "Div_2", 10k-R, 26.3, 24.4, wb, ed
The second measurement uses the value of R from the first measurement. If the first measurement fails, the second one also fails. In this example the test exits after the first failure. Use the off failure statement to disable an on failure loop.
2-32
In-Circuit Test Statement Summary
Table 2-5 and Table 2-6 on page 2-34 list the statements commonly used with in-circuit tests. These are not meant to be exhaustive lists. Table 2-5 Command capacitor connect-unpowered clear connect-unpowered disconnect-unpowered discharge diode end on failure end test exit test fuse gpconnect gpdisconnect inductor jumper nfetr/pfetr Analog mode Result Measures fixed or variable capacitors. Connects specified buses to nodes or brc's. Disconnects all buses then connects specified buses to nodes or brc's. Disconnects specified nodes or brc's. Discharges capacitors. Measures forward bias diode or zener voltage. Marks the end of an on failure loop. Delimits the end of a test block. Exits a test block. Usually used with an on failure loop. Verifies the presence of fuses. Closes the specified GP relay. This statement coincides with the BT-BASIC gpconnect statement. See the syntax descriptions of both statements for details. Opens the specified GP relay. This statement coincides with the BT-BASIC gpdisconnect statement. See the syntax descriptions of both statements for details. Measures fixed or variable inductors. Verifies the presence of jumpers. Measures Ron of N-channel and P-channel FETs.
2-33
Table 2-5 Command npn/pnp off failure on failure
Analog mode (continued) Result Calculates the gain of npn and pnp transistors by measuring two values of DC base current. Turns off an active on failure statement. Marks the start of an on failure loop. Measures potentiometer resistance. Outputs a message to the printer is device. Outputs a message to the report is device. Measures fixed or variable resistors. Verifies the contact position of a switch. Delimits the start of a test block. Measures zener reverse breakdown voltage.
potentiometer print report resistor switch test analog zener
Table 2-6 Command analog gpconnect
BT-BASIC Result Invokes the analog mode. Closes specified general purpose relays. Opens specified general purpose relays. Turns off the capacitance learning.
gpdisconnect learn capacitance off
2-34
Table 2-6 Command
BT-BASIC (continued) Result Turns on the capacitance learning. The capacitance compensation is activated for the tests that are executed from the testplan between this statement and the following learn capacitance off statement. Specifies a wait interval, in seconds, between applying a stimulus and taking a reading for all analog in-circuit tests. Specifies the printer device. Specifies the report device. Executes the specified test block. Continues a test after a pause. Changes the test limits specified in the in-circuit test statements. The tolerance margin statement can be used to increase or decrease the test limits. If no value is specified, the value used is 0. Initializes the system to execute in-circuit test statements, and executes the capacitor discharge block.
learn capacitance on
minimum wait printer is report is test test cont tolerance margin
unpowered
2-35
The Measuring Operational Amplifier (MOA)
The ASRU Card contains the sources, detectors, and the MOA circuit used for in-circuit testing. Figure 2-18 Figure 2-18 Analog in-circuit test configuration
Rx
shows the basic hardware configuration for performing an analog in-circuit test.
PC Board Test Fixture Control Card Pin Card Testhead Relays
ASRU Relay
Rref ASRU Relay
Vs Source MOA Detector
MOA Circuit on the ASRU Card
The component under test is represented by resistor Rx. Under control of the test program, Pin Card and ASRU Card relays switch the component to be tested into the MOA circuit. When stimulus source voltage, Vs, is applied, the MOA output is measured by a detector to determine the value of the component, Rx.
For more details, see the following topics: Understanding the Operational Amplifier Basic Op-Amp Equations
2-36
Understanding the Operational Amplifier

To understand how the MOA on the ASRU Card is used to test analog components, an understanding of the operational amplifier (op-amp) circuit is necessary. Understanding the op-amp and how it is used as a measurement tool by the Agilent In-Circuit Test System is useful when you are verifying and editing component tests. It also helps you identify possible measurement problems caused by circuit topology on the board under test. The electrical characteristics of the operational amplifier make it ideal for testing analog components. An ideal op-amp exhibits the following:

Assuming ideal characteristics for the op-amp, the textbook gain formula for an op-amp is: ( V s R ref ) V moa = -----------------Rx where Vmoa is the output voltage of the op-amp, Vs is the input (stimulus) voltage, Rx is the component under test, and Rref is the feedback resistor. However, the voltage gain equation does not take into account some of the non-ideal circuit conditions. Figure 2-19 illustrates a basic op-amp circuit, and some non-ideal circuit conditions in terms of currents and voltages.
Infinite gain. Infinite bandwidth. Infinite input impedance. Zero input current. Amplifier parameters (gain, bandwidth, etc.) are stable at all temperatures.
These characteristics are the reason the operational amplifier is selected to perform measurements rather than a voltmeter or an ohmmeter. Those instruments can give erroneous results when doing in-circuit measurements because they cannot compensate for components in parallel with the component under test. In comparison to these instruments, the op-amp can use small stimulus voltages when performing tests. The DC stimulus voltage for an in-circuit test is 0.1 volt. Using such a small stimulus prevents any PN junctions in surrounding devices from being turned on.
2-37
Figure 2-19
Currents and voltages in a basic op amp circuit

Rx I Summing Node N Ib Vin MOA Vmoa Rref I-Ib
Vs Source Voltage
The basic circuit components consist of the op-amp, an input resistor, Rx, and a feedback resistor, Rref. If a source voltage, Vs, is applied at the circuit input, current I flows through Rx. This current also flows into the summing node, N. If the op-amp exhibits the ideal characteristic of an infinite input impedance, all of the current, I, also flows through the feedback resistor, Rref. However, because no op-amp is perfect, a very small bias current, Ib, flows into the inverting input. Ib is considered an error current because ideally, all of the current should flow through the feedback resistor. The remaining current, (I -Ib), flows through the feedback resistor, Rref. Figure 2-19 also illustrates the voltages in the op-amp circuit. The voltage drop Vin is an error voltage across the inputs of the op-amp caused by the error current Ib. Vmoa is the output voltage of the op-amp.
Basic Op-Amp Equations

Some basic equations can be derived from the current flow and voltages in the op-amp circuit. From Kirchoff's current law, the sum of currents entering and leaving a node equals zero. Therefore, referring to Figure 2-19: (1) (2) (3) I at summing node N = 0 I = Ib + ( I Ib ) ( V s V in ) ---------------------- = I Rx ( V in V moa ) ---------------------------- = ( I I b ) R ref
(4)
Equations (3) and (4) are derivations of Ohm's Law (I = E/R). Equation (2) can be rewritten using equations (3) and (4) by substituting values for I and (I - Ib).
2-38
(5)
( V s V in ) ( V in V moa ) ---------------------- = I b + ---------------------------Rx R ref
If both sides of equation (5) are divided by (Vs - Vin), the new equation is: (6) I b + ( V in V moa ) 1 ----- = -------------------------------------Rx ( V s V in )R ref
Equation (9), however, does not always work for all in-circuit measurements. The component topology of the board under test can sometimes exaggerate the non-ideal characteristics of the op-amp, and the MOA circuit in general. When the system encounters a difficult measurement situation, an expanded equation equivalent to equation (7) is used. Use of the expanded measurement equation is referred to as Enhancement.
The value of Rx can be found by inverting both sides of equation (6) which gives the equation: (7) ( V s V in )R ref R x = -------------------------------------I b + ( V in V moa )
To further simplify equation (7), some assumptions can be made concerning the MOA circuit. The first of these assumptions is that the error current Ib is so small that it is insignificant, and this value in the equations can be set to zero. If Ib is small, then the voltage drop it causes, Vin, is also small enough to be insignificant, so it too can be set to zero. These assumptions are shown in equation (8). (8) ( V s R ref ) R x = ------------------ V moa
Equation (8) is the one most often used by the system to calculate the value of Rx, and is merely a transposed version of the op-amp voltage gain equation: (9) ( V s R ref ) V moa = ---------------------Rx
2-39

Analog Testing 02

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Analog In-Circuit Testing

Agilent Technologies 2007

Agilent Medalist ICT Systems : Analog Testing

Introduction To Analog In-Circuit Testing

Introduction To Analog In-Circuit Testing

Analog in-circuit (unpowered) testing verifies that:

Block Example provides an example of an analog test blocks.

Basic Hardware for In-Circuit Tests

Analog components that can be tested in-circuit include:

Stimulus Sources I or E AC or DC ASRU Card

Measuring Operational Amplifier Circuit

Response Detectors (A/D) AC / DC or Phase Sync.

Agilent Technologies 2007

Agilent Medalist ICT Systems : Analog Testing

Introduction To Analog In-Circuit Testing

Basic Test Block Example

! End of Analog Tests subroutine.

Agilent Technologies 2007

Agilent Medalist ICT Systems : Analog Testing

Introduction To Analog In-Circuit Testing

Analog test block

Agilent Technologies 2007

Agilent Medalist ICT Systems : Analog Testing

System Sources and Detectors for In-Circuit Testing

System Sources and Detectors for In-Circuit Testing

Table 2-1 Source DC voltage sources AC voltage sources

Detectors for In-Circuit Testing

Agilent Technologies 2007

Agilent Medalist ICT Systems : Analog Testing

System Sources and Detectors for In-Circuit Testing

Agilent Technologies 2007

Agilent Medalist ICT Systems : Analog Testing

Basic Analog In-Circuit Measurements

Basic Analog In-Circuit Measurements

Guarding (G Bus) Wideband Operation of the MOA

V Sources S Rx = Rref ( Vs ) -Vmoa

The Source (S) and Input (I) Buses

Basic Analog In-Circuit Measurements

Basic Analog In-Circuit Measurements

Parallel resistance paths cause measurement errors

Vs Zsg Zig Ip MOA Vmoa

Agilent Technologies 2007

Agilent Medalist ICT Systems : Analog Testing

Basic Analog In-Circuit Measurements

The G Bus breaks parallel resistance paths

I Bus Virtual Ground

G Bus Relay MOA Vmoa

Wideband Operation of the MOA

Wideband (wb) versus narrowband frequency responses

Agilent Technologies 2007

Agilent Medalist ICT Systems : Analog Testing

Special Analog In-Circuit Measurements

Special Analog In-Circuit Measurements

Agilent Technologies 2007

Agilent Medalist ICT Systems : Analog Testing

Special Analog In-Circuit Measurements

Six-wire measurement technique

Table 2-2 Option sa

Agilent Technologies 2007

Agilent Medalist ICT Systems : Analog Testing

Special Analog In-Circuit Measurements

Connections and measurement options