Introduction to Computer Aided Design

Architecture of FPGAs (2)

Introduction to CAD
Naehyuck Chang
naehyuck@snu.ac.kr

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Introduction (1)
• MPGA versus FPGA
– Similarity
• Consisting of an array of logic blocks that can be
programmably interconnected to realize different
designs
– MPGA
• Programmed using IC fabrication to form metal
interconnection
– FPGA
• Programmed via electrically programmable switches
Seoul National University
Dept. of Computer Engineering
Introduction to Computer Aided Design

Introduction (2)
• PLD versus FPGA
– PLD
• Simple but inefficient crossbar like structure
• Implemented using predominantly two-level AND-
OR logic with wide input AND gates
– FPGA
• More efficient MPGA-like routing
• Implemented using multiple level of lower fanin
gates
Seoul National University
Dept. of Computer Engineering
Introduction to Computer Aided Design

Introduction (3)
• Type of programmable switch
• Logic Block Architecture
• Routing Architecture

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Type of programmable switch (1)

• SRAM
– Switch is a pass transistor controlled by the
state of a SRAM bit

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Type of programmable switch (2)

• Antifuse
– When electrically programmed, forms a low
resistance path

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Type of programmable switch (3)

• EPROM
– Switch is a floating-gate transistor that can be
turned off by injecting charge onto their
floating gate

Seoul National University

Dept. of Computer Engineering
 Introduction to Computer Aided Design

Summary of programmable switch (1)

• Performance
– Dependent on area and parasitic resistance and
capacitance
– To improve performance
• The appropriate granularity and functionality of the
logic block
• The routing architecture to achieve a high degree of
routability

Seoul National University

Dept. of Computer Engineering
 Introduction to Computer Aided Design

Summary of programmable switch (2)

• Performance (contd.)
– No one architecture is likely to be best suited
for all programming technologies and for all
design

Seoul National University

Dept. of Computer Engineering
 Introduction to Computer Aided Design

Summary of programmable switch (3)

# Extra
Technology R(ohm) C(fF)
Volatile Re-Program Area Fab
and Process (on switch) (parasitic)
Steps
SRAM
Mux
Yes Yes in circuit Large 0.5 - 2k 10 - 20 fF 0
Pass Transistor
1.2um CMOS
Fuse small
ONO
(via)
Anti-fuse No No 300 - 500 5 fF 3
Orig. Tran.
1.2um CMOS
Large
Fuse small
Amorphous
(via)
Anti-fuse No No 50 - 100 1.1 - 1.3 fF 3
Orig. Tran.
1.2um CMOS
Large
EPROM
No Yes out of circuit Small in array 2 - 4k 10 - 20 fF 3
1.2um CMOS
EEPROM
No Yes in circuit 2x EPROM 2 - 4k 10 - 20 fF >5
1.2um CMOS

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Overview of Logic Block

Architecture (1)
• Low level architecture
– Transistor pairs
– Basic small gates such as two-input NAND’s or
XOR’s
– Multiplexers
– Look-up tables
– Wide-fanin AND-OR structures

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Overview of Logic Block

Architecture (2)
• Ways to define the granularity of logic
block
– # of Boolean functions that can be implemented
– # of equivalent two-input NAND gates
– Total number of transistors
– Total normalized area
– # of inputs and outputs

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Overview of Logic Block

Architecture (3)
• Fine-Grain Logic Block
• Coarse-Grain Logic Block

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Fine-Grain Logic Blocks (1)

• The Plessey logic block

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Coarse-Grain Logic Blocks (1)

• The Actel Act-1 logic block

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Coarse-Grain Logic Blocks (2)

• The Actel Act-2 logic block

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Coarse-Grain Logic Blocks (3)

• The Quicklogic logic block

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Coarse-Grain Logic Blocks (4)

• Look-up table-based logic

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Coarse-Grain Logic Blocks (5)

• The Xilinx 3000 logic block

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Coarse-Grain Logic Blocks (6)

• The Xilinx 4000 logic block

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Coarse-Grain Logic Blocks (7)

• The Altera 5000 Series logic block

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Summary of LB’s granularity (1)

• Effect of Granularity on Density
– Trade-off between # of blocks and area needed
to implement design

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Summary of LB’s granularity (2)

• Number of blocks and block area for one
circuit

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Summary of LB’s granularity (3)

• Number of blocks and routing area/block, for one
design

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Summary of LB’s granularity (4)

• Average normalized total area versus K for a K-
LUT

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Summary of LB’s granularity (5)

• Two implementations of a same logic function

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Summary of LB’s granularity (4)

• Average number of logic block levels and block
delay for K-LUT’s

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

• Net delay versus K, number of inputs to lookup

table

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Summary of LB’s granularity (5)

• Critical path delay versus K, number of inputs

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Summary of LB’s granularity (6)

• Best performance K versus Ts

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Overview of Routing
Architecture (1)
• Low level architecture
– Wire segments of varying length and
programmable switch

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Overview of Routing
Architecture (1)
• Density and performance
– Dependent on distribution of wire segments
• If all segment is too long, implementing local
interconnections becomes too costly in area and
delay
• If all segment is too short, implementing long
interconnections use too may switch, resulting in
large delay

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Routing Architecture (1)

• General FPGA routing architecture

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Routing Architecture (2)

• Xilinx 3000 routing Xilinx 4000 segments of length 2
architecture

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Routing Architecture (3)

• Actel Routing architecture

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Routing Architecture (4)

Altera MAX 5000 global routing Altera 5000 local routing
architecture architecture

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Routing Architecture (5)

• Plessy routing architecture

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Summary of routing architecture

(1)
• Percent routing completion versus Fc, one circuit

Seoul National University

Dept. of Computer Engineering
Introduction to Computer Aided Design

Summary of routing architecture

(2)
• Average Number of Switches Average Excess Tracks for Each
per Logic Block Tile for Each Routing Architecture
Routing Architecture

Seoul National University

Dept. of Computer Engineering