VHDL PROGRAMME IN DATAFLOW

1.BAND GATE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity band is Port ( a,b,c,d : in STD_LOGIC; y : out STD_LOGIC); end band; architecture dataflow of band is begin y<=(not a)and(not b)and(not c)and(not d); end dataflow;

2.BOR GATE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bor_3 is Port ( a,b,c : in STD_LOGIC; y : out STD_LOGIC); end bor_3; architecture dataflow of bor_3 is begin y<=(not a)or(not b)or(not c); end dataflow;

3. 2 BIT COMPARATOR library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity comp_2 is Port ( a,b : in STD_LOGIC; eq,less,greater : out STD_LOGIC); end comp_2; architecture dataflow of comp_2 is begin eq<=a xnor b; less<=(not a)and b; greater<=a and (not b); end dataflow; 4.BNAND GATE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bnand is Port ( a,b,c,d,e,f,g : in STD_LOGIC; y : out STD_LOGIC); end bnand; architecture dataflow of bnand is begin y<=(((((((not a)nand(not b))nand(not c))nand(not d))nand(not e))nand(not f))nand(not g)); end dataflow;

5.BUFFER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity buffer_1 is Port ( a : in STD_LOGIC; y : out STD_LOGIC); end buffer_1; architecture dataflow of buffer_1 is begin y<=a; end dataflow; 6.D_MUX library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity demux_18 is Port ( a : in STD_LOGIC; s : in STD_LOGIC_VECTOR (3 downto 0); y : out STD_LOGIC_VECTOR (7 downto 0)); end demux_18; architecture dataflow of demux_18 is begin y(0)<=a and(not s(2))and(not s(1))and(not s(0)); y(1)<=a and(not s(2))and(not s(1))and s(0); y(2)<=a and(not s(2))and s(1) and(not s(0)); y(3)<=a and(not s(2))and s(1)and s(0); y(4)<=a and s(2)and(not s(1))and(not s(0)); y(5)<=a and s(2)and(not s(1))and s(0); y(6)<=a and s(2)and s(1)and(not s(0)); y(7)<=a and s(2)and s(1)and s(0); end dataflow;

7. BCD-EXCESS3 CODE CONVERTER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity excess_3 is Port ( b3,b2,b1,b0 : in STD_LOGIC; e : out STD_LOGIC_VECTOR (3 downto 0)); end excess_3; architecture dataflow of excess_3 is begin e(3)<=b3 or (b2 and b0)or(b2 and b1); e(2)<=(b2 and b1 and b0)or (b3 and b2)or((not b2)and b0)or((not b2)and b1); e(1)<=((not b1)and(not b0))or(b3 and b2)or(b1 and b0); e(0)<=(not b0); end dataflow; 8. FULL SUBTRACTOR library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fsub is Port ( a,b,c : in STD_LOGIC; diff,borrow : out STD_LOGIC); end fsub; architecture dataflow of fsub is begin diff<=a xor b xor c; borrow<=((not a)and b)or((not a)and c)or(b and c); end dataflow;

9.BINARY TO GRAY CODE CONVERTER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity grey is Port ( b : in STD_LOGIC_VECTOR (3 downto 0); g : out STD_LOGIC_VECTOR (3 downto 0)); end grey; architecture dataflow of grey is begin g(3)<=b(3); g(2)<=b(3)xor b(2); g(1)<=b(2)xor b(1); g(0)<=b(1)xor b(0); end dataflow; 10. HALF SUBTRACTOR library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity hsub is Port ( a,b : in STD_LOGIC; d,bo : out STD_LOGIC); end hsub; architecture dataflow of hsub is begin d<=a xor b; bo<=(not a)and b; end dataflow;

11. INVERTER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity inverter_1 is Port ( a : in STD_LOGIC; y : out STD_LOGIC); end inverter_1; architecture dataflow of inverter_1 is begin y<=not a; end dataflow; 12.MUX 4:1 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux_4 is Port ( a,b,c,d : in STD_LOGIC; s : in STD_LOGIC_VECTOR (1 downto 0); y : out STD_LOGIC); end mux_4; architecture dataflow of mux_4 is begin y<=((not s(1))and (not s(0)) and a)or((not s(1))and s(0))or( s(1)and not s(0)) or(s(1)and s(0)); end dataflow;

13. NOR GATE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity nor_2 is Port ( a,b : in STD_LOGIC; y : out STD_LOGIC); end nor_2; architecture dataflow of nor_2 is begin y<=a nor b; end dataflow; 14. RS NOR LATCH library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sr_nor is Port ( s,r : in STD_LOGIC; q,nq : inout STD_LOGIC); end sr_nor; architecture dataflow of sr_nor is begin q<=r nor nq; nq<=s nor q; end dataflow;

VHDL PROGRAMME IN BEHAVIORIAL 1. BINARY TO GRAY(WHEN..ELSE) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --------------------------------------------------entity bitogr is port(b:in std_logic_vector(3 downto 0); g:out std_logic_vector(3 downto 0)); end bitogr; --------------------------------------------------architecture behavioural of bitogr is begin g<="0000" when b="0000" else "0001" when b="0001" else "0011" when b="0010" else "0010" when b="0011" else "0110" when b="0100" else "0111" when b="0101" else "0101" when b="0110" else "0100" when b="0111" else "1100" when b="1000" else "1101" when b="1001" else "1111" when b="1010" else "1110" when b="1011" else "1010" when b="1100" else "1011" when b="1101" else "1001" when b="1110" else "ZZZZ; end behavioural;

2. 1 BIT COMPARATOR(IF THEN ELSIF)

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --------------------------------------------------entity comp_1 is port(a,b:in std_logic; e,l,g:out std_logic); end comp_1; --------------------------------------------------architecture behavioural of comp_1 is begin process (a,b) begin if(a=b) then e<='1'; l<='0'; g<='0'; elsif(a<b ) then e<='0'; l<='1'; g<='0'; else e<='0'; g<='1'; l<='0'; end if; end process; end behavioural;

3. 1 BIT COMPARATOR( IFTHENELSE) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --------------------------------------------------entity comp_2 is port(a,b:in std_logic_vector (1 downto 0); e,l,g:out std_logic); end comp_2; --------------------------------------------------architecture behavioural of comp_2 is begin process ( a,b ) begin if (a=b) then e<='1'; else e<='0'; end if; if (a>b) then g<='1'; else g<='0'; end if; if(a<b) then l<='1'; else l<='0'; end if; end process; end behavioural; 4.4BIT COMPARATOR ( IF THENELSE) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --------------------------------------------------entity comp_4 is port(a,b:in std_logic_vector (3 downto 0); e,l,g:out std_logic); end comp_4; --------------------------------------------------architecture behavioural of comp_4 is

begin process ( a,b ) begin if (a=b) then e<='1'; else e<='0'; end if; if (a>b) then g<='1'; else g<='0'; end if; if(a<b) then l<='1'; else l<='0'; end if; end process; end behavioural; 5. 1 BIT COMPARATOR (IF..THEN..ELSE IF) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --------------------------------------------------entity comp_12 is port(a,b:in std_logic; e,l,g:out std_logic); end comp_12; --------------------------------------------------architecture behavioural of comp_12 is begin process (a,b) begin if(a=b) then e<='1'; l<='0'; g<='0'; else if(a<b ) then e<='0'; l<='1'; g<='0'; else if(a>b) then

e<='0'; g<='1'; l<='0'; end if; end if; end if;

end process; end behavioural; 6. 2 BIT COMPARATOR(IF THEN ELSIF) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --------------------------------------------------entity comp_22 is port(a,b:in std_logic_vector(1 downto 0); e,l,g:out std_logic); end comp_22; --------------------------------------------------architecture behavioural of comp_22 is begin process (a,b) begin if(a=b) then e<='1'; l<='0'; g<='0'; elsif(a<b ) then e<='0'; l<='1'; g<='0'; else e<='0'; g<='1'; l<='0'; end if; end process; end behavioural;

7. 2 BIT COMPARATOR(IF THEN ELSE IF) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --------------------------------------------------entity comp_23 is port(a,b:in std_logic_vector(1 downto 0); e,l,g:out std_logic); end comp_23; --------------------------------------------------architecture behavioural of comp_23 is begin process (a,b) begin if(a=b) then e<='1'; l<='0'; g<='0'; else if(a<b ) then e<='0'; l<='1'; g<='0'; else if(a>b) then e<='0'; g<='1'; l<='0'; end if; end if; end if; end process; end behavioural; 8. D MUX (IF THEN ELSE IF ) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity demux1_8 is port(x,y,z,i :in std_logic; y0,y1,y2,y3,y4,y5,y6,y7 : out std_logic); end demux1_8 ;

architecture behavioral of demux1_8 is begin process(x,y,z,i) begin if(x='0' and y='0'and z='0')then y0<=i; else if(x='0' and y='0'and z='1')then y0<=i; else if(x='0' and y='1'and z='0')then y0<=i; else if(x='0' and y='1'and z='1')then y0<=i; else if(x='1' and y='0'and z='0')then y0<=i; else if(x='1' and y='0'and z='1')then y0<=i; else if(x='1' and y='1'and z='0')then y0<=i; else y0<=i; end if; end if; end if; end if; end if; end if; end if; end process; end behavioral; 9. FULL ADDER library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity fulladd is port(a,b,c :in std_logic; s,ca : out std_logic); end fulladd ; architecture behavioral of fulladd is begin process(a,b,c) begin if(a='0' and b='0' and c='1')or(a='0' and b='1' and c='0')or(a='1' and b='0' and c='0')or(a='1' and b='1' and c='1') then s<='1';

else s<='0'; end if; if(a='0' and b='1' and c='1')or(a='1' and b='0' and c='1')or(a='1' and b='1' and c='0')or(a='1' and b='1' and c='1') then ca<='1'; else ca<='0'; end if; end process; end behavioral; 10. FULL SUBTRACTOR library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity fullsub is port(a,b,c :in std_logic; d,bo : out std_logic); end fullsub ; architecture behavioral of fullsub is begin process(a,b,c) begin if(a='0' and b='0' and c='1')or(a='0' and b='1' and c='0')or(a='1' and b='0' and c='0')or(a='1' and b='1' and c='1') then d<='1'; else d<='0'; end if; if(a='0' and b='0' and c='1')or(a='0' and b='1' and c='0')or(a='0' and b='1' and c='1')or(a='1' and b='1' and c='1') then bo<='1'; else bo<='0'; end if; end process; end behavioral;

11.HALF ADDER library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

entity halfadd is port(a,b :in std_logic; s,ca : out std_logic); end halfadd ; architecture behavioral of halfadd is begin process(a,b) begin if(a=b) then s <= '0'; else s<='1'; end if; if(a='1' and b='1') then ca<='1'; else ca<='0'; end if; end process; end behavioral; 12. HALF SUBTRACTOR library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity halfsub is port(a,b :in std_logic; d,bo : out std_logic); end halfsub ; architecture behavioral of halfsub is begin process(a,b) begin if(a=b) then d <= '0'; else d<='1'; end if; if(a='0' and b='1') then bo<='1'; else bo<='0'; end if; end process; end behavioral;

13. D MUX ( IF THEN ELSIF) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity demux_41 is port(a :in std_logic_vector(1 downto 0); i :in std_logic; y0,y1,y2,y3 : out std_logic); end demux_41 ; architecture behavioral of demux_41 is begin process(a,i) begin case if(a='0' and b='0' and c<='0') then y0<=i; elsif(a='0' and b='0' and c<='1') then y1<=i; elsif(a='0' and b='1' and c<='0') then y2<=i; elsif(a='0' and b='1' and c<='1') then y3<=i; elsif(a='1' and b='0' and c<='0') then y4<=i; elsif(a='1' and b='0' and c<='1') then y5<=i; elsif(a='1' and b='1' and c<='0') then y6<=i; elsif(a='1' and b='1' and c<='1') then y7<=i; end if; end process; end behavioral; 14.FULL SUBTRACTOR library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity fullsub is port(a,b,c :in std_logic; d,bo : out std_logic); end fullsub ; architecture behavioral of fullsub is begin process(a,b,c)

begin if(a='0' and b='0' and c='1')or(a='0' and b='1' and c='0')or(a='1' and b='0' and c='0')or(a='1' and b='1' and c='1') then d<= '1'; else d<='0'; end if; if(a='0' and b='1')then bo<= '1'; elsif(a='0' and b='1' and c='1')then bo<='1'; elsif(a='1' and b='1' and c='1')then bo<=1; else bo<=0; end if; end process; end behavioral; 15. BINARY TO EXCESS3 (CASE) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity binarytoxs3 is port(a :in std_logic_vector(3 downto 0); y : out std_logic_vector(3 downto 0)); end binarytoxs3 ; architecture behavioral of binarytoxs3 is begin process(a) begin case a is when "0000"=> y<="0011"; when "0001"=> y<="0100"; when "0010"=> y<="0101"; when "0011"=> y<="0110"; when "0100"=> y<="0111"; when "0101"=> y<="1000"; when "0110"=> y<="1001"; when "0111"=> y<="1010"; when "1000"=> y<="1011"; when "1001"=> y<="1100"; end case; end process; end behavioral;

16. DMUX 1:2 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity demux_12 is port(a,i :in std_logic; y0,y1 : out std_logic); end demux_12 ; architecture behavioral of demux_12 is begin process(a,i) begin if(a='0') then y0<=i; elsif(a='1')then y1<=i; end if; end process; end behavioral; 17. DMUX 1:8 (IF ELSIF) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity demux_81 is port(a,b,c,i :in std_logic; y0,y1,y2,y3,y4,y5,y6,y7 : out std_logic); end demux_81 ; architecture behavioral of demux_81 is begin process(a,b,c,i) begin if(a='0' and b='0' and c<='0') then y0<=i; elsif(a='0' and b='0' and c<='1') then y1<=i; elsif(a='0' and b='1' and c<='0') then y2<=i; elsif(a='0' and b='1' and c<='1') then y3<=i; elsif(a='1' and b='0' and c<='0') then y4<=i; elsif(a='1' and b='0' and c<='1') then y5<=i; elsif(a='1' and b='1' and c<='0') then

y6<=i; elsif(a='1' and b='1' and c<='1') then y7<=i; end if; end process; end behavioral; 18. MUX 4:1 (IF.ELSIF) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity mux_41 is port(a,b,i0,i1,i2,i3 :in std_logic; y : out std_logic); end mux_41 ; architecture behavioral of mux_41 is begin process(a,b,i0,i1,i2,i3) begin if(a='0' and b='0') then y<=i0; elsif(a='0'and b='1')then y<=i1; elsif(a='1' and b='0')then y<=i2; elsif(a='1' and b='1')then y<=i3; end if; end process; end behavioral; 19. MUX 8:1 ( IFELSIF ) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity mux_81 is port(a,b,c,i0,i1,i2,i3,i4,i5,i6,i7 :in std_logic; y : out std_logic); end mux_81 ; architecture behavioral of mux_81 is begin process(a,b,i0,i1,i2,i3,i4,i5,i6,i7) begin if(a='0' and b='0' and c='0') then

y<=i0; elsif(a='0' and b='0' and c='1') then y<=i1; elsif(a='0' and b='1' and c='0') then y<=i2; elsif(a='0' and b='1' and c='1') then y<=i3; elsif(a='1' and b='0' and c='0') then y<=i4; elsif(a='1' and b='0' and c='1') then y<=i5; elsif(a='1' and b='1' and c='0') then y<=i6; elsif(a='1' and b='1' and c='1') then y<=i7; end if; end process; end behavioral; 20. 1 BIT ALU library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity alu_1 is port(s :in std_logic_vector(2 downto 0); x,y : in std_logic; a : out std_logic); end alu_1 ; architecture behavioral of alu_1 is begin process(s,x,y) begin case s is when "000"=> a<=x; when "001"=> a<=y; when "010"=> a<=x or y; when "011"=> a<=x and y; when "100"=> a<=x xor y; when "101"=> a<=not(x or y); when "110"=> a<=not(x and y); when "111"=> a<=not(x xor y); end case; end process; end behavioral;

21. BINARY TO EXCESS3 ( CASE) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity binarytoxs3 is port(a :in std_logic_vector(3 downto 0); y : out std_logic_vector(3 downto 0)); end binarytoxs3 ; architecture behavioral of binarytoxs3 is begin process(a) begin case a is when "0000"=> y<="0011"; when "0001"=> y<="0100"; when "0010"=> y<="0101"; when "0011"=> y<="0110"; when "0100"=> y<="0111"; when "0101"=> y<="1000"; when "0110"=> y<="1001"; when "0111"=> y<="1010"; when "1000"=> y<="1011"; when others=> y<="1100"; end case; end process; end behavioral; 22. DECODER 3:8 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity decoder38 is port(s :in std_logic_vector(2 downto 0); a : out std_logic_vector(7 downto 0)); end decoder38 ; architecture behavioral of decoder38 is begin process(s) begin case s is when "000"=> a<="00000001"; when "001"=> a<="00000010"; when "010"=> a<="00000100"; when "011"=> a<="00001000"; when "100"=> a<="00010000"; when "101"=> a<="00100000";

when "110"=> a<="01000000"; when "111"=> a<="10000000"; end case; end process; end behavioral; 23. DMUX 1:4 (CASE) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity demux_41 is port(a :in std_logic_vector(1 downto 0); i :in std_logic; y : out std_logic_vector(3 downto 0)); end demux_41 ; architecture behavioral of demux_41 is begin process(a,i) begin case a is when "00" =>y(0)<=i; when others =>y(0)<='0'; end case; case a is when "01" =>y(1)<=i; when others =>y(1)<='0'; end case; case a is when "10" =>y(2)<=i; when others =>y(2)<='0'; end case; case a is when "11" =>y(3)<=i; when others =>y(3)<='0'; end case; end process; end behavioral; 24. QUESTION library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity desprob is port(e :in std_logic_vector(1 downto 0); c,d : in std_logic; a,b : out std_logic);

end desprob ; architecture behavioral of desprob is begin process(e) begin b<='1'; case e is when "00"=> a<=c; when "01"=> a<=d; when "10"=> a<=c or d; when others => a<='0'; end case; end process; end behavioral; 25. MUX 2:1 (CASE) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity mux_21 is port(a,i0,i1 :in std_logic; y : out std_logic); end mux_21 ; architecture behavioral of mux_21 is begin process(a,i0,i1) begin case a is when '0' => y<=i0; when '1' => y<=i1; when others=>y<='Z'; end case; end process; end behavioral; 26. TRISTATE BUFFER library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity tristatebuf is port(a :in std_logic_vector(1 downto 0); y : out std_logic); end tristatebuf ; architecture behavioral of tristatebuf is begin

process(a) begin case a is when "10"=> y<='1'; when "11"=> y<='0'; when others=> y<='Z'; end case; end process; end behavioral; 27. TRISTATE INVERTER library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity tristateinv is port(a :in std_logic_vector(1 downto 0); y : out std_logic); end tristateinv ; architecture behavioral of tristateinv is begin process(a) begin case a is when "10"=> y<='0'; when "11"=> y<='1'; when others=> y<='Z'; end case; end process; end behavioral; 28. BINARY TO GRAY (WHEN ELSE) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity binarytogray is port(a,b,c,d,s :in std_logic; w,x,y,z : out std_logic); end binarytogray ; architecture dataflow of binarytogray is begin w<=a when s='0' else a ; x<= a xor b when s='0' else a xor b ; y<= b xor c when s='0'

else b xor c ; z<= c xor d when s='0' else c xor d ; end dataflow; 29. D MUX( WHEN ELSE) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity demux_12 is port(s,i :in std_logic; y0,y1 : out std_logic); end demux_12 ; architecture dataflow of demux_12 is begin y0<=i when s='0' else '0'; y1<=i when s='1' else '0'; end dataflow; 30.MUX 4:1 ( WHEN ELSE) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity mux_41 is port(i0,i1,i2,i3 :in std_logic; s :in std_logic_vector(1 downto 0); y : out std_logic); end mux_41 ; architecture dataflow of mux_41 is begin y<=i0 when s="00" else i1 when s="01" else i2 when s="10" else i3; end dataflow; 31. ALU library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

entity selectorval is port(a,b :in std_logic; s : in std_logic_vector(2 downto 0); y : out std_logic); end selectorval ; architecture dataflow of selectorval is begin y<= (a and b) when s="000" else (not(a and b)) when s="001" else (a xor b) when s="010" else (a xnor b) when s="011" else (not a) when s="100" else (not b) when s="101" else 'Z'; end dataflow; 32. EXCESS3 TO BINARY library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity xs3tobinary is port(a :in std_logic_vector(3 downto 0); w,x,y,z : out std_logic); end xs3tobinary ; architecture dataflow of xs3tobinary is begin w<='1' when a="1011" else '1' when a="1100" else '0' ; x<='1' when a="0111" else '1' when a="1000" else '1' when a="1001" else '1' when a="1010" else '0' ; y<='1' when a="0101" else '1' when a="0110" else '1' when a="1001" else '1' when a="1010" else '0' ; z<='1' when a="0100" else '1' when a="0110" else '1' when a="1000" else '1' when a="1010" else '1' when a="1100" else '0' ; end dataflow;

33. DMUX 1:8 (WITH SELECT) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity demux_81 is port(s :in std_logic_vector(2 downto 0); i: in std_logic; y0,y1,y2,y3,y4,y5,y6,y7 : out std_logic); end demux_81 ; architecture dataflow of demux_81 is begin with s select y0<=i when "000", '0' when others; with s select y1<=i when "001", '0' when others; with s select y2<=i when "010", '0' when others; with s select y3<=i when "011", '0' when others; with s select y4<=i when "100", '0' when others; with s select y5<=i when "101", '0' when others; with s select y6<=i when "110", '0' when others; with s select y7<=i when "111", '0' when others; end dataflow; 34. GRAY TO BINARY (WITH SELECT) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity graytobinary is port(s :in std_logic_vector(3 downto 0); a :out std_logic_vector(3 downto 0)); end graytobinary ; architecture dataflow of graytobinary is

begin with s select a<="0000" when "0000", "0001" when "0001", "0011" when "0010", "0010" when "0011", "0110" when "0100", "0111" when "0101", "0101" when "0110", "0100" when "0111", "1100" when "1000", "1101" when "1001", "1111" when "1010", "1110" when "1011", "1010" when "1100", "1011" when "1101", "1001" when "1110", "1000" when others; end dataflow; 35. MUX 8:1 (WITH SELECT) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity mux_81 is port(s :in std_logic_vector(2 downto 0); i0,i1,i2,i3,i4,i5,i6,i7: in std_logic; y : out std_logic); end mux_81 ; architecture dataflow of mux_81 is begin with s select y <=i0 when "000", i1 when "001", i2 when "010", i3 when "011", i4 when "100", i5 when "101", i6 when "110", i7 when others; end dataflow;

36. AFTER EXAMPLE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TASK18_1 is Port ( x,y : in STD_LOGIC; s,ca : out STD_LOGIC); end TASK18_1; architecture behavioral of TASK18_1 is begin s<=(x xor y) after 20ns; ca<=(x and y) after 30ns; end behavioral; 37.Q2 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity task18_2 is Port ( a : in std_logic_vector(1 downto 0); i0,i1,i2,i3 : in STD_LOGIC; y : out STD_LOGIC); end task18_2; architecture Behavioral of task18_2 is begin y<=i0 after 10ns when a="00" else i1 after 10ns when a="01" else i2 after 10ns when a="10" else i3 after 10ns; end Behavioral; 38. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity task18_3 is Port ( a,b : in STD_LOGIC; w,x,y,y1 : out STD_LOGIC); end task18_3; architecture Behavioral of task18_3 is begin y1<=a; y<=a after 10ns; x<=(a and b) after 30ns; w<=a after 10ns ,'1' after 20ns,'0' after 30ns; end Behavioral; 39. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity task_18_4 is Port ( a,b,c : in STD_LOGIC; p,q,r,s : out STD_LOGIC); end task_18_4; architecture Behavioral of task_18_4 is begin process(a,b,c) begin if(a=b)then p<='1'; else p<='0'; end if; end process; q<=c after 10 ns; r<=a after 30 ns; process(a,b,c) begin if(a='0' and b='1')or(a='1' and b='0') then s<='1'; else s<='0'; end if; end process; end behavioral;

40. NULL EXPRESSION library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity task_18_5 is Port ( a : in STD_LOGIC_vector(2 downto 0); i : in std_logic_vector(6 downto 0); y : out STD_LOGIC); end task_18_5; architecture Behavioral of task_18_5 is begin process(a,i) begin case a is when "000" => y<=i(0); when "001" => y<=i(1); when "010" => y<=i(2); when "011" => y<=i(3); when "100" => y<=i(4); when "101" => y<=i(5); when "110" => y<=i(6); when "111" => y<= null; end case; end process; end Behavioral; 41. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity task_18_6 is Port ( din : in STD_LOGIC_vector(6 downto 0); e : in std_logic; dout : out STD_LOGIC_vector(6 downto 0)); end task_18_6; architecture Behavioral of task_18_6 is begin process(din,e) begin

if(e='0') then dout(0)<=din(0); dout(1)<=din(1); dout(2)<=din(2); dout(3)<=din(3); dout(4)<=din(4); dout(5)<=din(5); dout(6)<=din(6); else dout(0)<=din(1); dout(1)<=din(2); dout(2)<=din(3); dout(3)<=din(4); dout(4)<=din(5); dout(5)<=din(6); dout(6)<=din(0); end if; end process; end Behavioral; 42. FOR LOOP library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity task_18_7 is Port ( din : in STD_LOGIC_vector(6 downto 0); e,i: in std_logic; dout : out STD_LOGIC_vector(6 downto 0)); end task_18_7; architecture Behavioral of task_18_7 is begin process(din,e,i) begin if(e='0') then i:=0; for i in 0 to 6 loop dout(i)<=din(i); end loop; else dout(6)<=din(0); i:=0; for i in 0 to 5 loop

dout(i)<=din(i+1); end loop; end if; end process; end Behavioral;

43. D FLIPFLOP library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity task19_1 is Port ( d,clk,rst : in STD_LOGIC; q, qbar : out STD_LOGIC); end task19_1; architecture behavioral of task19_1 is begin process(d,clk,rst) begin if(clk'event and clk='1') then if(rst<='1')then q<='0'; qbar<='1'; else q<=d; qbar<= (not d); end if; end if; end process; end behavioral;

44. T FLIP FLOP library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity task19_2 is Port ( t,clk,rst : in STD_LOGIC; q,qbar : out std_logic); end task19_2; architecture behavioral of task19_2 is begin process(t,clk,rst) variable w:std_logic; begin w:='0'; if(clk'event and clk='1') then if(rst='1')then q<='0'; qbar<='1'; else if(t='1') then w:=(not w); end if; q<=w; qbar<=not w; end if; end if; end process; end behavioral;

45. MASTER-SLAVE JK FLIP FLOP library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity task19_3 is Port ( j,k,clk,rst : in STD_LOGIC; qbar : out std_logic; q : inout std_logic); end task19_3; architecture behavioral of task19_3 is begin process(j,k,q,clk,rst) variable w:std_logic; begin if(clk'event and clk='1') then if(rst='1')then q<='0'; qbar<='1'; else if(j='0' and k='1') then q<='0';

qbar<='1'; else if(j='1' and k='0')then q<='1'; qbar<='0'; else if(j='1' and k='1')then w:=q; w:=(not w); end if; q<=w; qbar<=not w; end if; end if; end if; end if; end process; end behavioral;

46. UP-DOWN COUNTER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity task19_4 is Port ( clk,mode : in STD_LOGIC; count : out STD_LOGIC_vector(3 downto 0)); end task19_4; architecture behavioral of task19_4 is begin process(clk,mode) variable temp:std_logic_vector(3 downto 0):="0000"; begin if(rising_edge (clk)) then if(mode='1')then temp:=temp+1; else temp:=temp-1; end if; count<=temp; end if; end process; end behavioral;

47. BASE-6 COUNTER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity base_6 is port(clk: in std_logic; count: out std_logic_vector( 2 downto 0)); end base_6; architecture data of base_6 is begin process(clk) variable temp: std_logic_vector(2 downto 0):=000; begin if(clkevent and clk=1) then count<=temp; temp:=temp+1; end if; if(temp > 101) then temp:=000; end if; end process; end data;

48. FREQUENCY DIVIDER (DIVISION BY 3) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fdiv_3 is port(clk: in std_logic; count: out std_logic); end fdiv_3; architecture data of fdiv_3 is begin

process(clk) variable temp: std_logic_vector(2 downto 0):=000; begin if(clkevent and clk=1) then temp:=temp+1; if(temp >011) then count<=1; end if; if (temp > 110) then count<=0; temp:=001; end if; end if; end process; end data; 49. UNIVERSAL COUNTER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity task1910 is Port ( syn_clr,load,en,up : in STD_LOGIC; d:in std_logic_vector(3 downto 0); qout : out std_logic_vector(3 downto 0)); end task1910; architecture Behavioral of task1910 is begin process(syn_clr,load,en,up,d) variable temp:std_logic_vector(3 downto 0):="0000"; begin if(syn_clr='1')then qout<="0000"; elsif(syn_clr='0' and load='1') then qout<=d; elsif(syn_clr='0' and load='0' and en='1' and up='1')then temp:=temp+1; qout<=temp; elsif(syn_clr='0' and load='0' and en='1' and up='0')then temp:=temp-1; qout<=temp; else qout<=temp;

end if; end process; end Behavioral; 50. MICROWAVE OWEN library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity micro_wave is Port ( hr_in : inout integer range 0 to 23; min_in,sec_in : inout integer range 0 to 59); end micro_wave; architecture Behavioral of micro_wave is begin process variable hr :integer range 0 to 23; variable min,sec:integer range 0 to 59; begin hr:=hr_in; min:=min_in; sec:=sec_in; wait for 10000 ns; if(hr_in=0 and min_in=0 and sec_in=0)then hr:=0; min:=0; sec:=0; elsif(sec=0)then sec:=59; if(min=0)then min:=59; if(hr=0)then hr:=23; else hr:=hr-1; end if; else min:=min-1; end if; else sec:=sec-1; end if;

hr_in<=hr; min_in<=min; sec_in<=sec; end process; end Behavioral;

51. ROM

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity rom_44 is port ( rd,cs: in std_logic; add: in std_logic_vector( 3 downto 0); data: out std_logic_vector( 3 downto 0)); end rom_44; architecture data of rom_44 is type rom_44 is array ( 0 to 3 , 0 to 3) of std_logic_vector(3 downto 0); constant rom1: rom_44 := ((0001,1000,1001,0010), (1001,1100,1100,0000), (1101,1011, 0101,0010), (1111,1101,1011,1111)); begin data<= rom1 ( conv_integer (add(0 to 1)),conv_integer (add(2 to 3))) when (rd=1 and cs=1) else ----; end data;

52. RAM library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ram_44 is port ( rd,cs: in std_logic; wr: in std_logic; add: in std_logic_vector( 3 downto 0); data: out std_logic_vector( 3 downto 0)); end ram_44; architecture data of ram_44 is type ram_44 is array ( 0 to 3 , 0 to 3) of std_logic_vector(3 downto 0); constant ram1: ram_44 := ((0001,1000,1001,0010), (1001,1100,1100,0000), (1101,1011, 0101,0010), (1111,1101,1011,1111)); begin if( rd=1 and cs=1) then data<= ram1 (conv_integer (add(3 downto 2)),conv_integer (add(1 downto 0))); elsif (rd=0 and cs=1 and wr=1) then ram1 (conv_integer (add(3 downto 2)),conv_integer (add(1 downto 0))):=data; data<= ram1 (conv_integer (add(3 downto 2)),conv_integer (add(1 downto 0)));

else data<= ----; end if; end process; end data;

53. DECADE COUNTER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dec_cnt is port (clk: in std_logic; digit : out integer range 0 to 9); end dec_cnt; architecture data of dec_cnt is begin process(clk) variable temp : integer range 0 to 10; begin if (clkevent and clk=1) then temp:=temp+1; if( temp =10) then temp:=0; end if; end if; digit <= temp; end process; end data;

54. JHONSON COUNTER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity jo_cnt is port (clk:in std_logic; count : inout bit_vector( 3 downto 0 )); end jo_cnt; architecture data of jo_cnt is begin process( clk) variable temp:bit_vector(3 downto 0):=0000; begin count<=temp; if( clkevent and clk=1) then if(temp=0000)then temp:= 1000; elsif ( temp (3) =1 and temp /= 1111)then temp := temp sra 1; else temp := temp srl 1; end if; end if; end process; end data;

55.LEFT-RIGHT SHIFT REGISTER WITH RESET library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity lrsr is generic ( k: integer :=4); port (clk,rst,w : in std_logic; q: buffer std_logic_vector ( k downto 1)); end lrsr; architecture data of lrsr is begin process( clk,rst,w) begin if(rst=0) then q<=(others=> 0); elsif ( clkevent and clk =1) then for i in k downto 2 loop q(i) <= q(i 1); end loop; q(1) <= w; end if; end process; end data;

56. n bit register library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity reg is generic ( n: integer := 8); port ( r : in std_logic_vector (n-1 downto 0); rin,clk : in std_logic; q : out std_logic_vector ( n- 1 downto 0)); end reg;

architecture data of reg is begin process ( r, rin, clk ) begin wait until clkevent and clk=1 ; if ( rin = 1) then q<=r; end if; end process; end data;

57. SHIFT REGISTER PARALLEL LOAD library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity srpl is generic ( n : integer := 4); port ( r : in std_logic_vector ( n-1 downto 0); l,w,clk : in std_logic; q : buffer std_logic_vector ( n-1 downto 0)); end srpl; architecture data of srpl is begin process (r,l,w,clk) begin if ( clkevent and clk=1) then if ( l=1) then q<=r; else for i in 0 to n-2 loop q(i)<=q(i+1); end loop; q(n-1) <= w; end if; end if; end process; end data;

STRUCTURAL MODELING 1. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity task2101 is Port ( A0,B0,A1,B1,A2,B2,A3,B3 : in STD_LOGIC; sum0,sum1,sum2,sum3,car3:out std_logic); end task2101; architecture structural of task2101 is component xor_gt is port(c,d : in std_logic; e : out std_logic); end component; component and_gt is port(c,d : in std_logic; e : out std_logic); end component; component or_gt is port(c,d : in std_logic; e : out std_logic); end component; signal s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,car0,car1,car2 :std_logic; begin u1: xor_gt port map(A0,B0,s1); u2:and_gt port map(A0,B0,s2); u3:xor_gt port map('0',s1,sum0); u4:and_gt port map('0',s1,s3); u5: or_gt port map(s2,s3,car0); u6: xor_gt port map(A1,B1,s4); u7:and_gt port map(A1,B1,s5); u8:xor_gt port map(car0,s4,sum1); u9:and_gt port map(car0,s4,s6); u10: or_gt port map(s5,s6,car1); u11: xor_gt port map(A2,B2,s7); u12:and_gt port map(A2,B2,s8); u13:xor_gt port map(car1,s7,sum2); u14:and_gt port map(car1,s7,s9); u15: or_gt port map(s8,s9,car2); u16: xor_gt port map(A3,B3,s10); u17:and_gt port map(A3,B3,s11); u18:xor_gt port map(car2,s10,sum3); u19:and_gt port map(car2,s10,s12); u20: or_gt port map(s11,s12,car3); end structural;

2. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity task2102 is Port ( i0,i1,i2,i3,se0,se1,se3: in STD_LOGIC; Y:out std_logic); end task2102; architecture structural of task2102 is component and_gt is port(c,d : in std_logic; e : out std_logic); end component; component or_gt is port(c,d : in std_logic; e : out std_logic); end component; component not_gt is port(c : in std_logic; e : out std_logic); end component; signal s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,y0,y1 :std_logic; begin u1:and_gt port map(i0,se0,s1); u2:not_gt port map(se0,s2); u3:and_gt port map(s2,i1,s3); u4:or_gt port map(s1,s3,y0); u5:and_gt port map(y0,se1,s4); u6:not_gt port map(se1,s5); u7:and_gt port map(s5,i2,s6); u8:or_gt port map(s4,s6,y1); u9:not_gt port map(se3,s10); u10:and_gt port map(y1,s10,s7); u11:not_gt port map(s10,s8); u12:and_gt port map(s8,i3,s9); u13:or_gt port map(s7,s9,Y); end structural;

3. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity task2103 is Port ( A,B : in STD_LOGIC; p:in std_logic_vector(2 downto 0); Y:out std_logic_vector(7 downto 0)); end task2103; architecture structural of task2103 is component xor_gt is port(c,d : in std_logic; e : out std_logic); end component; component and_gt is port(c,d : in std_logic; e : out std_logic); end component; component or_gt is port(c,d : in std_logic; e : out std_logic); end component; component not_gt is port(c: in std_logic; e : out std_logic); end component; component xnor_gt is port(c,d : in std_logic; e : out std_logic); end component; component buffer_gt is port(c : in std_logic; e : out std_logic); end component; component and3_gt is port(c,d,f : in std_logic; e : out std_logic); end component; signal s1,s2,s3,s4,s5,s6,s7,s8:std_logic_vector(2 downto 0); signal s9,s10,s11,s12,s13,s14,s15,s16,s17,s18,s19,s20,s21,s22,s23,s24:std_logic; begin u1:not_gt port map(p(0),s1(0)); u2:not_gt port map(p(1),s1(1)); u3:not_gt port map(p(2),s1(2)); u4:and3_gt port map(s1(0),s1(1),s1(2),s9); u5:not_gt port map(A,s10); u6:and_gt port map(s9,s10,Y(0)); u7:not_gt port map(p(0),s2(0)); u8:not_gt port map(p(1),s2(1));

u9:and3_gt port map(s2(0),s2(1),p(2),s11); u10:not_gt port map(B,s12); u11:and_gt port map(s11,s12,Y(1)); u12:not_gt port map(p(0),s3(0)); u13:not_gt port map(p(2),s3(2)); u14:and3_gt port map(s3(0),p(1),s3(2),s13); u15:or_gt port map(A,B,s14); u16:and_gt port map(s13,s14,Y(2)); u17:not_gt port map(p(0),s4(0)); u18:and3_gt port map(s4(0),p(1),p(2),s15); u19:and_gt port map(A,B,s16); u20:and_gt port map(s15,s16,Y(3)); u21:not_gt port map(p(1),s5(1)); u22:not_gt port map(p(2),s5(2)); u23:and3_gt port map(p(0),s5(1),s5(2),s17); u24:xor_gt port map(A,B,s18); u25:and_gt port map(s17,s18,Y(4)); u26:not_gt port map(p(1),s6(1)); u27:and3_gt port map(p(0),s6(1),p(2),s19); u28:xnor_gt port map(A,B,s20); u29:and_gt port map(s19,s20,Y(5)); u30:not_gt port map(p(2),s7(2)); u31:and3_gt port map(p(0),p(1),s7(2),s21); u32:buffer_gt port map(A,s22); u33:and_gt port map(s21,s22,Y(6)); u34:and3_gt port map(p(0),p(1),p(2),s23); u35:buffer_gt port map(B,s24); u36:and_gt port map(s23,s24,Y(7)); end structural;

4. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity task2104 is Port ( A,clk : in STD_LOGIC; Y:out std_logic); end task2104; architecture structural of task2104 is component nand_gt is port(c,d : in std_logic; e : out std_logic); end component; component not_gt is port(c : in std_logic; e : out std_logic); end component; signal s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16,s17,s18,s19,s20:std_logic; begin u1:not_gt port map(A,s1); u2:nand_gt port map(A,clk,s2); u3:nand_gt port map(s1,clk,s3); u4:nand_gt port map(s2,s5,s4); u5:not_gt port map(s4,s6); u6:nand_gt port map(s4,clk,s7); u7:nand_gt port map(s1,clk,s8); u8:nand_gt port map(s7,s10,s9); u9:not_gt port map(s9,s11); u10:nand_gt port map(s9,clk,s12); u11:nand_gt port map(s11,clk,s13); u12:nand_gt port map(s12,s15,s14); u13:not_gt port map(s14,s16); u14:nand_gt port map(s14,clk,s17); u15:nand_gt port map(s16,clk,s18); u16:nand_gt port map(s17,s20,s19); end structural;

5. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity prgm2 is Port ( i0,i1,i2,i3,s0,s1,s2 : in STD_LOGIC;y :out std_logic); end prgm2; architecture struct of prgm2 is component mux2 is port(i0,i1,s0:in std_logic; y:out std_logic); end component; component not_gt is port(a:in std_logic; y:out std_logic); end component; signal k1,k2,k3:std_logic; begin u1:mux2 port map(i0,i1,s0,k1); u2:mux2 port map(k1,i2,s1,k2); u3:mux2 port map(k2,i3,k3,y); u4:not_gt port map(s2,k3); end struct; 6. 4 BIT BINARAY PARALELL ADDER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity prgm2 is Port ( a0,a1,a2,a3,b0,b1,b2,b3,c0 : in STD_LOGIC; ca,sum0,sum1,sum2,sum3 : out STD_LOGIC); end prgm2; architecture struct of prgm2 is c0:=0; component fadder is port(a0,b0,c0:in std_logic; sum,ca : out std_logic); end component;

signal k1.k2,k3,k4:std_logic; u1:fadder port map(a0,b0,c0,sum0,k1); u2:fadder port map(a1,b1,k1,sum1,k2); u3:fadder port map(a2,b2,k2,sum2,k3); u4:fadder port map(a3,b3,k3,sum3,k4); end struct;

7. SISO library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; Sentity siso is Port ( d,clk : in STD_LOGIC;q :inout std_logic; qbar:inout std_logic); end siso; architecture struct of siso is component dflip is Port ( a,clk : in STD_LOGIC;q,qbar:inout std_logic); end component; --signal k1,k2,k3,k4,k5,k6:std_logic; begin u1:dflip port map(a=>d,clk=>clk,q=>q,qbar=>qbar); u2:dflip port map(a=>q,clk=>clk,q=>q,qbar=>qbar); u3:dflip port map(a=>q,clk=>clk,q=>q,qbar=>qbar); u4:dflip port map(a=>q,clk=>clk,q=>q,qbar=>qbar);

end struct;

8. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity prgm2 is Port ( i0,i1,i2,i3,s0,s1,s2 : in STD_LOGIC;y :out std_logic); end prgm2; architecture struct of prgm2 is component mux2 is port(i0,i1,s0:in std_logic; y:out std_logic); end component; component not_gt is port(a:in std_logic; y:out std_logic); end component; signal k1,k2,k3:std_logic; begin u1:mux2 port map(i0,i1,s0,k1); u2:mux2 port map(k1,i2,s1,k2); u3:mux2 port map(k2,i3,k3,y); u4:not_gt port map(s2,k3); end struct;

VERILOG 1. BUFFER module buffer(a, y); input a; output y; assign y=a; endmodule 2. FULL ADDER module fadder(a,b,c, sum,ca); input a,b,c; output sum,ca; assign sum=(a^b)^c; assign ca=((a&b)|((a^b)&c)); endmodule 3. HALF SUBTRACTOR module halfsub(a,b,diff,bo); input a,b; output bo,diff; assign diff=((a&(~b))| (b&(~a))); assign bo=(~ a)& b; endmodule 4. MUX 8:1 module mux8(i0,i1,i2,i3,i4,i5,i6,i7,s, y); input i0,i1,i2,i3,i4,i5,i6,i7; input [2:0]s; output y; reg y; always @(*) begin if (s==000) y=i0; else if(s==001) y=i1; else if(s==010)

y=i2; else if(s==011) y=i3; else if(s==100) y=i4; else if(s==101) y=i5; else if(s==110) y=i6; else if(s==111) y=i7; end endmodule 5. NAND GATE module nand_gt(a,b, y); input a,b; output y; assign y=~(a & b); endmodule 6. NOR GATE module nor_gt(a,b, y); input a,b; output y; assign y=~(a | b); endmodule 7. D MUX 1:4 module demux4(i,s, y1,y2,y3,y4); input i; input[1:0]s; output y1,y2,y3,y4; reg y1,y2,y3,y4; always@(*) begin if(s==00) begin y1=1;y2=0;y3=0;y4=0; end else if(s==01) begin y1=0;y2=1;y3=0;y4=0; end else if(s==10)

begin y1=0;y2=0;y3=1;y4=0; end else if(s==11) begin y1=0;y2=0;y3=0;y4=1; end end endmodule 8. DMUX 1:4 module dmux4(i,s, y); input i; input [1:0]s; output [3:0]y; reg y; always@(*) if (s==00) y=0001; else if (s==01) y=0010; else if (s==10) y=0100; else if (s==11) y=1000; endmodule 9. MUX 1:8 module mux8(i,s,y); input [7:0]i; input [2:0]s; output y; reg y; always@(*) begin if(s==000) y=i(0); else if (s==001) y=i(1); else if (s==010) y=i(2); else if (s==011) y=i(3);

else if (s==100) y=i(4); else if (s==101) y=i(5); else if (s==110) y=i(6); else if (s==111) y=i(7); end endmodule 10. BINARAY TO EXCESS 3 module binecxess3(a,b,c,d, p,q,r,s); input a,b,c,d; output p,q,r,s; reg p,q,r,s; always@(*) begin assign s=(~d); assign p=(a|(b&d)|(b&c)); assign q=((b&(~c)&(~d))|(a&d)|(a&c)|((~b)&d)|((~b)&c)); assign r=((a&b)|(~(c^d))); end endmodule 11. BINARY TO GRAY module bingray(a,b,c,d, p,q,r,s); input a,b,c,d; output p,q,r,s; reg p,q,r,s; always@(*) begin p=a; if(a^b==1) q=1; else q=0; if(c^b==1) r=1; else r=0;

if(c^d==1) s=1; else s=0; end endmodule 12. DECODER 3:8 module decoder(i, y,e); input [2:0]i; input e; output [7:0]y; reg [7:0]y; always@(*) begin if(e==1) y= 8'b 11111111; else case(i) 3'b 000:y=8'b 11111110; 3'b 001:y=8'b 11111101; 3'b 010:y=8'b 11111011; 3'b 011:y=8'b 11110111; 3'b 100:y=8'b 11101111; 3'b 101:y=8'b 11011111; 3'b 110:y=8'b 10111111; 3'b 111:y=8'b 01111111; endcase end endmodule 13. MUX 8:1 module mux8(i, y,s); input [7:0]i; input [2:0]s; output y; reg y; always @(*) begin case (s) 2'b 000:y=i(0); 2'b 001:y=i(1);

2'b 010:y=i(2); 2'b 011:y=i(3); 2'b 100:y=i(4); 2'b 101:y=i(5); 2'b 110:y=i(6); 2'b 111:y=i(7); endcase end endmodule 14. 7 SEGMENT module segment7(A,B,C,D, p,q,r,s,t,u,v); input A,B,C,D; output p,q,r,s,t,u,v; reg p,q,r,s,t,u,v; always@(*) begin p=(A|C|(~(B^D))); q=((~B)|(~(C^D))); r=(B|D|(~C)); s=(A|((~B)&(~D))|((~B)&C)|(B&D&(~C))|(C&(~A)&(~D))); t=(((~B)&(~D))|(C&(~D))); u=(A|(B&(~C))|(B&(~D))|((~C)&(~D))); v=(A|(C&(~D))|(B^C)); end endmodule

15. T FLIPFLOP module tff(t,clk,rst,q,qb); input t,clk,rst; output q,qb; always @ (posedge clk) begin if ( rst==1) begin q<=0; qb<=1; end else if( t==1 & clk==1) begin q<=1; qb<=0; end else if ( t==1 & clk==0) begin q<=0; qb<=1; end end end endmodule 16. DFF module ( clk,rst,d,q,qb); output q,qb; input clk,rst,d; reg q,qb; always @ (posedge clk) if (~ rst) begin q<=0; qb<=1; end else if (d) begin q<=!q; qb<=q; end endmodule

17. UP/DOWN COUNTER module updn ( clk,rst,count,q); input clk,rst,count; output [3:0]q; reg [3:0]q; always @ (posedge clk) begin if(rst) begin q<=0; end else if (count) begin q<=q+1; end else begin q<=q-1; end end endmodule 18. SISO module sisor(clk,si,so); input clk,si; output [3:0] so; reg so; always @ (posedge clk) begin so={si,so[3:1]}; end endmodule

19. LINEAR FEED-BACK SHIFT REGISTER module lfs (clk,rst,q); input clk,rst; output [7:0]; reg [7:0] q; wire w; assign w=!(q[7] ^ q[3]); always @ (posedge clk, negedge rst) if(rst==0) q<=8b1; else

q<={q[6:0],w}; endmodule

20. RING COUNTER module ringc(clk,rst,q); input clk,rst; output [7:0] q; reg [7:0]q; wire w; assign w=q[7]; always @ (posedge clk, negedge rst) if(rst==0) q<=8b1; else q<={ q [6 :0],w}; endmodule