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1. INTRODUCTION
A linear feedback shift register (LFSR) is a shift register whose input bit is a linear function of its previous state. The only linear function of single bits is XOR, thus it is a shift register whose input bit is driven by the exclusive-or (XOR) of some bits of the overall shift register value. A 4-bit Fibonacci LFSR with its state diagram. The XOR gate provides feedback to the register that shifts bits from left to right. The maximal sequence consists of every possible state except the "0000" state. The initial value of the LFSR is called the seed, and because the operation of the register is deterministic, the stream of values produced by the register is completely determined by its current (or previous) state. Likewise, because the register has a finite number of possible states, it must eventually enter a repeating cycle. However, an LFSR with a well-chosen feedback function can produce a sequence of bits which appears random and which has a very long cycle. Applications of LFSRs include generating pseudo-random numbers, pseudo-noise sequences, fast digital counters, and whitening sequences. Both hardware and software implementations of LFSRs are common.
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A LFSR (linear feedback shift register) is a shift register where the input is a linear function of two or more bits (taps). There are many possible configurations, the one presented here is very simple and has the property that it will start from an input of all 0's and is very easy to implement in software and hardware. A LFSR of this type will never contain only 1's and would stall if loaded with that value. Only some taps will generate a maximal sequence with a period of 2^n-1 cycles. In this article we discuss the two implementations of LFSR generators, how to determine feedback taps for generating a maximal length sequence, and the properties of maximal length sequences (m-sequences). We also provide tables of m-sequence feedback taps.
Linear feedback shift registers can be implemented in two ways. The Fibonacci implementation consists of a simple shift register in which a modulo-2 sum of the binary-weighted taps is fed back to the input. (The modulo-2 sum of two 1-bit binary numbers yields 0 if the two numbers are identical, and 1 if the differs: 0+0=0, 0+1=1, 1+1=0.)
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Fig (2.1.1). Fibonacci implementation of LFSR. For any given tap, weight gi is either 0, meaning "no connection," or 1, meaning it is fed back. Two exceptions are g0 and gm, which are always 1 and thus always connected. Note that gm is not really a feedback connection, but rather is the input of the shift register. It is assigned a feedback weight for mathematical purposes, as is explained below. The Galois implementation consists of a shift register, the content of which is modified at every step by a binary-weighted value of the output stage, again using modulo-2 math.
Fig (2.1.2). Galois implementation of LFSR. Careful inspection reveals that the order of the Galois weights is opposite that of the Fibonacci weights. Given identical feedback weights, the two LFSR implementations will produce the same sequence. However, the initial states of the two implementations must necessarily be different for the two sequences to have identical phase (that is, zero bit offset relative to each other). The initial state of the Fibonacci form is called the initial fill or initial vector, and this initial fill comprises the first m bits output from the generator. The initial state of the Galois generator must be adjusted appropriately to attain the equivalent output of its first m bits. (In mathematical literature, the initial state of either form is called the seed.) When implemented in hardware, modulo-2 addition is performed using exclusiveOR (XOR) gates. The Galois form is generally faster than the Fibonacci in
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hardware due to the reduced number of logic gates in the feedback loop, thus making it the favored form. It should be noted that, in some industries, the Fibonacci form LFSR is referred to as a simple shift register generator (SSRG), and the Galois form is referred to as a multiple-return shift register generator (MRSRG) or modular shift register generator (MSRG).
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remaining feedback taps. The value of each fj is equal to the subscript of the corresponding connection g. The g subscript on the right bracket signifies the Galois LFSR form. The set of feedback taps for the equivalent Fibonacci generator is denoted as[f1, m-f2, m-f3, ..., m-fJ] f where the f subscript on the right bracket signifies the Fibonacci LFSR form. Note that subtracting the feedback tap numbers from m is equivalent to reversing the order of the feedback taps. As an example, consider an LFSR of size m = 8 with feedback connections at g8, g6, g5, g4, and implied g0. The feedback taps are specified as [8, 6, 5, 4]g for the Galois form, and [8, 8-6, 8-5, 8-4]f = [8, 2, 3, 4]f = [8, 4, 3, 2]f for the Fibonacci form.
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The constant 1 in the generator polynomial represents the input connection of the shift register, g0.Now, here is the key to determining m-sequence feedback taps: The generator polynomial of Equation 1 is said to be primitive if it cannot be factored (i.e. it is prime), and if it is a factor of (i.e. can evenly divide) XN+1, where N = 2m-1 (the length of the m-sequence). It can be shown that an LFSR represented by a primitive polynomial will produce a maximal length sequence. Consider again the example of the [3, 1] LFSR just given. We wish to know if this generator will produce an m-sequence. First we note that m = 3 and N=23-1=7. It
Dept. Of ECE, College of Engg. Poonjar. Page 6
can be shown that its polynomial, X3+X1+1, cannot be factored, and it can be shown that its polynomial is a factor of X7+1. Thus, we conclude that this LFSR will indeed produce a maximal length sequence. In this example, we went through the process of determining whether or not the given set of feedback taps would result in a maximal length sequence. Normally, however, we are required to do just the opposite. That is, we are normally asked to find all sets of feedback taps that will produce m-sequences for a given register size. For example, we may be asked to find all sets of maximal-length feedback taps for an LFSR with m=3 registers. We do this as follows: The length of the msequences will be N=23-1=7. We know that the solution lies in all the primitive factors of polynomial X7+1. We use modulo-2 linear algebra (probably with the aid of a computer algorithm) to find the prime factors to be
The primitive polynomials are those factors whose order is the same as the register size, m = 3. Of the three prime factors we see here, the last two meet this criterion. Thus we see that there are exactly two sets of m-sequence feedback taps, [3, 1] and [3, 2].It is interesting to note that, given any shift register size, there will always be an even number of m-sequence feedback sets. More specifically, given any one of its m-sequence feedback sets, [f1, f2, f3, ..., fJ] there will be a companion set described as [f1, m-f2, m-f3, ..., m-fJ] whose sequence will be the mirror image of the original set's sequence. Note that subtracting feedback tap numbers from m for the companion set is equivalent to reversing the order of those taps. Thus we conclude that, for any given feedback set that produces an msequence, the mirror image of the feedback set will produce the mirror image of the m-sequence. And, of course, the resulting sequence will also be an msequence since all possible states are exhausted. An astute reader may have noticed in the last example that the two derived sets of m-sequence feedback taps, [3, 1] and [3, 2], are in fact mirror images of each other. If the reader wishes to determine m-sequence feedback sets not available here, the method described in this section can be used to do so. However, writing software that performs modulo-2 polynomial factorization using, for example, the famous Berlekamp algorithm will typically not be a trivial task for a non-mathematician. Fortunately there are off-the-shelf solutions available. Maple soft sells a product called Maple which includes a function called Berlekamp. This will return all primitive polynomial factors of any given polynomial. If you own Mat Lab or some other popular numerical computing environment, you might be able to find and download a free copy of a factorization script written by another user.
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3. FIBONACCI LFSR
Fig (3.1) A 16 Bit Fibonacci LFSR A 16-bit Fibonacci LFSR. The feedback tap numbers in white correspond to a primitive polynomial in the table so the register cycles through the maximum number of 65535 states excluding the all-zeroes state excluding the all-zeroes state. The state ACE1 hex shown will be followed by 5670 hex. The bit positions that affect the next state are called the taps. In the diagram the taps are [16, 14, 13, and 11]. The rightmost bit of the LFSR is called the output bit. The taps are XOR'd sequentially with the output bit and then fed back into the leftmost bit. The sequence of bits in the rightmost position is called the output stream.
The bits in the LFSR state which influence the input are called taps (white in the diagram). A maximum-length LFSR produces an m-sequence (i.e. it cycles through all possible 2n 1 states within the shift register except the state where all bits are zero), unless it contains all zeros, in which case it will never change. As an alternative to the XOR based feedback in an LFSR, one can also use XNOR .This function is not linear, but it results in an equivalent polynomial counter whose state of this counter is the complement of the state of an LFSR. A state with all ones is illegal when using an XNOR feedback, in the same way as a state with all zeroes is illegal when using XOR. This state is considered illegal because the counter would remain "locked-up" in this state.
The sequence of numbers generated by an LFSR or its XNOR counterpart can be considered a binary numeral system just as valid as Gray code or the natural binary code.
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The arrangement of taps for feedback in an LFSR can be expressed in finite field arithmetic as a polynomial mod 2. This means that the coefficients of the polynomial must be 1's or 0's. This is called the feedback polynomial or characteristic polynomial. For example, if the taps are at the 16th, 14th, 13th and 11th bits (as shown), the feedback polynomial is
The 'one' in the polynomial does not correspond to a tap it corresponds to the input to the first bit (i.e. x0, which is equivalent to 1). The powers of the terms represent the tapped bits, counting from the left. The first and last bits are always connected as an input and output tap respectively. Tables of primitive polynomials from which maximum-length LFSRs can be constructed are given below and in the references.
The LFSR will only be maximum-length if the number of taps is even; just 2 or 4 taps can suffice even for extremely long sequences. The set of taps must be relatively prime and share no common divisor to all taps. There can be more than one maximum-length tap sequence for a given LFSR length Once one maximum-length tap sequence has been found, another automatically follows. If the tap sequence, in an n-bit LFSR, is [n, A, B, C, 0], where the 0 corresponds to the x0 = 1 term, then the corresponding 'mirror' sequence is [n, n C, n B, n A, 0]. So the tap sequence [32, 7, 3, 2, 0] has as its counterpart [32, 30, 29, 25, 0]. Both give a maximum-length sequence.
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Some example C/C++ code is below (assuming 16-bit shorts): unsigned short lfsr=0xACE1u; unsigned bit; unsigned period=0; do{ /*taps: 16 14 13 11; characteristic polynomial: x^16 + x^14 + x^13 + X^11 + 1*/ bit = ((lfsr >> 0) ^ (lfsr >>2) ^ (lfsr >> 3) ^ (lfsr >> 5)) & 1; lfsr = (lfsr >>1) | (bit << 15); ++period; } while (lfsr! = 0xACE1u); The above code assumes the right most significant bit 1, and the least significant bit 16. As well as Fibonacci, this LFSR configuration is also known as standard, many-to-one or external XOR gates. It has an alternative configuration.
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4. GALOIS LFSRS
Named after the French mathematician Evariste Galois, an LFSR in Galois configuration, which is also known as modular, internal XORs as well as oneto-many LFSR, is an alternate structure that can generate the same output stream as a conventional LFSR. In the Galois configuration, when the system is clocked, bits that are not taps are shifted one position to the right unchanged. The taps, on the other hand, are XOR'd with the output bit before they are stored in the next position. The new output bit is the next input bit. The effect of this is that when the output bit is zero all the bits in the register shift to the right unchanged, and the input bit becomes zero. When the output bit is one, the bits in the tap positions all flip (if they are 0, they become 1, and if they are 1, they become 0), and then the entire register is shifted to the right and the input bit becomes 1.
Fig (4.1) A 16-bit Galois LFSR. The register numbers in white correspond to the same primitive polynomial as the Fibonacci example but are counted in reverse to the shifting direction. This register also cycles through the maximal number of 65535 states excluding the allzeroes state. The state ACE1 hex shown will be followed by E270 hex.To generate the same output stream, the order of the taps is the counterpart (see above) of the order for the conventional LFSR; otherwise the stream will be in reverse. Note that the internal state of the LFSR is not necessarily the same. The Galois register shown has the same output stream as the Fibonacci register in the first section. Galois LFSRs do not concatenate every tap to produce the new input (the XOR'ing is done within the LFSR and no XOR gates are run in serial, therefore the propagation times are reduced to that of one XOR rather than a whole chain), thus it is possible for each tap to be computed in parallel, increasing the speed of execution.
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In a software implementation of an LFSR, the Galois form is more efficient as the XOR operations can be implemented a word at a time: only the output bit must be examined individually. Below is a code example of a 32-bit maximal period Galois LFSR that is valid in C and C++, (assuming that unsigned int has 32 bit precision): unsigned lfsr = 1; unsigned period = 0; do { /* taps: 32 31 29 1; characteristic polynomial: x^32 + x^31 + x^29 + x + */ lfsr (lfsr >> 1) ^ (-(lfsr & 1u) & 0xD0000001u); ++period; } while (lfsr! =1u); 1 And here is the code for the 16 bit example in the figure (Assuming 16bit shorts) unsigned short lfsr = 0xACE1u; unsigned period = 0; do { /* taps: 16 14 13 11; characteristic polynomial: x^16 + x^14 + x^13 + x^11 + 1 */ lfsr = (lfsr >> 1) ^ (-(lfsr & 1u) & 0xB400u); ++period; } while (lfsr! = 0xACE1u); These code examples create a toggle mask to apply to the shifted value using the XOR operator. The mask is created by first removing all but the least significant bit (the output bit) of the current value. This value is then negated (twos complement negation), which creates a value of either all 0s or all 1s, if the output bit is 0 or 1, respectively. By ANDing the result with the tap-value (e.g., 0xB400 in the second example) before applying it as the toggle mask, it acts functionally as a conditional to either apply or not apply the toggle mask based on the output bit.
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A more explicit but significantly less efficient code example is shown below. unsigned short lfsr = 0xACE1u; unsigned period = 0; do { unsigned lsb = lfsr & 1; /* Get lsb (i.e., the output bit). */ lfsr >>= 1; /* Shift register */ if (lsb == 1) /* only apply toggle mask if output bit is 1. */ lfsr ^= 0xB400u; /* Apply toggle mask, value has 1 at bits corresponding * to taps, 0 elsewhere. */ ++period; } while (lfsr! = 0xACE1u);
4.1
Binary Galois LFSRs like the ones shown above can be generalized to any qary alphabet {0, 1... q 1} (e.g., for binary, q is equal to two, and the alphabet is simply {0, 1}). In this case, the exclusive-or component is generalized to addition modulo-q (note that XOR is addition modulo 2), and the feedback bit (output bit) is multiplied (modulo-q) by a q-ary value which is constant for each specific tap point. Note that this is also a generalization of the binary case, where the feedback is multiplied by either 0 (no feedback, i.e., no tap) or 1 (feedback is present). Given an appropriate tap configuration, such LFSRs can be used to generate Galois fields for arbitrary values of q.
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5.
Bits Feedback polynomial Period N 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 x2 + x + 1 x3 + x2 + 1 x4 + x3 + 1 x5 + x3 + 1 x6 + x5 + 1 x7 + x6 + 1 x8 + x6 + x5 + x4 + 1 x9 + x5 + 1 x10 + x7 + 1 x11 + x9 + 1 2n 1 3 7 15 31 63 127 255 511 1023 2047
x12 + x11 + x10 + x4 + 1 4095 x13 + x12 + x11 + x8 + 1 8191 x14 + x13 + x12 + x2 + 1 16383 x15 + x14 + 1 x17 + x14 + 1 x18 + x11 + 1 32767 x16 + x14 + x13 + x11 + 1 65535 131071 262143
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6. OUTPUT-STREAM PROPERTIES
Ones and zeroes occur in 'runs'. The output stream 0110100, for example consists of five runs of lengths 1, 2,1,1,2, in order. In one period of a maximal LFSR, 2n 1 runs occur (for example, a six bit LFSR will have 32 runs). Exactly 1/2 of these runs will be one bit long, 1/4 will be two bits long, up to a single run of zeroes n 1 bits long, and a single run of ones n bits long. This distribution almost equals the statistical expectation value for a truly random sequence. However, the probability of finding exactly this distribution in a sample of a truly random sequence is rather low.
LFSR output streams are deterministic. If you know the present state, you can predict the next state. This is not possible with truly random events. The output stream is reversible; an LFSR with mirrored taps will cycle through the output sequence in reverse order.
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Fig (6.2) Output Sequences Of LFSR For those unfamiliar with Linear Feedback Shift Registers, see the Primer following Figure 1. For quick information on any of the LFSR parts (shift register, feedback function, output stream, tap sequences) click on the corresponding part in Figure 1. For a listing of tap sequences for registers 3 to 24 bits long and for 2, 4, and 6 tap sequences for registers 25 to 32 bits long. For C source code for an LFSR simulator. For a discussion of uses of LFSR's in cryptography, see "Applied Cryptography" by Bruce Schneier. For the math behind LFSR's, see "Shift Register Sequences" by Solomon Golomb.
Some nomenclature:
Clocking: - One of the inputs to a shift register is the clock; a shift occurs in the register when this clock input changes state from one to zero (or from zero to one, depending on the implementation). From this, the term "clocking" has arisen to mean activating a shift of the register. Sometimes the register is said to be "strobed" to cause the shift. Input: - After a shift, the bit on the left end of the shift register is left empty unless a new bit (one not contained in the original contents) is put into it. This bit is sometimes referred to as the input bit. As with the output
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bit, there are several different references to input that are clarified by context. Output: - During a shift, the bit on the far right end of the shift register is moved out of the register. This end bit position is often referred to as the output bit. To confuse matters a bit, the bits that are shifted out of the register are also often referred to as output bits. To really muddy the waters, every bit in the shift register is considered to be output during a serial to parallel conversion. Happily, the context in which the term "output" is used generally clears things up. Shift direction: - A shift register can shift its contents in either direction depending on how the device is designed. (Some registers have extra inputs that dictate the direction of the shift.) For the purposes of this discussion, the shift direction will always be from left to right.
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The bit positions selected for use in the feedback function are called "taps". The list of the taps is known as the "tap sequence". By convention, the output bit of an LFSR that is n bits long is the nth bit; the input bit of an LFSR is bit 1.
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Table [6.3.1] 4-Bit LFSR [4, 1] States and Output Register States Bit 1 (Tap) Bit 2 1 0 0 1 0 0 0 1 1 1 1 0 1 0 1 1 1 1 0 0 1 0 0 0 1 1 1 1 0 1 0 1 Bit 3 0 1 1 0 0 1 0 0 0 1 1 1 1 0 1 0 Bit 4 (Tap) 1 0 1 1 0 0 1 0 0 0 1 1 1 1 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1 1 0 Output Stream
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1) Maximal length tap sequences always have an even number of taps. 2) The tap values in a maximal length tap sequence are all relatively prime. A tap sequence like 12, 9, 6, 3 will not be maximal length because the tap are all divisible by 3.
Discovering one maximal length tap sequence leads automatically to another. If a maximal length tap sequence is described by [n, A, B, C], another maximal length tap sequence will be described by [n, n-C, n-B, nA]. Thus, if [32, 3, 2, 1] is a maximal length tap sequence, [32, 31, 30, 29] will also be a maximal length tap sequence. An interesting behaviour of two such tap sequences is that the output bit streams are mirror images in time.
One characteristic of the LFSR output not shared with a random stream is that the LFSR stream is deterministic. Given knowledge of the present state of the LFSR, the next state can always be predicted.
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7. APPLICATIONS
LFSRs can be implemented in hardware, and this makes them useful in applications that require very fast generation of a pseudo-random sequence, such as direct-sequence spread spectrum radio. LFSRs have also been used for generating an approximation of white noise in various programmable sound generators.. The Global Positioning System uses an LFSR to rapidly transmit a sequence that indicates high-precision relative time offsets.
a linear system, leading to fairly easy cryptanalysis. For example, given a stretch of known plaintext and corresponding ciphertext, an attacker can intercept and recover a stretch of LFSR output stream used in the system described, and from that stretch of the output stream can construct an LFSR of minimal size that simulates the intended receiver by using the BerlekampMassey algorithm. This LFSR can then be fed the intercepted stretch of output stream to recover the remaining plaintext. Three general methods are employed to reduce this problem in LFSR-based stream ciphers:
Non-linear
Non-linear combination of the output bits of two or more LFSRs (see also: shrinking generator); or Irregular clocking of the LFSR, as in the alternating step generator.
Important LFSR-based stream ciphers include A5/1 and A5/2, used in GSM cell phones, E0, used in Bluetooth, and the shrinking generator. The A5/2 cipher has been broken and both A5/1 and E0 have serious weaknesses.
The kernel provides an advantage of required programmability In computing hardware of a Software Defined Radio (SDR) Along with the low power implementation in processing of digital wireless standards and protocols. The proposed kernel uses shared memory-block architecture. It significantly reduces the energy dissipation in the memory accesses (Paccess). There is dominating effect and energy cost in modulus operation. The kernel replaces modulus operation by an equivalent operation, which drastically reduces the number of machine cycles and thus execution time. The kernel has the characteristics of reduced switching activity. A Software Defined Radio (SDR) is required to implement multiple wireless protocols by software . High-end wireless protocols require over 100 million operations per second per milliwatt (Mops/mW). This requirement is about 10 times more than that of most DSP processors. The high definition video and 4G wireless communication require much higher 1000 Mops/mW. The software is therefore required to run on
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the innovatively designed and parallel signal processing units in order that the total energy dissipation is minimized. Energy dissipation during signal processing can be reduced by achieving high Mops/mw as well as by significantly reducing the requirement of Mops themselves Proper use of LFSR polynomial and a systematic optimization approach at all levels of the design enabled a low power design of the kernel.
BROADCASTING
AND
To prevent short repeating sequences (e.g., runs of 0's or 1's) from forming spectral lines that may complicate symbol tracking at the receiver or interfere with other transmissions, linear feedback registers are often used to "randomize" the transmitted bitstream. This randomization is removed at the receiver after demodulation. When the LFSR runs at the same rate as the transmitted symbol stream, this technique is referred to as scrambling. When the LFSR runs considerably faster than the symbol stream, expanding the bandwidth of the transmitted signal, this is direct-sequence spread spectrum. Neither scheme should be confused with encryption or encipherment; scrambling and spreading with LFSRs do not protect the information from eavesdropping. They are instead used to produce equivalent streams that possess convenient engineering properties to allow for robust and efficient modulation and demodulation.
ATSC Standards (digital TV transmission system North America) DAB (Digital Audio Broadcasting system for radio) DVB-T (digital TV transmission system Europe, Australia, parts of Asia)
NICAM (digital audio system for television)
IBS (INTELSAT business service) IDR (Intermediate Data Rate service) SDI (Serial Digital Interface transmission)
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8. CONCLUSION
A linear feedback shift register (LFSR) is the heart of any digital system that relies on pseudorandom bit sequences (PRBS), with applications ranging from cryptography and bit-error-rate measurements, to wireless communication systems employing spread spectrum or CDMA techniques. It is used in the areas of Digital broadcasting, communication and also in the field of military cryptography. In future we can use LFSR in finding angular positions, when taken in blocks of n consecutive positions they form 2n 1different codes in a closed circular sequence. This property can be used for measuring absolute angular positions as the circle can be divided in as many parts as different codes can be retrieved as well as in GPS spreading Codes LFSR can be easily use. The LFSR is a shift register that has some of its outputs together in exclusive-OR configurations to form a feedback path. LFSRs are frequently used as pseudorandom pattern generators to generate a random number of 1s and 0s. Each output of the LFSR is multiplexed with an ASIC input and, when the device is placed in the LFSR (test) mode, the random, high-toggle-rate patterns produced are extremely good for generating high-fault coverage.
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REFERENCES
4. www.google.com 5.
Self-Test Services, The STS ASIC Testability Seminar, Self-Test Services, Ambler, PA, 1989.
6. W.W. Peterson and E.J. Weldon, Jr. Error Correcting Codes, MIT press, Cambridge,
MA 1972.
7. Texas Instruments, SCOPE Cell Design Manual, Texas Instruments Incorporated, Dallas,
TX, 1990.
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