Code No: RR411106 Set No.

1
IV B.Tech I Semester Regular Examinations, November 2006
VLSI DESIGN
(Bio-Medical Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
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1. (a) Find gm and rds for an n-channel transistor with

VGS = 1.2V; Vtn = 0.8V; W/L = 10; µnCox = 92µA/V2 and VDS = Veff.
The out put impedance constant. λ = 95.3 × 10−3 V −1
(b) Define the term Threshold voltage of MOSFET and explain its significance.
[10+6]
2. (a) Compare between CMOS and bipolar technologies.
(b) With neat sketches explain nMOS fabrication process. [8+8]
3. Design a stick diagram for the NMOS logic shown below Y = (A + B + C) [16]
4. Design a layout diagram for the NMOS logic shown below Y = (A + B + C) [16]
5. Calculate on resistance of the circuit shown in Figure 5 from VDD to GND. If n-
channel sheet resistance Rsn = 10 4 Ω per square and p-channel sheet resistance
Rsp = 4.5 × 104 Ω per square. [16]

Figure 5
6. Using PLA Implement Full-adder circuit. [16]
7. What are the different inputs that are provided to the place and route tool and
explain the significance of each input. [16]
8. Explain about the following Die bandings.
(a) Eutectic die bonding.
(b) Epoxy die bonding. [8+8]

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Code No: RR411106 Set No. 2
IV B.Tech I Semester Regular Examinations, November 2006
VLSI DESIGN
(Bio-Medical Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) Explain with neat sketches the Drain and Transfer characteristics of n-channel
enhancement MOSFET.
(b) With neat sketches explain the transfer characteristics of a CMOS inverter.
[10+6]

2. With neat sketches explain how npn transistor is fabricated in Bipolar process. [16]

3. Design a stick diagram for the CMOS logic shown below Y = (A + B).C [16]

4. Design a layout diagram for pMOS inverter. [16]

5. Calculate on resistance of the circuit shown in Figure 5 from VDD to GND. If n-

channel sheet resistance Rsn = 10 4 Ω per square and p-channel sheet resistance
Rsp = 2.5 × 104 Ω per square. [16]

Figure 5
6. With neat sketches explain the architecture of PAL. [16]

7. What is need for RTL simulation? Clearly explain RTL simulation flow in the
ASIC design flow and also mention few leading simulation tools. [16]

8. Clearly explain the wire bonding technology of the die bonding. [16]

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Code No: RR411106 Set No. 3
IV B.Tech I Semester Regular Examinations, November 2006
VLSI DESIGN
(Bio-Medical Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. A MOS Transistor in the active region measured to have a drain current of 20 µA

when VDS =Veff. When VDS is increased by 0.5V, ID increases to 23 µA. Estimate
the out impedance rds , and the out impedance constant λ. [16]

2. With neat sketches explain how pnp transistor is fabricated in Bipolar process. [16]

3. Design a stick diagram for n-MOS Ex-NOR gate. [16]

4. Design a layout diagram for the PMOS logic shown below Y = (A + B).C [16]

5. Explain clearly about different parastic capacitances of an nMOS transistor. [16]

6. Implement Full-adder circuit using PAL. [16]

7. Clearly explain each step of high level design flow of an ASIC. [16]

8. Mention different growth technologies of the thin oxides and explain about any one
technique. [16]

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Code No: RR411106 Set No. 4
IV B.Tech I Semester Regular Examinations, November 2006
VLSI DESIGN
(Bio-Medical Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) Find gm and rds for an n-channel transistor with

VGS = 1.2V; Vtn = 0.8V; W/L = 10; µnCox = 92 µA/V2 and VDS = Veff +
0.5V
The out put impedance constant. λ = 95.3 × 10−3 V−1
(b) Explain the term Figure of merit of a MOS Transistor. [10+6]

2. With neat sketches explain how npn transistor is fabricated in Bipolar process. [16]

3. What is a stick diagram and explain about different symbols used for components
in stick diagram. [16]

4. Explain with suitable examples how design the layout of a gate to maximize per-
formance and minimize area. [16]

5. Calculate the gate capacitance value of 2µm technology minimum size transistor
with gate to channel capacitance value is 8 × 10−4 pF/µm2 . [16]

6. Implement 2-bit comparator using PROM. [16]

7. (a) Define the term DFT and explain about it.

(b) Explain any one test procedure to test sequential logic. [8+8]

8. With neat sketches explain the electron lithography process. [16]

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