Modern processor can feature the following: Hyper threading This term refers to Intels Hyper-Threading Technology(HTT).

simultaneous HTT is a form of SMT multithreading(SMT).

processing. Dual- core processors are common specific case for the multicore technology. Give assignment to students to search latest multicore technologies Cache To aid communication between the CPU and Main Memory, a special type of memory called static RAM is used. Cache memory is the SRAM used in CPU which stores the frequently used instructions and data for quicker processing. The level 1 (L1) cache memory is the first and fastest cache and has been built into the CPU since even before the Pentium. L1 cache lies very close to CPU and has capacity to store data around 8-32 KB. L2 cache memory is the second cache memory larger than the L1 cache (around 256 KB to 1 MB) and is usually slower. The L2 cache memory was external cache before. The third cache memory is L3 cache memory, which is printed in the system boards and are seen only on high-end CPUs (Intel Xeon, Itanium) and has capacity up to 3 MB and growing. Microcode Microcode is the set of instructions that make up the various micro programs that the processor executes while carrying out its various duties. The Multimedia Extensions (MMX) microcode is specialized example of a separate micro-program that carries out a

particular set of functions. Microcode is at a much lower level than the code that makes up application programs. Over clocking

Overclocking is the process of running a computer component at a higher clock rate (more clock cycles per second) than it was designed for or was specified by the manufacturer, usually practiced byenthusiasts seeking an increase in the performance of their computers. Some purchase low-end computer components which they then overclock to higher clock rates, or overclock high-end components to attain levels of performance beyond the specified values. Others overclock outdated components to keep pace with new system requirements, rather than purchasing new hardware.
Throttling

takes advantage of modern CPUs superscalar architecture. Superscalar processors are able to have multiple instructions operating on separate data in parallel. HTT capable processors appear to the operating system to two processors. As a result, the operating system can schedule two processors at the same time, as in the case of symmetric multiprocessing (SMP), where two or more processors use the same system resources.In fact, the operating system must support SMP in order to take advantage of HTT. Multicore A processor that exhibits a multicore

architecture has two completely separate processors in the same package. Whether there are multiple dies in the same package, or the single die contains the equivalent circuitry operating processor of as multiple can it if processors, treat the two the single system

PU throttling/processor throttling is the process when the CPU tries to avoid overheating and getting damaged. So if the temperature of the CPU exceeds some specified limits, the system will throttle down the CPU, allowing it to cool down and avoid damage. This process may also take place when the computer is idle

were

separate

processors. As with HTT, the operating system must support SMP. In addition, SMP is not an enhancement if the applications run on SMP system are not written for parallel

or no difficult tasks are executed on it. The CPU will take a lower frequency so it consumes less energy and so that the fans make less noise. Dynamic frequency scaling (also known as CPU throttling) is a technique whereby "on-the-fly", in computer automatically architecture adjusted

energy use and lengthen battery life. This was introduced initially in the Intel 486SL processor, which is an enhanced version of the 4886DX processor. Subsequently the power management and features into were all universalized incorporated

motherboard or chipset. The second ( back side) bus in a processor with DIB is used for the L2 cache, enabling it to run at much greater speeds than if it were to share the main processor bus. Speed 32 and 64 bit system bus The set of data lines between the CPU and the primary memory of the system can be 32 or 64 bits wide. The wider the bus, the more data that can be processed per unit time, and hence the more work that can be performed.

Pentium and later processors. This feature set is called SMM, which stands for system management mode. SMM circuitry is integrated into physical chip but operates independently to control the processors power use based on its activity level. It enables the user to specify time intervals after which the CPU will be partially or fully powered down. It also supports the suspend/resume feature that allows for instant power on and power off, used mostly with laptop PCs.These settings are typically controlled via system BIOS settings. Dual Independent Bus Architecture The Dual independent Bus (DIB) architecture was first implemented in sixth generation of processors for Intel and AMD. DIB was created to improve processor bus bandwidth and performance. Having two (dual) independent data I/O buses enables the processor to access data from either of its buses simultaneously and in parallel, rather than in a singular sequential manner. The main (often called front side) processor bus is the interface between the processor and the

the frequency of a microprocessor can be either to conserve power or to reduce the amount of heat generated by the chip. Dynamic used frequency scaling is commonly in laptops and other

mobile devices, where energy comes from a battery and thus is limited. It is also used in quiet computing settings and to decrease energy and cooling costs for lightly loaded machines. Less heat output, in turn, allows the system cooling fans to be throttled down or turned off, reducing noise levels and further decreasing power consumption. It is also used for reducing heat in insufficiently cooled systems when the temperature reaches a certain threshold, such as in poorly cooled overclocked systems.
SMM (Power management) Intel has created power management

circuitry that enables processors to conserve