CircuitiMicroelettronici1 2005

CMOS GATES
Design abstraction levels in digital

circuits
2
The Basic MOS Gate: the Inverter
Vin Vout
0 1
1 0
3
The Basic MOS Gate: the Inverter
VM
4
Switching Threshold
• The switching threshold, VM, is defined as the point where

Vin = Vout. Its value can be obtained graphically from the
intersection of the VTC with the line given by Vin = Vout.
• Best value is VM = VDD / 2. This allow to have about same

noise margin for both high and low logic levels.
5
NMOS Inverter with Resistive Load
VDD
R
VDD = R·ID + Vout
Vout
Vin = 0 ⇒ ID = 0 ⇒ Vout = VDD
Vin ID
Vout = 0 ⇒ ID = VDD / R
6
Vin = VOH
VDD ID
VDD / R
R
Vout
Vin ID
Vin = 0
VOL VOH = VDD Vout
7
• VOH = VDD
• VOL: NMOS in linear region and VDS (= VOL) small
β ⋅ (VDD − VTH ) ⋅ VOL = (VDD − VOL ) R , β = µ ⋅ COX ⋅ W L

VOL = VDD [1 + β ⋅ (VDD − VTH ) ⋅ R ]
• VM: Vin = Vout ⇒ Vgs = Vds ⇒ NMOS saturated

β
⋅ (VM − VTH ) = (VDD − VM ) R
2
2
(R ⋅ β ⋅VTH − 1) + 1 + 2 ⋅ R ⋅ β ⋅ (VDD − VTH )
VM =
R⋅β
8
Swotching Threshold
Switching Threshold
2.0
0.750
1.8
1.6 1.000
1.4
1.2
1.250
VDD=2.5V log(W/L)
1.0
VTH=0.5V
1.500
0.8
0.6
1.750
0.4
2.000
0.2
0
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0
log(R)
9
For high input there is static power dissipation
VOH = VDD ☺
VOL is not zero and it depends from

resistor and transistor sizing
(the gate is ratioed)
10
NMOS Inverter with NMOS Load
VDD
VGS2 = VDS2 ⇒ M2 always saturated

M2
VDS2 = VDD – Vout
Vout
Vin = 0 ⇒ ID = 0 ⇒ Vout = VDD – VTH

Vin ID
M1
Vout = 0 ⇒ ID = (β/2)·(VDD-VTH)2
11
Vin = VOH
ID
VDD
M2
Vout
Vin ID
M1
Vin = 0
VOL Vout
VTH
M2 is always satured VOH = VDD -VTH

12
• VOH = VDD-VTH
• VOL: M1 in linear region and VDS = VOL small
β2
⋅ (VDD − VOL − VTH )2 = β 1 ⋅ (VOH − VTH ) ⋅ VOL
2
.......... ......
• VM: Vin = Vout ⇒ M1 saturated

β1 β2
⋅ (VM − VTH ) = ⋅ (VDD − VM − VTH )
2 2
2 2 W1 = W2
VM =
VDD ⋅ β 2 + VTH ⋅ ( β 2 − β1 ) L1 = L2
⇓
β1 + β 2 VM=VDD/2
13
Switching Threshold
Switching Threshold
2.0
1.8
1.750
1.6
1.4
1.500
VDD=2.5V 1.2
VTH=0.5V log(W2/L2)
1.0
1.250
0.8
1.000
0.6
0.4
0.750
0.2
0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
log(W1/L1)
14
For high input there is static power dissipation
VOH = VDD – VTH ⇒ it depends from MOS technology
VOL is not zero and it depends from transistor sizing

(the gate is ratioed)
Solution: the load must be controlled by the input
15
Other two examples
VDD VDD
M2 M2
Vout Vout
Vin Vin
M1 M1
16
Static Complementary CMOS
Pull-up network (PUN) and pull-down network (PDN)
VDD
In1
pull-up: make a connection from VDD to F
In2 PUN
…
when F(In1,In2,…InN) = 1
InN
F(In1,In2,…InN)
In1
pull-down: make a connection from F to GND
In2 PDN
…
InN
17
Threshold Drops
VDD VDD
PUN
S D
VDD
D 0 → VDD S 0 → VDD - VTn

VGS
CL CL
18
Threshold Drops
PDN VDD → 0 VDD → |VTp|

VGS
D CL S CL
VDD
S D
19
Static CMOS Inverter
An Intuitive Perspective
VOH = VDD VOL = 0 independently from device size

Inverter CMOS is ratioless 20
Transfer Characteristic
21
22
23
24
Switching Threshold
• VM: Vin = Vout ⇒ M1 and M2 saturated
(HP: L1 = L2 = L)
µ n ⋅ COX Wn µ p ⋅ COX Wp
⋅ ⋅ (VM − VTHn ) = ⋅ ⋅ (VDD − VM − VTHp )
2 2
2 L 2 L
µ n Wn
VDD − VTHp + VTHn ⋅ ⋅
µ p Wp
VM =
µ n Wn
1+ ⋅
µ p Wp
For VTHn = |VTHp|, µn = 3·µp, Wp = 3·Wn ⇒ VM = VDD / 2 !!!!
25
Switching Threshold
Simulated inverter switching threshold versus PMOS/NMOS ratio
(0.25 µm CMOS, VDD = 2.5 V)
26
Noise Margin
• VIH and VIL are the operational points of the inverter where
the derivative of the transfer characteristic is -1.
• To easily estimate the noise margin a

piecewise approximation of the transfer
characteristic can be used.
• The transition region is approximated by
a straight line, the gain of which equals
the gain g at the switching threshold VM.
27
Noise Margin
• High gain g means high noise margin
• For g = ∞ and VM = VDD / 2, NMH = NML = VDD / 2

28
Noise Margin: g = ?
gmn + gm p 1 ⎛ gmn gm p ⎞
g= , gd = λ ⋅ I ⇒ g = ⋅ ⎜⎜ + ⎟⎟
gd n + gd p λn + λ p ⎝ I I ⎠
β
I = ⋅ (Vgs − Vth ) ⇒ gm = β ⋅ (Vgs − Vth ) ⇒
gm 2
=
2
2 I (Vgs − Vth )
1 ⎛ 2 2 ⎞
g= ⋅ ⎜⎜ + ⎟⎟
λn + λ p ⎝ VM − Vthn VDD − VM − | Vthp | ⎠
VDD ↓ ⇒ VM ↓ ⇒ g ↑
Lp, Ln ↑ ⇒ λn, λp ↓ ⇒ g ↑
29
Scaling the Supply Voltage
30
Device Variations
• Good ⇔ Fast ⇔ Best
• Nominal ⇔ Typical
• Bad ⇔ Slow ⇔ Worst
31
The Transient Behavior
• The propagation delay of the CMOS inverter is determined by
the time it takes to charge and discharge the load capacitor
CL through the PMOS and NMOS transistors, respectively.
• This observation suggests that getting CL as small as possible

is crucial to the realization of high-performance CMOS
circuits.
• When cascading two or more CMOS inverter, CL depend from

the size of the PMOS and NMOS transistors.
32
Charge and Discharge CL
Delay Definition
Vin
Propagation delay
50% tp = (tpHL + tpLH)/2
t
tpHL tpLH
Vout
90%
50% signal slopes
10%
t
tf tr
33
Vin
Vout
PMOS NMOS
ICL
34
Vin 1. NMOS off

PMOS linear region
2. NMOS saturated
PMOS off
Vout
3. NMOS linear region

PMOS off
ICL
1 2 3
35
The Transient Behaviour
Computing the Capacitances
36
Computing the Capacitances
• Rule of Thumb
– Neglect the intrinsic and the wiring caps (OK for small and
close gates), i.e., neglect the self loading
– Neglect the gate-to-source caps of M3 and M4
– CL=(WnLnCox) + (WpLpCox)
37
Delay Calculation
VDD • The closed NMOS transistor can

be modelled by a (non linear)
resistor.
Vout = 0
CL
Rn
tpHL = f(Rn, CL)
Vin = V DD
38
Delay Calculation
• Propagation delay is proportional to the time-constant of the network
formed by the pull-down resistor and the load capacitance
VDD t pHL = ln(2) ⋅ Reqn ⋅ C L ≈ 0.69 ⋅ Reqn ⋅ C L

t pLH = ln(2) ⋅ Reqp ⋅ C L ≈ 0.69 ⋅ Reqp ⋅ C L
Vout = 0 tp =
1
(t pHL + t pLH ) ≈ 0.35 ⋅ (Reqn + Reqp )⋅ CL
2
Rn CL • ln(2) derives from tp definition (Vout from Vdd

to Vdd / 2)
Vin = V DD • Reqn, Reqp = ?
39
Computing the Resistances
• The simplest model assumes the transistor is a switch with
an infinite “off” resistance and a finite “on” resistance Ron
VGS ≥ VT
Ro
S n D
• However Ron is nonlinear, so use instead the average value

of the resistances, Req, at the end-points of the transition
• Since the propagation time definition the start point for the
transition is Vdd, while the end point is Vdd / 2
40
Vin
Vout (t )
t2
1
Reqn = ∫
t 2 − t1 t1 I (t )
dt
VDD
Vout
VDD / 2 t ∈ (t1, t2) the nmos can be
considered always saturated
then I is costant
β
I= ⋅ (VDD − VTH )
2
ICL
2
t1 t2 41
VDD / 2
1 Vout 3 VDD
Reqn = ∫ β
dVout = ⋅
2 β ⋅ (VDD − VTH )2
⋅ (VDD − VTH )
VDD
− VDD
2
VDD
2 2
L 3 VDD
Reqn = Run ⋅ , Run = ⋅
W 2 µ n ⋅ COX ⋅ (VDD − VTH )2
• Run is the equivalent resistance of a squared (W = L) nmos

transistor
• Given the technology and the supply, Run is univocally determined,
so Reqn is directly computed from the transistor size
• Same considerations can be done for Reqp, by defining Rup
42
Delay Calculation
• Being VTHn = |VTHp| and µn ≈ 3·µp we obtain
Rup = 3 ⋅ Run
• To have same tpHL and tPLH, PMOS must be bigger than the
NMOS
⎧Wp = 3 ⋅ Wn
⎨
⎩ Lp = Ln
43
Delay Calculation
VDD • The closed NMOS transistor can

be modelled by a (non linear)
current source.
Vout
In CL
tpHL = f(In, CL)
Vin = V DD
44
Delay Calculation
VDD
Vin
VDD
VDD / 2
Vout
Vout
In CL
In
Vin = V DD t1 t2
45
Delay Calculation
• When Vout goes to Vdd to Vdd / 2 it is possible to suppose
the nmos always saturated i.e., In costant.
C L ⋅ ∆Vout = I n ⋅ t pHL
µ ⋅ Cox W
In = (VDD − VTH )2
2 L
∆Vout = VDD / 2
46
Delay Calculation
C L ⋅ VDD L
t pHL = = Tun ⋅ ⋅ C L
µ ⋅ Cox ⋅ (VDD − VTH )2
W W
L
• Tun is the equivalent propagation of a squared (W = L) nmos

transistor on a unit capacitor (1F)
• Given the technology and the supply, Tun is univocally determined,
so propagation is directly computed from the transistor size and the
load capacitor
• Same considerations can be done for Tup
47
Delay Calculation Comparison
L 3 VDD L
t pHL = ln(2) ⋅ Run ⋅ ⋅ C L = ln(2) ⋅ ⋅ ⋅ ⋅ CL ≈
W 2 µ n ⋅ COX ⋅ (VDD − VTH ) W
2
VDD L
≈ 1.04 ⋅ ⋅ ⋅ CL
µ n ⋅ COX ⋅ (VDD − VTH ) W
2
L VDD L
t pHL = Tun ⋅ ⋅ C L = ⋅ ⋅ CL
W µ ⋅ Cox ⋅ (VDD − VTH ) W
2
The two delay calculation approach give

about the same (approximate) results
48
Delay Calculation
x 10-11
5
t HL + t LH
tpLH tp =
4.5
tpHL 2
4 tp
B of 2.4 gives about
tp(sec)
symmetrical response
3.5 B of 1.6 to 1.9 gives

optimal performance
3
1 2 3 4 5
B = Wp / Wn
49
Improve the Transient Behaviour
• Reduce CL. Three major factors contribute to the load capacitance: the internal diffusion
capacitance of the gate itself, the interconnect capacitance, and the fanout. Careful layout
helps to reduce the diffusion and interconnect capacitances.
• Increase the W/L ratio of the transistors. This is the most powerful and effective
performance optimization tool in the hands of the designer. Proceed however with caution
when applying this approach. Increasing the transistor size also raises the diffusion
capacitance and hence CL. In fact, once the intrinsic capacitance (i.e. the diffusion
capacitance) starts to dominate the extrinsic load formed by wiring and fanout, increasing the
gate size does not longer help in reducing the delay, and only makes the gate larger in area.
This effect is called “self-loading”. In addition, wide transistors have a larger gate
capacitance, which increases the fan-out factor of the driving gate and adversely affects its
speed.
• Increase VDD. The delay of a gate can be modulated by modifying the supply voltage. This
flexibility allows the designer to trade-off energy dissipation for performance, as we will see in
a later section. However, increasing the supply voltage above a certain level yields only very
minimal improvement and hence should be avoided. Also, reliability concerns (oxide
breakdown, hot-electron effects) enforce firm upper-bounds on the supply voltage in deep
sub-micron processes.
50
Increase VDD
51
Increase Sizes
x 10-11
3.8
for a fixed load The majority of the
3.6
3.4 improvement is already
3.2 obtained for S = 5. Sizing
3 factors larger than 10
barely yield any extra gain
tp(sec)
2.8
2.6 (and cost significantly
2.4 more area).
2.2
2
1 3 5 7 9 11 13 15 self-loading effect (intrinsic
S capacitance dominates)
52
Optimum Transistor Sizing
53
54
55
Choosing f
56
Choosing f
57
Choosing f
7
• Choosing f larger than
6
optimum has little effect on
normalized delay
5 delay and increase the

4 number of stages (and
3 area).
2
– Common practice to use f = 4
– But too many stages has a
1
substantial negative impact on
0 delay
1 1.5 2 2.5 3 3.5 4 4.5 5
f
58
Choosing f
1
N f tp [ps]
Cg,1 = 1 CL = 64 Cg,1
1 8 1 64 65
Cg,1 = 1 CL = 64 Cg,1
2 8 18
1 4 16
Cg,1 = 1 CL = 64 Cg,1 3 4 15
1 2.8 8 22.6
4 2.8 15.3
Cg,1 = 1 CL = 64 Cg,1
59
Input Signal Rise/Fall Time
x 10-11
5.4
• In reality, the input signal changes
5.2 gradually (and both PMOS and
5 NMOS conduct for a brief time).
4.8 This affects the current available for
4.6
charging/discharging CL and impacts
tp(sec)
propagation delay.
4.4
• tp increases linearly with increasing
4.2
input slope, ts, once ts > tp
4
• ts is due to the limited driving
3.8
capability of the preceding gate
3.6
0 2 4 6 8 x 10-11
ts(sec)
60
Energy and Power
• CMOS inverter with its almost ideal VTC — symmetrical

shape, full logic swing, and high noise margins — offers a
superior robustness, which simplifies the design process
considerably and opens the door for design automation.
• Another major attractor for static CMOS is the almost
complete absence of power consumption in steady-state
operation mode. It is this combination of robustness and low
static power that has made static CMOS the technology of
choice of most contemporary digital designs.
• The power dissipation of a CMOS circuit is instead dominated
by the dynamic dissipation resulting from charging and
discharging capacitances.
61
Dynamic Dissipation due to Charging and
Discharging Capacitances
Each time the capacitor CL gets

charged through the PMOS
transistor, its voltage rises from 0 to
VDD, and a certain amount of energy
is drawn from the power supply. Part
of this energy is dissipated in the
PMOS device, while the remainder is
stored on the load capacitor. During
the high-to-low transition, this
capacitor is discharged, and the
stored energy is dissipated in the
NMOS transistor.
62
Gate is switched on and off

f0→1 times per second
INDEPENDENT FROM THE PMOS AND NMOS SIZES

63
Minimize the Dynamic Dissipation
• Reduce VDD
• Reduce load capacitances
• Reduce the switching activity (i.e., f0→1)

64
Reducing the Switching Activity
• Y = CK + A + B
• A, B with very low frequency change with respect CK
CK A
A B
Y Y
B CK
Only the last gate has high

Both gates has high switching activity switching activity
65
Dissipation Due to
Direct-Path Currents
• Ipeak is determined by the saturation current of the devices and is hence

directly proportional to the sizes of the transistors.
• The peak current is also a strong function of the ratio between input and
output slopes.
66
Dissipation Due to
67
Dissipation Due to
68
Dissipation Due to
Minimize the Direct-

Path Dissipation
• Reduce VDD
• Optimize rise / fall
time of the input
69
Optimize Rise / Fall Time of the Input
Generate proper transistor input signal in order to
never have both PMOS and NMOS on
VDD in
inp inp
inn
in out
out
inn P on P off P on
N off N on N off
GND
P off P off
N off N off
70
Static Complementary CMOS
Pull-up network (PUN) and pull-down network (PDN)
VDD
In1
pull-up: make a connection from VDD to F
In2 PUN
…
InN
F(In1,In2,…InN)
In1
pull-down: make a connection from F to GND
In2 PDN
…
InN
PUN and PDN are dual logic networks

71
NMOS Transistors in Series/Parallel
Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
A B
X Y Y = X if A and B
X B Y = X if A OR B
Y
NMOS Transistors pass a “strong” 0 but a “weak” 1

72
PMOS Transistors in Series/Parallel
Connection
PMOS switch closes when switch control input is low
A B
X Y Y = X if A AND B = A + B
X B Y = X if A OR B = AB
Y
PMOS Transistors pass a “strong” 1 but a “weak” 0 73

Complementary CMOS Logic Style
• PUN is the DUAL of PDN (can be shown by using

De Morgans Theorem)
A + B = A⋅ B A⋅ B = A + B
• The basic gates are inverting
74
NAND CMOS
75
NOR CMOS
76
NAND static behaviour
77
NAND dynamic behaviour
3
Input Data Delay
2,5
A=B=1→0 Pattern (psec)
A=B=0→1 67
2
A=1 →0, B=1
A=1, B=0→1 64
Voltage [V]
1,5
A=1, B=1→0 A= 0→1, B=1 61
1
A=B=1→0 45
0,5
A=1, B=1→0 80
0
0 100 200 300 400 A= 1→0, B=1 81
-0,5
time [ps]
78
Complex CMOS Gate: PDN
F = D + A • (B + C)
79
F = D + A • (B + C)
B C
80
F = D + A • (B + C)
B C
81
F = D + A • (B + C)
D B C
82
Complex CMOS Gate: PUN
VDD VDD
C
SN1 F SN4 A
F
SN2 B
A A
D D SN3
B C B C D
(a) pull-down network (b) Deriving the pull-up network A

hierarchically by identifying
D
sub-nets
B C
(c) complete gate
83
Complex CMOS Gate
Dynamic Design
To simplify the design it is possible assume that series
of transistors can be considered as one transistor with
scaled width scaled according the number of device
L
Req = Ru
Mn = W / L ⇔ Mx = (W / n) / L W n
M2 = W / L They can drive the same amount of current
M1 = W / L
84
Complex CMOS Gate
Dynamic Design
Parallels of transistors can be considered in worst case
condition as one transistor with same size
L
M1 = W / L Mn = W / L ⇔ Mx = W / L Req = Ru
W
In the worst case they drive the same amount of current
85
Complex CMOS Gate
Dynamic Design
Hp: Cin = CL
86
Complex CMOS Gate
Dynamic Design
87
Complex CMOS Gate
Dynamic Design
2
1
2 2
88
Complex CMOS Gate
Dynamic Design
12
6
12
2
1
2 2
89
Complex CMOS Gate
Dynamic Design
Use a two level logic network and design to have same propagation time
of a unit inverter with load cap equal to its input cap.
F = A + B ⋅C
90
Complex CMOS Gate
Dynamic Design
Use only basic gates and design to have same propagation time
of a unit inverter with load cap equal to its input cap.
F = A + B ⋅C = A⋅ B ⋅C
91
Complex CMOS Gate
Fan In Considerations
A B C D
Four input NAND gates
A CL
B C3
C C2
D C1
92
Complex CMOS Gate
Fan In Considerations
A B C D
• For the moment we have supposed
CL > C1 + C2 + C3
A CL • and so the delay is approximately
(R1 + R2 + R3 + R4)·CL
B C3
C C2 • Otherwise ?
– Distributed RC
D C1
93
Complex CMOS Gate
Distribuited RC (Elmore Delay)
94
Complex CMOS Gate
• Progressive sizing
InN MN CL Distributed RC line
M1 > M2 > M3 > … > MN

In3 M3 C3
(the FET closest to the output
In2 M2 C2 should be the smallest)
In1 M1 C1
95
Complex CMOS Gate
A 3 B 3 C 3 D 3
A 44 CL=100 fF
B 45 C3
Progressive sizing in pull-down
C 46 C2
chain gives up to a 20%
improvement. D 47 C1
96
Complex CMOS Gate
tp as a Function of Fan-In (NAND Gate)
• Propagation delay deteriorates rapidly as a function of fan-in,
quadratically in the worst case.
• Gates with a fan-in greater than 4 should be avoided
1250
quadratic
1000 function of fan-in
750
tp (psec)
tpHL tp
500
250 tpLH linear function of

fan-in
0
2 4 6 8 10 12 14 16
fan-in 97
CMOS Gates Styles
• Static complementary CMOS - except during switching, output

connected to either VDD or GND via a low-resistance path
– high noise margins
• full rail to rail swing
• VOH and VOL are at VDD and GND, respectively
– low output impedance, high input impedance
– no steady state path between VDD and GND (no static
power consumption)
– delay a function of load capacitance and transistor
resistance
– comparable rise and fall times
98
Problems with CMOS
• Gate with N inputs requires 2N transistors

– other circuit styles use N+1 transistors
• tp deteriorates with high fan-in
– series connected transistors slows down gate
– increases total capacitance
• fan-out loads down gate
– 1 fan-out = 2 gate capacitors (PMOS and NMOS)
99
Dynamic Logic: Basic Principles
The PDN (pull-down network)

is constructed exactly in the
same fashion as a
complementary CMOS. The
operation of this circuit can be
divided into two major
phases: precharge and
evaluation, with the mode of
operation determined by the
clock signal.
100
Precharge
When CLK = 0, the output node Out is precharged to
VDD by the PMOS transistor Mp. During that time,
the evaluate NMOS transistor Me is off, so the pull-
down path does not fight the pull-up path.
Evaluation
When CLK = 1, the precharge transistor Mp is off,
and the evaluation transistor Me is turned on. The
output is conditionally discharged based on the input
values and the pulldown topology. If the inputs are
such that the PDN conducts, then a low resistance
path exists between Out and GND and the output is
discharged to GND. If the PDN is turned off, the
precharged value remains stored on the output
capacitance CL.
101
CLK
In
Out
precharge evaluation precharge evaluation
In must be fixed during the evaluation phase !!

102
Dynamic Logic: Properties
• The logic function is implemented by the NMOS pull-down network. The

construction of the PDN proceeds just as it does for static CMOS.
• The number of transistors (for complex gates) is substantially lower than in
the static case: N + 2 versus 2N.
• It is nonratioed. The sizing of the PMOS precharge device is not important
for realizing proper functionality of the gate.
• It only consumes dynamic power. Ideally, no static current path ever exists
between VDD and GND. The overall power dissipation, however, can be
significantly higher compared to a static logic gate.
• The logic gates have faster switching speeds. There are two main reasons
for this. The first reason is due to the reduced load capacitance attributed
to the number of transistors per gate and the single-transistor load per fan-
in. Second, the dynamic gate do not have short circuit current, and all the
current provided by the pull-down devices go into discharging the load
capacitance.
103
Dynamic Logic: Properties
• The low and high output levels VOL and VOH are easily identified as GND
and VDD and are not dependent upon the transistor sizes.
• The other VTC parameters are different from static gates.

– Noise margins and switching thresholds have been defined as static
quantities, which are not influenced by time. To be functional, a dynamic gate
requires a periodic sequence of precharges and refreshes. Pure static
analysis, therefore, does not apply. During the evaluate period, the pull-down
network of a dynamic inverter starts to conduct when the input signal exceeds
the threshold voltage (VTn) of the NMOS pull-down transistor.
• It is reasonable to set the switching threshold (VM) as well as VIH and VIL
of the gate equal to VTn. This translates to a low value for the NML.
104
Dynamic Logic:
Precharged and Predischarged
VDD VDD
CLK CLK
Mp Me
Out
In1
In1 In2
PUN
In2 In3
PDN
In3
Out
CLK CLK
Me Mp
105
Dynamic Logic:
Precharged and Predischarged
106
Connect Dynamic Gates
Out2 is at an intermediate voltage level, so the second gates

does not work properly
107
Cascading problems arise because the output (and hence the

input to the next PDN stage) is precharged to 1. Setting the
inputs to 0 during precharge could solve this problem. In doing
so, all logic transistors of the next function block are turned off
after precharge, and no inadvertent discharging of the storage
capacitors can occur during evaluation. In other words, correct
operation is guaranteed as long as the inputs can only make a
single 0 to 1 transition during the evaluation period. This
eliminates the inadvertent discharging since transistors will only
be turned on when needed and at most one time per cycle.
108
Domino Logic
109
Domino Logic
In = 0 In = 1
VDD VDD
CLK CLK CLK

Mp Mp
In Out2
Out1
Out1
CLK CLK
Me Me
Out2
110
No-Race (NORA) Logic
111
No-Race (NORA) Logic
P E P E P E
VDD VDD CLK
CLK CLK
Mp Me In
In Out1 Out1
Out2
CLK CLK Out2
Me Mp
112
to Static Gates
• Output of dynamic gates is high (low) during the

pre(dis)charge phase and became valid during the evaluation
phase so it cannot used directly by a static gate
• The solution: use a logic interface that properly sample and

hold the output of a dynamic gate thus obtaing a signal suited
for static gates
C2MOS INVERTER
113
C2MOS Inverter
E P E P E P
VDD CLK
CLK
In*
In Out
CLK
Out
(*) In from a precharge dynamic gate

114
Dynamic OR with C2MOS Inverter
VDD
CLK
CLK
Out = A + B
A B CLK
CLK
GND
115
An Example
F = A+ B +C⋅D
3 level NORA logic with NAND-NOR synthesis + C2MOS
Direct and bar signal availables
Design the cell to have same propagation time as a unit inverter

with load cap equal to its input cap
116
Complex CMOS Gate
Rules of Thumb for Fast Designs
• Equalize loaded delay in every stage

• If delays not equal,
– Make the gate with the longest delay larger, which
decreases its delay but increases predecessor’s,
but the overall delay decreases as long as the
delay reduction is greater than the increase in
predecessor’s delay
• Repeat until all delays are equal
117
Complex CMOS Gate
Rules of Thumb for Fast Designs
• Keep fanouts of all gates less than 5

• Keep delays of gates in critical path roughly
the same
• Limit fanin
• Large fanin gates should have fewer fanouts
• Use short buffer chains (sometimes one
inverter) when necessary
118
MOS REFERENCES
Introduction
• Analog circuits incorporate voltage and current references
extensively. Such references are dc quantities that exhibit little
dependence on supply and process parameters and a well-defined
dependence on the temperature.
• In most applications, the required temperature dependence
assumes one of three forms:
– proportional to absolute temperature (PTAT);
– constant - Gm behavior;
– temperature independent.
We deal with the study of current and voltage reference

generators in CMOS technology
120
Current-mirror biasing
using a resistor
VDD Iout = (VDD-Vgs1) / R1
R1 Iout = (β / 2)·(Vgs1-Vth)2
At small signals and low frequencies

M1=M2 Iout
M1 M2
Iout is quite sensitive to VDD
121
Current-mirror biasing
using MOS
β1
I out = ⋅ (Vgs1 − Vth )
2
VDD 2
β0
I out = ⋅ (Vdd − Vgs1 − Vth )
2
M0 2
β 0 = β1 ⇒ Vgs1 = Vdd 2
Iout
β1 ⎛ Vdd
2
⎞
M1 M2
I out = ⋅⎜ − Vth ⎟
2 ⎝ 2 ⎠
Iout is quite sensitive to VDD

and to threshold of M0
122
Supply Independent Bias
123
MOS transistors are supposed to be biased in weak inversion region

124
125
Currents are also equal when Vg = 0, i.e., I1 = I2 = 0

even if this point is not shown in the graph.
126
Force I1 and I2 equal

with a current mirror:
that’s the bias circuit
127
128
NMOS in weak inversion region
I2 = Is·exp(Vgs2/(n·UT)) = I
I1 = M·Is·exp(Vgs1/(n·UT)) = I
Vgs2 = Vgs1 + R · I
I = log(M)· n·UT / R
No Vdd and Is, only n

129
What happen in strong inversion region ?
No Vdd and VT, only β = µ·Cox

130
NMOS in weak inversion

n ⋅U T
I = log(M ) ⋅
R
NMOS in strong inversion
2
2 ⎛ 1 ⎞
I= ⋅ ⎜1 − ⎟
β ⋅ R2 ⎝ M ⎠
131
Supply Independent Bias:
Some Measurements
Strong
I inversion
Weak
inversion
R 132
VDD Sensitivity
VDD
M3 ≡ M4
M1 ≡ M · M2
M3 M4
Iout Iout
gm3 = gm4 = gmp
M1 M2 gd4 = gnp = λp · Iout
gm1 = M · gm2 = M · gmn
gd1 = gdn = λn · Iout
133
VDD Sensitivity
vdd
gmp gmp·vy gdp
vy
gdn M·gmn·(vx-R·iout) gmn
vx S = iout / vdd = ?
·
R
iout
iout iout – M · gmn · (vx – R · iout)

vdd = + + R · iout
gmp gdn
gmn · vx – gmp · vy
vdd = vx +
gdp
iout
vy =
gmp
134
VDD Sensitivity
λn + M · λp
S=
1-M
+ M · R · gmn
Iout Iout
λp, λn ↓ i.e., long devices and / or

cascode for both pmos and nmos mirror
gmn
↑, i.e., weak inversion for nmos transistors
S↓⇒ Iout
1-M
↑, i.e., Iout ↓
Iout
135
Improve VDD Rejection
VDD min = ?
136
Ensure Start-Up
An important issue in supply-

independent biasing is the existence
of “degenerate” bias points. For
example, if all the transistors carry
zero current when the supply is
turned on, they may remain off
indefinitely because the loop can
support a zero current in both
branches. In other words, the circuit
can settle in one of two different
operating condition.
137
Ensure Start-Up
138
Ensure Start-Up
139
Ensure Start-Up
140
Stability
The bias will oscillate

for Cr ≈ Cg
141
Temperature Sensitivity
142
Temperature Sensitivity
NMOS in weak inversion

n ⋅U T
I = log(M ) ⋅
R
NMOS in strong inversion
2
2 ⎛ 1 ⎞
I= ⋅ 1−
2 ⎜ ⎟
β ⋅R ⎝ M ⎠
143
Costant gm Biasing
It is desirable to bias the transistors such that their transconductance
does not depend on the temperature, process, or supply voltage.
Vgs
n⋅U T ID
Weak inversion I D = I0 ⋅ e ⇒ gm =
n ⋅U T
β
ID = ⋅ (Vgs − Vth ) ⇒ gm = 2 ⋅ β ⋅ I D
2
Strong inversion
2
144
Costant gm Biasing
• Weak inversion: bias circuit designed with NMOS in weak inversion
ID log(M ) ⋅ n ⋅ U T R log(M )
gm = = =
n ⋅U T n ⋅U T R
• Strong inversion: bias circuit designed with NMOS in strong inversion
2
2 ⎛ 1 ⎞ 2 ⎛ 1 ⎞
gm = 2 ⋅ β ⋅ I D = 2 ⋅ β ⋅ ⋅ ⎜ 1 − ⎟ = ⋅ ⎜ 1 − ⎟
β ⋅R ⎝
2
M⎠ R ⎝ M⎠
In both cases transconductance does not depend on

temperature, process (except for R), or supply voltage.
145
Body Effect
• If nwell process, all the nmos bulk are
VDD
connected together to ground through
the substrate.
M3 M4 – M2 has its source connected to ground, so
it does not suffer of body effect.
Iout Iout – M1 has its source connected to a resistor,
so Vs ≠ Vbulk. M1 suffers of body effect.
M1 M2
• Due to body effect on M1, the circuit

behaviour deviates from the equations
previously discussed.
146
Body Effect
VDD
• Dual architecture: use a

pmos mirror instead of a
nmos mirror to determine
the current.
• The pmos transistors has
their sourses connected to
their corresponding bulk
(nwell), i.e., they does not
share the same nwell.
GND
147
Body Effect
VDD NMOS in weak inversion region
I2 = Is·exp(Vgs2/(n·UT)) = I
I1 = M·Is·exp(Vgs1/(n·UT)) = I
R
Vgs2 = Vgs1 + R · I
M2 M1
I = log(M)· n·UT / R
GND
No Vdd and Is, only n

No body effect !
148
Another solution
VDD VDD VDD
M1 in strong inverion and saturated region:
M3 M4
2 ⋅ Iout
R ⋅ Iout = Vgs1 = Vth1 +
I I
M5
β
Iout
M2
R·I
M1
R Vgs1
Vth1
• Threshold voltage is not well controlled
• Similar behaviour for M1 in weak inversion

I
149
Temperature (and Supply)
Independent Voltage Reference
• How to generate a quantity that remains constant with
temperature?
– If two quantities having opposite temperature coefficients
(TCs) are added with proper weighting, the result displays
a zero TC.
VREF = α1 ⋅ V1 + α 2 ⋅ V2
∂VREF ∂V ∂V
= α1 ⋅ 1 + α 2 ⋅ 2 = 0
∂T ∂T ∂T
150
Negative TC voltage
151
Positive TC voltage (1)
VDD
n·I I
+ ∆Vbe -
k
= 0.087 mV o
K
q
152
Positive TC voltage (2)
VDD
I I
+ ∆Vbe -
1 n
153
Bandgap Reference
VBE -1.5mV/°K
I
α1
T VBE
0.087mV/°K + VREF=α 1·VBE+α 2·ln(n)·VT
VT
ln(n)·VT
α2
generator
T 154
Bandgap Reference
VDD
Making Va = Vb = VREF,
the voltage across R is a ∆VBE
I I
Va Vb
VREF is a linear combination of ∆VBE and VBE
R
Since ln(n) = 17.2 translates to a prohibitively large n,

1 n the term R·I = VT·ln(n) must be scaled up by a
reasonable factor.
Q1 Q2
155
Bandgap Reference
R1 R2
-
+ Vout
R3
1 n
Q1 Q2
R1=R2
156
Bandgap Reference
157
Bandgap Reference
Collector Current Variation
R1 R2
-
+ Vout
R3
1 n
Q1 Q2
R1=R2
158
Bandgap Reference
Compatibility with CMOS Technology
R1 R2
-
+ Vout
R3
Q1 Q2
1 n
R1=R2
159
Bandgap Reference
Complete Circuit
VDD
Vout
R1 R2
R3
Q1 Q2
1 n
R1=R2
VDD min = ?
160
Bandgap Reference
A Simulation Results
• Bandgap voltages exhibit

a finite “curvature,” i.e.,
their TC is typically zero at
one temperature and
positive or negative at
other temperatures.
• The curvature arises from
temperature variation of
base-emitter voltages,
collector currents, and
offset voltages.
161
Bandgap Reference
OPAMP offset
R1 R2
-
Vos A1
+ + Vout
R3
Q1 Q2
1 n
R1=R2
162
Bandgap Reference
Reduction of the OPAMP offset effect
163
Bandgap Reference
Feedback Polarity
R1 R2
-
+ Vout
R3
Q1 Q2
1 n
R1=R2
164
Bandgap Reference
Supply Dependence and Startup
R1 R2
Y -
+ Vout
X
R3
Q1 Q2
1 n
R1=R2
165
Bandgap Reference
Variations for Different Samples
VREF
This effects can make unusable the reference circuit

since ∆VREF vs. T became to high
166
Bandgap Reference
Variations for Different Samples
VREF
• Resistors are implemented by polysilicon stripes

with ±30% (for example) of tolerance.
• Resistor variations does not change resistor ratioes,
but change BJT collector current, thus changing the
VREF vs. T characteristic Resistivity
167
Bandgap Reference
Trimming
R1 R2
• To avoid variations for different samples
- the resistors of each samplecan be trimmed
+ Vout in order to cope with poly resistivity and other
process variations.
• Trimming can be implemented by implementing
R3 each resistor by using several series or parallel
resistors and by changing the interconnections
1 n through switches.
• Signal controlling the switches can be stored
Q1 Q2
by using E2 technologies or poly fuses.
R1=R2
168
Bandgap Reference
Another Circuit
169
Bandgap Reference
Speed Issue
170
Bandgap Reference
Speed Issue
171
Bandgap Reference
Noise Issue
172
Bandgap Reference
Another Circuit
Being Iq1 = Iq2 = I
VREF
R1 ∆VR2 = ∆VBE1 – ∆VBE2=VT·log(n)

R2
Q1 Q2 VREF = VBE1 + 2 · R1 · ∆VR2 / R2

1 n
I I
VREF = VBE1 + 2 · R1 · VT·log(n) / R2
173
Bandgap Reference
Another Circuit
VDD
1 2
VREF
R1
R2
Feedback
Amplifier Q1 Q2
1 n
1 1 1
GND
174
Bandgap Reference
Another Circuit
VDD
VREF
R1
R2
Feedback Q1 Q2
Amplifier 1 n
R R
175
Voltage Source
• The voltage reference is supply and
temperature independent but:
– it is not easily programmable
– some implementations feature a high / medium
output impedance, i.e., they cannot drive low
impedance load (i.e., deliver high current value)
How build Programmable Voltage Source ?
176
Voltage Source
Vdd • Vout depend on the

RA
power supply
Vout • Vout depend on the load
RL
RB RL
RB // RL This is not a good

Vout = ⋅ Vdd
RA + RB // RL voltage source
177
Voltage Source
VREF Vdd • To improve the circuit, a

local feedback can be
A0 RA used to adap the value
Vout of RA to compensate for
power supply and load
RB RL variations
• A fixed reference is
used to determice Vout
RA = A0 ⋅ (Vout − Vref )
178
Voltage Source
VREF Vdd ⎧ RB // RL
⎪Vout = R + R // R ⋅Vdd
⎨ A B L
RA ⎪ R = A ⋅ (V − V )
A0 ⎩ A 0 out ref
Vout Being A0 very high

(e.g., > 40dB)
RB RL
Vout = Vref ∀ Vdd , RL
The feedback regulates Vout with respect

power supply and load variations 179
Programmable Voltage Source
VREF Vdd
⎧ RB // RL
⎪Vout = R + R // R ⋅ Vdd
RA ⎨ A B L
A0 ⎪ R = A ⋅ (V − V )
Vout ⎩ A 0 x ref
Being A0 very high

RB1 RL (e.g., > 40dB)
Vx
RB2 ⎛ RB1 ⎞
Vout = ⎜⎜1 + ⎟⎟ ⋅Vref ∀ Vdd , RL
⎝ RB 2 ⎠
180
Programmable Voltage Source
VREF Vdd
⎛ RB1 ⎞
RA Vout = ⎜⎜1 + ⎟⎟ ⋅Vref ∀ Vdd , RL
A0 ⎝ RB 2 ⎠
Vout
RB1 RL
This circuit is
commonly known as
RB2 Linear Voltage
Regulator
181
Voltage Regulator
What is RA ?
• RA is a voltage / current controlled resistance.
• The relation between the control variable and
the controlled resistance can be non linear but
is must be monotonic !!
• RA can be implemented through a bipolar or a
mos transistor (called pass device), and the
feedback can be implemented through an
operational amplifier.
182
Voltage Regulator with BJT
VREF Vdd VREF Vdd
+ -
- Vout + Vout
RB1 RB1
RB2 RB2
183
Voltage Regulator with MOST
VREF Vdd VREF Vdd
+ -
- Vout + Vout
RB1 RB1
RB2 RB2
184
Voltage Regulator
Low Drop Out (LDO)
⎛ R1 ⎞
VREF Vdd Vout = ⎜⎜1 + ⎟⎟ ⋅ Vref , Vout ∈ (Vref , Vdd − ∆V )
⎝ R2 ⎠
-
• ∆V is called minimum drop-out and
+ represents the minimum VDS needed
Vout to the PMOS pass device to work
properly.
R1 • The PMOS can work both in
saturation and linear region. This
depend from the power supply and
CL the load.
R2 • CL is needed for stabilization and to
deliver currents for fast load
variations
185
LDO Voltage Regulator
Closed Loop Small Signal Analysis
• Small signal considerations cen be done by
supposing:
– fixed load and variable supply
– fixed supply and variable load
• We consider the first condition and the following
assumptions:
– OPA modelled as a first order system with gain A0
and pole d
– Current flowing the resistor ladder neglected
186
VREF Vdd d1
A0
Guadagno [dB]
+ Vout
R1
VFB
CL
R2 fd1 GBW
Frequenza [Hz]
VOPA =
A0
(V+ − V− ) = A0 (VFB − VREF ) , d1 = A0
1 + s ⋅ d1 1 + s ⋅ d1 2π ⋅ GBW
187
vdd
S
G
+
vopa -gm (vopa-vdd) 1/gd
D
CL
ic vout
vOPA =
A0
1 + s ⋅ d1
⋅ vOUT vdd = vout +
1
gd
[
⋅ ic + g m ⋅ (vopa − vdd ) ]
188
gm
1+
v (s ) s+a
T (s ) = out =
gd
= G⋅ 2
vdd (s ) 1 + s ⋅ C L + g m ⋅ A0 s + 2 ⋅ ξ ⋅ ω n ⋅ s + ω n2
gd g d 1 + s ⋅ d1
g m ⋅ 2π ⋅ GBW 1 ⎡ 2π ⋅ GBW ⋅ C L g d ⎤
ωn = , ξ= ⋅⎢ + ⎥
CL g m ⋅ 2π ⋅ GBW ⎣ 2 A0 2⎦
189
• Increasing the gain of the

OPA, the LDO became
less sensible to static
supply variations
• Increasing the GBW of the

OPA, the LDO became
less sensible to dynamic
supply variations
190
Delta Vout [V] Delta Vout (line regulation)
0.14 0
10
0.12
0.10
0.08 −1
10
0.06
0.04
0.02 −2
10
−0.02
t GBW
−0.04 −3
0 1e−5 2e−5 3e−5 4e−5 5e−5 10 6 7 8
10 10 10
Increasing the GBW, the LDO responce to a supply step improve

but there are more oscillations.
191
Open Loop Small Signal Analysis
• Resr is the series resistance
presented by the load
VREF Vdd
capacitor CL
- • CB is the by-pass capacitor
IL
used to filter the high
+ Vout
VFBI frequencies
R1
CL CB
• The OPA is modelled as a
VFBO current source with a finite
output resistance Ropa and
R2
capacitance Cpar
Resr
• Cpar is due mainly to the
gate cap of the PMOS pass
device
192
vopa R1
Cpar CL CB
Ropa gd
gma·vfbi -gm·vopa vfbo
R2
Resr
v ofb (s )
T (s ) =
v ifb (s )
193
1 gd
P1 ≈ ⋅ P1
2 ⋅π CL 40
1 1
P2 ≈ ⋅
2 ⋅ π Resr ⋅ C B
Guadagno [dB]
Z1 P2
1 1
P3 ≈ ⋅
20
2 ⋅ π Ropa ⋅ C par
1 1
Z1 ≈ ⋅ P3
2 ⋅ π Resr ⋅ C L 1K 10K 100K 1M
Frequenza [Hz]
194
• Poles and zeroes are not at fixed frequencies; they
depend on load and power supply. This could mean
instability.
– A change in the load and / or the power supply change the
PMOS pass device transconductance and output
conductance, thus changing poles and zeroes positions.
• Load and power supply modify also the open loop
gain.
– For low drop-out (i.e., power supply little bit higher that the
output voltage) the open loop gain is very high. This could
mean instability.
195
VREF Vdd
• Solution: use compensation
techniques in order to improve -
stability.
+ Vout
– Typical compensation
techniques are implemented R1
by using a miller VFB
capacitance.
CL
R2
196
VBAT
1 M M2
M1
Mnativo
Ibias
MOUT
VOUT
C R
M4
M3
VBG R2
Compensation
M : 1 M6 1 : M M8 R1
M5 M7
M9
197
*******
100
Iload=1mA
90
Iload=5mA
Dominat pole
Iload=10mA
80 output capacitor
70
Iload=50mA
60
50
Iload=100mA
40
30
20
2nd and 3rd pole

10
with small damping factor
0 at "strong" loads
Volts dB (lin)
due to the second stage of the am

-10
-20
-30
-40
ESR zero -->
-50
Differential pair pole -->

-60
-70
-80
-90
-100
-110
1 10 100 1k 10k 100k 1x 10x
198
*******
-88
-90
• Phase strongly depend
on the load of the
-92
-94
regulator
-96
-98
PHASE VS LOAD CURRENT
• The minimum phase

-100
-102
margin is achieved
-104
-106
Measures (lin)
when the regulator open

-108
-110
-112
-114
loop gain is maximum
-116
-118
-120
-122
-124
-126
199
10u 100u 1m 10m
Line and Load regulation
Supply changed from 3.6V to 4V in Load changed from 10mA to 100mA

5µs for a fixed load current in 5µs fora fixed supply voltage
200
Power Supply Rejection Ratio
201
Switching Voltage Regulator
• In the linear voltage regulator the energy is
continuoulsy transfered from the power supply to the
load though a pass device. The transfer is regulated
by feedback, in order to mantain the output voltage
to a fixed value.
• A switching regulator use capacitors and / or
inductors to store energy that is transfered to the
load in discreet packages. The transfer is regulated
by feedback, in order to mantain the output voltage
to a fixed value.
202
Buck Converter
Vdd
Regulating
loop L Iload
Vp
IL
Reference Vout
D
C
203
Buck Converter
Vdd Transient expired and switch closed
Vp
L Iload
Vp
IL t
Vout IL
D
C
t
ton
d IL 1
Vdd − Vout = L ⋅ , IL = ∫ (Vdd − Vo)dt
dt L 204
Buck Converter
Transient expired and switch open
Vdd
Vp
L Iload
Vp t
IL
IL
D Vout
0.6V
C t
ton toff
d IL 1
0.6 − Vout = L ⋅ , IL = − ∫ (0.6 + Vo) dt
dt L
205
Buck Converter
Vp
ton
D= = duty cycle
t ton + toff
IL ∆IL D ∈ (0,1)
1
∫ (Vdd − Vout )dt − ∫ (0.6 + Vout )dt = 0
1
L ton L toff
⋅ (Vdd − 0.6 ) = D ⋅ (Vdd − 0.6 )

ton
Vout =
ton + toff
206
Buck Converter
D
1.2V 50mV R
L Iload
- I
V Vp
+ E
IL
R
Vout
Vout = D ⋅ Vdd
207
BUCK Converter Output Voltage
Vout
nmos
gate
signal
208
Buck Converter
Small Signal Analysis
Vdd
Regulating
loop L
Vp Iload
IL
D Vout
Reference C
Vin Vout
• The regulatong loop and the switch+diode can be linearized and

approximated by a voltage controlled voltage source.
• Since the values of L and C, the parassitic caps can be neglected.
209
Buck Converter
L Vout
-40dB/decade
+ C
A0·Vin -20dB/decade
Resr
1 1 π/2
fp = fz =
2π LC 2π Resr C
L = 10 µ H , C = 47 µ F , Resr = 150mΩ fp fz
fp ≅ 7 KHz , fz ≅ 22 KHz
fck = 450 KHz 210
Buck Converter
-40dB/decade
-20dB/decade 1
fp =
2π LC
π 1
fz =
π/2 2π Resr C
fp fz
ESR control stability

• high esr ensure stability but increase the ripple of the
output voltage (∆Vout ≈ Resr·∆IL)
211
Boost Converter
Vdd
IL L
D
Iload
Vp
Vout
Regulating
loop C
Reference
212
Boost Converter
Transient expired and switch closed
d IL
Vdd = L ⋅
Vdd dt
1
IL = ∫ Vdd dt
IL L L
Vp
D
Iload
Vp
t
Vout IL
C
t
ton
213
Boost Converter
Transient expired and switch open
d IL
Vdd − 0.6 − Vout = L ⋅
dt
Vdd
IL = ∫ (Vdd − 0.6 − Vout )dt
1
L
IL L
Vp
D
Iload
Vp
t
Vout IL
C
t
ton toff 214
Boost Converter
Vp
ton
D= = duty cycle
t
ton + toff
IL D ∈ (0,1)
Vdd dt + ∫ (Vdd − 0.6 − Vout )dt = 0

1 1
∫
L ton L toff
ton + toff 1
Vout = ⋅ Vdd − 0.6 = ⋅ Vdd − 0.6
toff 1− D
215
Linear vs. Switching Regulators
• Linear Regulators • Switching Regulators

– Simple ☺ – Step-up and step-down ☺
– Good performances ☺ – High power efficiency ☺
– Only step-down – High noise
– Low power efficiency – Very complex
216
Power Efficiency
LDO
VREF Vdd
-
Pldo ≈ VDS ⋅ I L = (Vdd − Vout ) ⋅ I L
+ Vout Pload Pload
efficiency = = =
R1 Pdd Pload + Pldo
VFB Vout ⋅ I L Vout
= =
CL Vout ⋅ I L + (Vdd − Vout ) ⋅ I L Vdd
R2
217
Power Efficiency
BUCK Converter
• The load current flows through the
two MOS transistors but since they
works as switches, they VDS is very
low, then they dissipates a very low
L Vout power thus achieving a very high
efficiency
• To have low VDS it is necessay to
C make the MOS very big (for high
load current, e.g., 1A, discrete
Resr
devices are used) so it is necessary
to consider the power lost by the
MOS drivers
218
Power Efficiency
BUCK Converter
100
90
80
70
efficiency %
60
50
40
30
20
10
0
0 100 200 300 400 500 600 700 800 900 1000 1100 1200
ILoad mA
219

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CMOS GATES

Design abstraction levels in digital

• The switching threshold, VM, is defined as the point where

• Best value is VM = VDD / 2. This allow to have about same

β ⋅ (VDD − VTH ) ⋅ VOL = (VDD − VOL ) R , β = µ ⋅ COX ⋅ W L

• VM: Vin = Vout ⇒ Vgs = Vds ⇒ NMOS saturated

For high input there is static power dissipation

VOL is not zero and it depends from

VGS2 = VDS2 ⇒ M2 always saturated

Vin = 0 ⇒ ID = 0 ⇒ Vout = VDD – VTH

M2 is always satured VOH = VDD -VTH

• VM: Vin = Vout ⇒ M1 saturated

For high input there is static power dissipation

VOH = VDD – VTH ⇒ it depends from MOS technology

VOL is not zero and it depends from transistor sizing

Solution: the load must be controlled by the input

Pull-up network (PUN) and pull-down network (PDN)

D 0 → VDD S 0 → VDD - VTn

PDN VDD → 0 VDD → |VTp|

VOH = VDD VOL = 0 independently from device size

For VTHn = |VTHp|, µn = 3·µp, Wp = 3·Wn ⇒ VM = VDD / 2 !!!!

• To easily estimate the noise margin a

• High gain g means high noise margin

• For g = ∞ and VM = VDD / 2, NMH = NML = VDD / 2

• Good ⇔ Fast ⇔ Best

• Bad ⇔ Slow ⇔ Worst

• This observation suggests that getting CL as small as possible

• When cascading two or more CMOS inverter, CL depend from

50% signal slopes

Vin 1. NMOS off

3. NMOS linear region

– Neglect the gate-to-source caps of M3 and M4

VDD • The closed NMOS transistor can

VDD t pHL = ln(2) ⋅ Reqn ⋅ C L ≈ 0.69 ⋅ Reqn ⋅ C L

Rn CL • ln(2) derives from tp definition (Vout from Vdd

Vin = V DD • Reqn, Reqp = ?

• However Ron is nonlinear, so use instead the average value

• Run is the equivalent resistance of a squared (W = L) nmos

VDD • The closed NMOS transistor can

tpHL = f(In, CL)

• Tun is the equivalent propagation of a squared (W = L) nmos

The two delay calculation approach give

3.5 B of 1.6 to 1.9 gives

5 delay and increase the

• CMOS inverter with its almost ideal VTC — symmetrical

Each time the capacitor CL gets

Gate is switched on and off

INDEPENDENT FROM THE PMOS AND NMOS SIZES

Minimize the Dynamic Dissipation

• Reduce load capacitances

• Reduce the switching activity (i.e., f0→1)

Only the last gate has high

• Ipeak is determined by the saturation current of the devices and is hence

Minimize the Direct-

PUN and PDN are dual logic networks

NMOS Transistors pass a “strong” 0 but a “weak” 1

PMOS Transistors pass a “strong” 1 but a “weak” 0 73

• PUN is the DUAL of PDN (can be shown by using

• The basic gates are inverting

(a) pull-down network (b) Deriving the pull-up network A

(c) complete gate

M2 = W / L They can drive the same amount of current