RADIOBEACON TRANSMITTER ND500II-x1x-x2x (125 WATTS) DOUBLE SIDEBAND NO VOICE SECTION 2 THEORY OF OPERATION GENERAL 1.

. The theory of operation for the subject transmitter is presented in this section. The information is presented in detail using the electrical schematics as a reference. TRANSMITTER DESCRIPTION 2. The ND500II-x1x-x2x double sideband (no voice) radiobeacon transmitter operates in the LF/MF band ( 190 kHz to 535 kHz) at 125 watts maximum carrier power. It automatically transmits specific beacon identification signals at preselected repetition rates. Special codes may also be transmitted when commanded from an external source. Provision is made for local or remote operation of the transmitter as well as antenna fine tuning through controls on the transmitters front panel. Emission is continuous carrier (NON mode) and beacon keyed identification tone ( A2A mode). All low level adjustment to pwb/assemblies are accessible from the top of the transmitter with the top cover removed. a. POWER SUPPLY(A1): The power supply provides +50vdc (B+), an unregulated +24vdc, a regulated +15vdc and can operated from either an ac or dc voltage source (battery etc). Monitoring circuits detect low levels on the ac power source or B+ voltage line and automatically switch to the dc supply (battery) and/or inhibit the + 24 and +15dc voltages. Status/alarm lamps, locate on the transmitters front panel, will turn on indicating the power supply is operating from either a dc or ac power source. An inhibit (ground) control signal from monitor pwb A5, when applied (dependent on the sitting of MONITOR switch S5), will result in the low dc voltages being inhibited and will shut down the transmitter.

 AC POWER SOURCE OPERATION: With power switch S3 set to ON, ac power (115 or 230 volts ac) will be applied through the contacts of switch S3 and AC POWER fuse F2, through connecter J1-1/2 and passed to the primary taps of the transformer T1. The secondary windings of transformer T1 provide tap selection to compensate for a low or high ac power source, tap selection is determined during installation (see selection 3). Under normal operating conditions, a nominal 57 volts rms is applied through full-wave rectifier U1, passed across choke inductor L1 and applied to terminal 1 on current shunt resistor R2. The output on terminals 2(+) and 3(-) of resistor R2, a dc voltage representing the dc current of the transmitter, is passed to connector J1-10/11 and can be monitored on TEST meter M1 when TEST switch S6 is set to DC CURRENT. The B+ voltage on terminal 4 of resistor R2 is applied diode CR3. MOSFET Q1 and passed through connector J1-6 for distribution throughout the transmitter. Power MOSFET transistor Q1 and its associated components form a limiting circuit which prevents the B+ voltage from exceeding 60vdc during no load conditions (i.e. no output power). When the breakdown voltage (56vdc) of zener diode CR3 is exceeded by the B+ voltage, a positive voltage will be developed at the junction of resistor R3/ zener diode CR3 and applied to the gate of MOSFET Q1, Q1 will be forward biased and turn on. Resistor R4 will be connected across the B+ voltage from exceeding 60vdc. UNREGULATE +24 VDC: The unregulated +24vdc circuit consists of MOFET transistor Q2, zener diode CR4 and associated components. Under normal operating conditions, the B+ vdc (fused) input on connecter J1-13 is applied thru resistor R5 to the drain of MOSFET Q2 and thru resistors A1R3/R11 to connector A1J1-8. A nominal 27vdc on connector A1J1-8 is passed to the gate of MOSFET Q2, Q2 will be gate on. +24vdc will be developed on the source of MOSFET Q2 and passed to the input of the 15 volt regulator circuit and to connector J1-7 for distribution throughout the transmitter. Zener diode CR4 ensures the gate of MOSFET Q2 is held at a constant 15vdc. Loss of unregulated +24vdc will result in loss of the regulated +15vdc. The transmitter will shut down.

 +15 Volt Dc Regulator: The +15 volt dc regulator consists of +15 volt dc regulator device U2, thyristor Q3 and their associated components. Normally, +24vdc will be passed through power MOSFET transistor Q2 and applied to regulator U2. The regulated +15 volt dc output of U2is passed across zener diode CR5, smoothing capacitor C2 and passed to connector J1-8/9 for distribution throughout the transmitter. Zener diode CR5 ensures the output of the regulator J2 does not exceeds 16.0vdc. If the +15 volt dc regulated output of U2axceeds 16.0vdc. Zener diode CR5 will be forward biased and turn on. A positive voltage will be applied to the gate of thyristor Q3. Thyristor Q3 will be gated on and clamp the +24vdc to ground. Fuse F3 on the B+ vdc (fused) line will blow. The transmitter will shut down. Dc Power Source (Battery): The dc power source (battery) circuit consists of relays K1/K2, zener diode CR6 (A1CR5 on NAB6 variations) and their associated components. Under normal operating conditions, relay K1 will be energized, relay K2 will be de-energized and the battery 48vdc input on J1-3(+) will be inhibited. If the ac power source falls below the required limits, protection circuits, within the ac monitoring pwb A1A1, will cause relay K1 to de-energized. The battery 48vdc input on J1-3(+) will be applied through the contacts of relay K1, resistor R1 and passed to shunt resistor R2. Storage capacitor C1 will begin to charge, through resistor R1, towards the dc level of the battery. When the voltage on storage capacitor C1 exceeds 20vdc, zener diode CR6 (A1CR5) will be forward biased through resistor A1R7/R8 energizing relay K2. When relay K2 energizes, resistor R1 will be removed from the circuit and storage capacitor C1 will continue to charge directly to the dc power source (battery). The B+ voltage from the dc power source is applied through resistor R2 and connector J1-6 for distribution throughout the transmitter. When relay K1 de-energizes, the ground on battery status connector on J115 is removed. Adc voltage produced through voltage divider resistors A1R15/A1R16 is passed through connector A1J1-10, battery status connector J1-15 and applied to the battery alarm lamp on the front panel. The lamp will turn on.

 Ac Monitoring: The ac monitoring (ac power source) circuit consists of transistor AQ2, AQ4, power MOSFET transistor A1Q5, relay K1 and their associated omponents. Under normal operating conditions, transistor A1Q2 and power MOSFET transistor A1Q5will be forward biased and turn on. Relay K1 will be energizedand the battery 48vdc input on connector J1-3(+) will be inhibited. A dc voltage developed through resistor A1R13/A1R14 will be passed through connectors A1J1-5, J1-16 and applied to an ac power status lamp on the front panel. The lamp will be turn on. If the ac power falls below the desired limits, the B+ voltage developed across full-wave rectifier diodes A1CR1/A1CR2 and voltage divider resistors A1R1/A1R2 will be insufficient to overcome the breakdown threshold of zener diode A1CR4. Transistor A1Q2 will be reversed biased and the turn off. Transistor A1Q4 will be forward biased and turn on. Resistor A1R12 will be grounded through transistor A1Q4 and power MOSFET transistor A1Q5 will be reversed biased and turn off. Relay K1 will de-energize and the ac battery 48vdc input on connector J1-3(+) will no longer be inhibited. The dc voltage on ac power status connector J1-16 will be removed and the ac power status lamp on the front panel will turn off. The transmitter will automatically switch over to the dc power source. The transmitter will automatically switch black to the ac power source when it returns to normal. B+ Monitoring/inhibit: The B+ monitoring/inhibit circuit is comprised of transistors A1Q1/A1Q3, power MOSFET transistor Q2 and their associated components. Under normal operating conditions, the B+ vdc (fused) input on connector J1-13 will exceed the breakdown threshold of diode A1CR3. Transistor A1Q1 will be forward biased and turn. Transistor A1Q3 will be reversed biased and turned off. A positive voltage (approximately 27vdc) will be applied through connector A1J1-8 and passed to the gate of power MOSFET transistor Q2, Q2 will be forward biased and turned on. +24vdc will also be passed to the input of +15 volt dc regulator U2-1. Zener diode CR4 limits the gate drive to MOSFET Q2 at 15vdc. If the B+ vdc (fused) input on connector J1-13 falls below the desired level, zener diode A1CR3 will be reversed biased and turn off. Transistor A1Q1

will be reversed biased and turn off. Transistor A1Q3 will be forward biased thru resistor A1R9 and turn on. Resistor A1R11 will be connected to ground thru transistor A1Q3 and apply o ground to the gate of MOSFET Q2, Q2 will be gate off. The +24vdc will be removed from the source of MOSFET Q2 and from the input to the +15vdc will be regulator circuit. The +24 and +15vdc will be inhibited on connecters J1-7 and J1-8/9. The transmitter will shut down. b. OSCILLATOR/RF DRIVE PWB (A2) The oscillator/rf drive circuits generate an rf drive signal at the assigned carrier frequency for the subject transmitter. Internal links can be configured to accommodate either an internally or an externally (frequency synthesizer) generated rf carrier source. Carrier Oscillator: The carrier oscillator circuit is comprised of transistor Q1/Q2, crystal Y1 and their associated components. The oscillator is a modified crystal controlled Pierce circuit with a frequency range of 4,8 or 16 times the carrier frequency and is controlled by carrier oscillator crystal Y1. Carrier frequency trimmer capacitor C5 is used to fine tune the oscillator frequency. Transistor Q2 and its associated components from an isolation amplifier for the carrier oscillator. Test point TP1 provides a convenient monitoring point for the carrier oscillators output. Frequency Divider: The frequency divider circuit is comprised of frequency divider device U1, divide-by-links (4, 8 or 16) and associated components. Frequency divider U1 divides the carrier oscillator frequency by the required factor (4,8 or 16) to achieve the correct operating frequency. The appropriate divide-by-links is connected during installation (see section 3) and is dependent on the carrier oscillators frequency. Balance/RF Drive: The balance/rf drive circuit is comprised of transistors Q3/Q4, a class D push-pull amplifier formed by power MOSFET transistor Q5/Q6 and their associated components. A +15vdc square wave, at the assigned carrier frequency, is applied to the bases of transistor Q3/Q4. When the square wave is +15vdc, transistor Q3 will be forward biased (turned on) and transistor Q4 will be reversed biased (turned off). Capacitor C9 will begin to

charge towards +15vdc. When the square wave is zero volts, transistor Q3 will be reversed biased (turned off) and transistor Q4 will be forward biased (turned on). Capacitor C9 will begin to discharge towards ground. The resultant current flow on the primary of transformer T1 will be a 15 volt square wave, at the carrier frequency, with sharp leading and trailing edges. The secondary of transformer T1 contains two identical windings. Each winding is connected across the gate and source of a power MOSFET (Q5/Q6). The voltage applied to the gate of MOSFET Q5 will be 180 degress out of phase with the voltage being applied to MOSFET Q6. When the gate of power MOSFET Q5 is positive, the gate of MOSFET Q6 will be negative. MOSFET Q5 will be gated on and MOSFET Q6 will be gated off. The B+ vdc on connector J1-3will be applied through inductor L4 and passed through the source/drain junction of power MOSFET Q5. During the next half cycle, the gate of MOSFET Q5 will be negative and the gate of MOSFET Q6 will be positive. MOSFET Q5 will be gate off and MOSFET Q6 will be gated on. A ground will be applied through the drain/source junction of power MOSFET Q6. The signal at the junction of the drain/source of MOSFET Q5/Q6 will be square wave switching at the carrier frequency between ground and the B+ voltage level. The peak detected output at the junction of diode CR3 and capacitor C13 represents the rf drive level being applied to the power amplifier/modulator assembly A6. Test point TP4 provides a convenient monitoring point of the rf drive output of the assembly. c. KEYER PWB(A3): The keyer is a self-contained logic block the automatically generates keyed audio tones signals which are used to modulate the transmitter. This is accomplished by means of a 64-bit code cycle or frame which is eight seconds long. The second identification signal is programmed in the keyer and may contain up to three characters (letters or numbers) followed by either a long space or a long filler dash to the end of the code cycle or frame. The length of a dot is fixed at 125 milliseconds (1 bit) while the length of the dash is fixed at 375 milliseconds (3 bit). A tone oscillator circuit capable of generating a 400 or 1020 Hz tone is also contained on the keyer together with an associated keying gate. In addition to the actual beacon

identification letters or numbers, two separate minor variations to the code may be selected via external controls. These coding variations are referred to as standby 1 and standby 2 and may be used to transmit information such as changeover from the selected main to the standby transmitter or changeover of the power source from, for instance ac supply to the (optional) battery backup or diesel backup. The keyer also has the capability to generate whole frames of tones or space to meet particular customer coding requirements. If the transmitter is in the MCW operating mode, a keying override signal is applied to override the coded keying and actuate a continuous tone as the keyed tone output. The timing oscillator consisting of operational amplifier U2A and associated components is a free running clock producing a 64-pulse per second signal. The output of the timing oscillator may be monitored at test point TP1. The 2-stage binary counter circuit consist of counter U3 and its associated components. It 12 outputs, labeled Q1 through Q12, divide the timing oscillator signal by a factor of two to 4096, depending on which output is selected. Each output is a +15 volt square wave at the divided repetition rate (frequency). The Q5 thru Q8 outputs of 12-stage binary counter U3 are connected to the binary coded control inputs of the code multiplexers U4 and U5. The control inputs determine (as a binary number clocking at 2.0 Hz) which multiplexer gate of 16 in each multiplexer is to be switched on at a particular period of time. When a multiplexer gate is switched on, as determined by the state of the control input, the common input (pin 1) is shorted to the required output. Q9 output of 12-stage binary counter U3 and U2B determines which multiplexer, U4 or U5, will be enabled first. This, together with timing pulses from Q5 thru Q8 outputs of binary counter U3, allows only one gate out of a possible 32 gates to be on (+ 15.0 vdc) at a particular instant. The cycle starts at U4 gate '0' and ends at U5 gate '15', 32 steps and takes approximately eight seconds to complete, at which time it recycles and starts again. the outputs of multiplexers U4 and U5 are connected to code bus terminal boards TB 1 and TB2 by straps programming the spaces and dashes for the code. The code bus which consists of terminal blocks TB 1 and TB2 is where the

actual beacon identification code is programmed into the keyer. If there are no connections made on the code bus, the keyer output will be a continuous series of dots. Q4 output of the 12-stage binary counter which is a square wave at 4 Hz, turns keying output gate U1D on and off through resistor R15 and diode CR7. If there is a connection made from the code multiplexer to the dash portion of the code bus, program dash gate U1A will turn on, + 15.0 vdc will be applied through resistor R12 at the appropriate time which will turn keyer output gate U1D on through diode CR7. Keying output gate U1D will be on only as long as any code multiplexer's output gate which is connected to the dash bus, is on corresponding to the time for two bits at each gate output connected. If there is a connection made from the code multiplexer to the SPACE 1 portion of the code bus, program space, gate U1B will turn on at the appropriate time which will turn keyer output gate U1D off through gate U1B and diode CR7. When programming the keyer, if a space is required during an intetval, it is connected to the space bus. If a dot is required during an intetval, there is no connection needed since Q4 output of binary counter U3 will provide continuous dots. The X0, X1 and X2 outputs of code multiplexer U4 are always connected to the space bus; i.e. pre-programmed to ensure that a space period appears before the start of the beacon identification code. The X3 output of code multiplexer U4 is never connected because the first element of any letter or number of the beacon identification code is always a mark whether the character starts with a dot or a dash. The Q10 thru Q12 outputs of the 12-stage binary counter U3 are connected to the control inputs of frame selector U6. By connecting the output of U6 (XO to X7) to the SPACE or MARK terminal of the frame bus, the frame content can be selected. If a continuous space is required during the whole of a particular frame, link the appropriate output of U6 to the space terminal of the frame bus. If a continuous mark is required during the whole of a particular frame, link the appropriate output of U6 to the mark terminal of the frame bus. The outputs of frame selector U6 begin cycling at output XO and continue in sequence to output X7. Each output corresponds to an individual 8.0 second

frame which may consist of a tone (MARK), a SPACE, or the programmed beacon identification code. When a mark is selected during a frame, gate U1D is turned on for the entire frame through diode CR8 which creates a tone period. When a space is selected during a frame, gate U1B is turned on which keys gate U1D off for an entire frame, which creates a space period. Operational amplifiers U7A/U7B and their associated components form a stable, free running rf oscillator. Solder links 'B' and 'C' in the feedback network allow frequencies of 400 Hz or 1020 Hz to be used for the beacon tone (links 'B' and 'c' installed signifies a 1020 Hz tone; links 'B' and 'c' removed signifies a 400 Hz tone). Each keyer contains two standby code, capabilities (a total of four separate code variations, two for each side of the transmitter). A longer space period between the second and third characters of a three-character code and a blip before the start of the beacon identification code. The X15 output of code multiplexer U5 is connected to the SPACE 1 code bus through resistor R11 and diode CR4 so that a space is normally generated. When a ground is placed on J1-4, standby 2 and the count reaches gate X15 of U5, this count is inhibited which allows the output of the 12-stage binary counter U3 to turn on the keying output gate U1D through resistor R15 and diode CR 7 to provide an additional dot in the code. Gate U1B is only off for as long as the count is at X15 of U5. This creates the blip before the start of the code. When a ground is connected to J1-2, standby 1 and the SPACE 2 portion of the code bus in wired to the space period between the second and third letters of a three-letter code, the space between these two letters will increase. When the count reaches the appropriate point of the code (between the second and third letters), gate U1C will turn on which will place a ground on the anode of diode CR1 of the timing oscillator. This ground will cause the timing oscillator to slow down to one-third of its rate which will automatically increase the time between the second and third letters. Similarly, an increased space can be programmed between the first and second letters.

d. MODULATOR DIUVER PWB (A4) (See figure SD-5): The modulator driver circuits process the audio signal and convert the processed audio to a pulse-width modulation signal that contains the carrier level and audio information. Logic circuits monitor the level of the rf drive and the modulation pulse-width output and produce mod drive and rf drive alarm control signals which turn on associated alarm lamps located on the front panel when these thresholds are exceeded. Mod Enable Switch: The mod enable switch circuit is comprised of analog switches U1BIU1C, operational amplifier U6A, MOD% potentiometer R2 and their associated components. Under normal operating conditions the keyed tone (audio) on J1-6 is applied through capacitor C26, MOD% potentiometer R2, resistor R3 and passed to analog switch U1B-4. MOD"" potentiometer R2, adjusts the level of the audio input to the modulator driver pwb. With MOD switch S2 (see figure SD-1), set to on, a + 15 volt dc mod enable control signal will be applied through connector J1-5, resistor R43 and passed to switches U1B-5 and U1C-6. The two analog switches will turn on. The audio information is applied through the two analog switches and applied to the inverting gate of operational amplifier U6A-2. A preset bias level, established through voltage divider resistors R5 thru R7 is applied to the non-inverting input of U6A-3. This bias level determines the maximum carrier power output of the transmitter. The output of operational amplifier U6A-1 is applied through resistor R8 and passed to dynamic analog divider U3. The output of U6A-1 can be monitored at test point TPl. + 15 to -15 Vdc Converter: The + 15 vdc to -15 vdc converter circuit is comprised of inverter gates U2A thru U2F, transistors Q8/Q9 and their associated components. Inverter gates U2A, U2B, resistors R41/42 and capacitor C3 form an oscillator that produces a + 15 volt dc square wave at a frequency of approximately 36 kHz. The output of U2B is applied to parallel connected inverters U2C thru U2F which provide buffering for the 36 kHz input from U2B and produce a low impedance, high current drive for transistors Q8/Q9. Balance drive transistors Q8/Q9 will be gated on and off at the 36 kHz switching frequency. The output at the emitter junction of transistors Q8/Q9 is applied through capacitor C6 and across diode CR4. Diode CR4 allows only the negative-going portion of the square wave to

remain. Diode CR5 and capacitor C25 form a peak detector and smoothing circuit for the unloaded -15 vdc. Test point TP5 provides ,a convenient location to monitor the -15 vdc (approximately -12.0 vdc will be measured on TP5 due to the load presented by the modulator driver circuits). PWM Square Wave Generator: The pulse-width modulator square wave generator consists of programmable timer U4 and its associated components. The oscillator frequency is adjusted to a nominal frequency of 70 kHz by FREQ variable capacitor C1l. The output of the generator will be a 15 volt square wave at the oscillator frequency and will be applied to the ramp integrator circuit. PWM Ramp Integrator: The PWM ramp integrator circuit consists of operational amplifier U7 A plus its associated components. The 15 volt square wave from the PWM square wave generator is applied to the inverting input of U7 A Capacitor C16 and resistor R32 which are located in the feedback circuit of U7 A, result in a linear sawtooth waveform being produced at the output of U7 A Test point TP3 provides a convenient location to measure the waveform. RAMP ADJUST potentiometer R26 is adjusted to set the negative going peaks of the linear waveform to a dc reference potential of zero volts. Variable Pulse-Width Generator: The variable pulse-width generator circuit is a differential amplifier that compares the linear sawtooth waveform from the ramp integrator with the audio signal and produces a nominal 70 kHz rectangular waveform as the pulse-width modulation signal. The circuit comprises operational amplifier U7B, transistors Q4, Q5 and their associated components. They are configured to form an emitter coupled differential amplifier. A portion of the audio signal is applied to the non-inverting input of U7B from the wiper of OIP POWER potentiometer R3l. Unity gain buffer amplifier U7B applies this voltage to the base of Q5. The linear sawtooth waveform from U7 A is applied to the base of Q4. Refer to figure 2-1 for a simplified schematic of the differential amplifier. For initial explanation purposes, assume the audio signal is a dc reference voltage that does not contain the audio component. When the linear sawtooth waveform voltage is more negative than the de reference voltage, Q4 will be forwarded biased and Q5 will be reverse biased. When the linear

sawtooth waveform voltage is less negative than the dc reference voltage, Q5 will be forward biased and Q4 will be reverse biased. The output at the collector of Q5 will be approximately zero vdc when Q4 is forward biased and + 15 vdc when it is reverse biased. The forward/reverse bias ratio of Q5 is determined by the level of the audio signal. When audio is superimposed on the dc reference voltage, the audio input applied to the base of Q5 will go more or less negative at the audio rate. The magnitude of the change will be determined by the amplitude of the audio component. When it is more negative, Q5 will be reverse biased for a longer portion of the linear sawtooth waveform period. When it is less negative, Q5 will be reverse biased for a shorter portion of the linear sawtooth waveform period. When a audio component is present, the resulting pulsewidth modulated output at the collector of Q5 is a varying width rectangular waveform at the repetition rate of the square wave generator (nominally 70 kHz). This waveform can be monitored at test point TP4. Linear Attenuator: . The linear attenuator circuit consists of operational amplifier U5A and unity gain amplifier U5B, transistors Q1/ Q2 and their associated components. Operational amplifier U5A and transistor Q1 form a diode to ground circuit which results in a bias voltage of approximately 0.6 vdc being applied to the emitter of transistor Q2. Normally the control voltage applied to the non-inverting input of U5B from VSWR cutback on J14 is zero volts. The zero volt control signal is applied thru unity gain amplifier U5B and passed to the base of transistor Q2. Transistor Q2 will be reversed biased and turn off. The linear attenuator circuit will present a high impedance between the audio signal and ground. When a VSWR cutback positive control signal is applied to the non-inverting input of U5B, the output of U5B will be positive. Transistor Q2 will be forward biased and turn on. The impedance of the linear attenuator circuit will begin to decrease in proportion to the current flow through transistor Q2. The attenuation factor will vary in proportion to the VSWR cutback control signal being applied from J1-4. B+ Variation Compensation: The B+ variation compensation circuit is comprised of monolithic analog multiplier U3 (connected as a dynamic

analog divider), operational amplifier U6B and associated components. The compensation circuit ensures the modulation depth and output power remain constant if variations on the B+ line occur and also provides a means of adjusting the output power through the increase/decrease of the remote power trim voltage ( + 15 vdc maximum). The keyed tone (audio), B+ voltage and power trim inputs are -applied to analog divider U3. -The output of U3 is passed to the inverting gate of operational amplifier U6B. The resultant output on U6B-7 can be monitored at test point TP2. Any increase or decrease of the B + voltage on U3-5 will result in a proportional increase or decrease on the output of operational amplifier U6B-7. The same results are applicable with an increase or decrease of the power trim input on U3-1 as those mentioned for the B+ voltage. Low RF Drive Cutback: The low rf drive cutback circuit is comprised of operational amplifier U9A, inverter/buffers U8A1U8B, transistor Q3 and their associated components. A dc voltage, proportional to the rf drive level, is applied through connector J1-1 and passed to the non-inverting input of operational amplifier U9A-3. The bias level on the inverting input of U9A-2 is developed through voltage divider resistors R33/R47/R34. During initial turn on, the rf drive level being applied to U9A-3, is insufficient to overcome the bias level on U9A-2. Transistor Q3 will be forward biased and turn on. The non-inverting input to U9A-3 will be at ground level and U9A's output will be low. The low output from U9A will be applied through inverter U8A-3/2 and provide a high through diode CR3 to input of inverter U8A-7 which will inhibit the mod drive. The high output on U8A-2 will also be applied through inverter U8B-5/4 and passed to rf drive alarm connector J2-5. The low alarm control signal will be applied to the RF DRIVE ALARM lamp on the front panel. The rf drive alarm lamp will turn on. After a nominal five seconds, the if drive level input on connector J1-1 will exceed the bias level on operational amplifier U9A-2, the output of U9A-1 will go high, transistor Q3 will be reversed biased and turn off. The output of inverter U8B-2 will be low and the high being applied through diode CR3 to U8A-7 will go low.

The mod drive will no longer be inhibited. The output of U8B-4 will go high and the rf drive alarm lamp will turn off. Balanced Drive: The balance drive circuit is comprised of buffer amplifier U8A, transistors Q6/Q7 and their associated components. The balance drive forms a switching circuit that is driven by the variable pulse-width modulation signal from the variable pulse-width generator circuit. The pulse-width modulated signal is inverted by buffer amplifier U8A Transistors Q6/Q7 will be gated on and off at the PWM switching frequency. The switching action of transistors Q6/Q7 ensures the leading and trailing edges of the rectangular waveform are sharp. The mod drive output on connector 12-8 is a low impedance pulse-width modulated signal switching between + 15 vdc and ground.

Pulse-Width Fault Detector: The pulse-width fault detector circuit is comprised of operational amplifier U9B, inverter U8D and relay K1 plus their associated components. The subject circuit monitors the pulse-width modulation signal for the presence of + 15 volt dc pulses. A two-pole low pass filter network, comprising resistors R37!R38 and capacitors C21/C22, continuously monitors the mod drive output for the presence of positive voltage pulses. When they are present, capacitor C21 will charge to an average value, dependent on the on/off ratio. The voltage on capacitor C22 which is applied to the non-inverting input of U9B, will not exceed the reference threshold voltage applied to the non-inverting input of U.9B from

the junction of resistors R39/R40. The output of U9B will be a low impedance to ground, resulting in the output of U8D being + 15 vdc. A mod drive alarm signal will not be applied to J2-6. If the voltage on capacitor C22 exceeds the reference threshold voltage applied to the inverting input of U9B, the output of U9B will be a + 15 vdc. Relay K1 will energize and remove the mod drive output on J2-6. The output of U8D will be zero volts dc. A zero potential mod drive alarm signal will be applied through J2-6 to MOD DRIVE ALARM lamp DS3 on the transmitter's front panel. The lamp will turn on. e. POWER AMPLIFIER/MODULATOR (A6) (See figure SD-8): The power amplifier/modulator is comprised of a modulator which provides high level amplitude modulation of the carrier signal plus an rf power amplifier. The rf power amplifier provides 125 watts of carrier power at 100% amplitude modulation over a frequency range of 190 to 535 kHz. Modulator: The modulator circuit is comprised of power MOSFET transistor Q1 (connected as an electronic switch) and its associated components. Under normal operating conditions, the mod drive input, (zero to + 15 vdc pulses), on connector 11 is applied through inductor L3 to the gate of transistor Q1. When the gate of Q1 is positive, Q1 will be forward biased (turned on), current will flow through Q1, through a low-pass filter circuit, formed by inductors L1/L2 and capacitors C1 through C3 to the B+ line. When the gate of Q1 is negative, Q1 will be reverse biased (turned off). The low-pass filter circuit removes the 70 kHz switching frequency but passes the audio information. Transistor Q3 will be switching on and off with a pulse duration corresponding to the carrier level plus tone modulation (MCW). The B+ to modulator drive source voltage will also be varying at this rate and will effectively control the output of the power amplifier. If operating in the CW mode, the B+ to modulator drive source voltage will not vary and the output of the power amplifier will remain constant. Power Amplifier: The power amplifier circuit is comprised of power MOSFET transistors Q2 through Q5, 2:1 step-down transformer T1, output transformer T2 and their associated components. The subject amplifier operates as a class 'D' (switched mode) amplifier. Under normal operating conditions, a 48 volt peak-to-peak rf drive input on connector J2 is applied

through the primary windings of transformer T1 to four identical secondary windings. Each secondary winding is connected between the gate and source leads of its respective MOSFET. The power MOSFETs are connected in a series push-pull configuration with the phasing of their inputs determining which pair (Q2/Q5 or Q3/Q4) are turned on. With power . MOSFET transistors Q2/Q5 forward biased (turned on) and Q3/Q4 reversed biased (turned off), current will flow from the B+ line through the source/drain junction of Q2 and the primary of transformer TI, through the source drain of Q5 to the less positive voltage at the modulation drive source. During the next half cycle, transistors Q2/Q5 will be reversed biased (turned off) and Q3/Q4 will be forward biased (turned on). Current will flow from the B+ line through the source/drain junction of Q4 and the primary of transformer TI (in the reverse direction), through the source drain junction of Q3 to the less positive voltage at the modulation drive source. The rf output on connector 13 will be a square wave at the rf carrier frequency level. The maximum and minimum undistorted rf. carrier output the power amplifier can produce is dictated by the magnitude of the Bmodulator voltage. f. MONITOR PWB (A5) (See figures SD-6 and SD-7): The monitor pwb monitors the critical parameters of the subject transmitter and produces local control signals which turn on lamps on the transmitter's front panel when these parameters are not met or a status condition of the transmitter is to be known. Potentiometers provide adjustments for establishing the carrier/modulation thresholds, shutdown time delay (seconds) and calibration of the forward/reflected power metering circuits. The assembly produces an additional unmetered + 15 vdc [+ 15 vdc (A1)], for internal use. Remote outputs include battery status (ac or dc power source), audio monitoring, shutdown condition (transmitter has shutdown) and SWR condition (transmitter's rf output is being cutback). Forward Power/Fwd Pwr Cal: The forward power monitoring and calibration circuit is comprised of buffer amplifiers U1NU1D, FWD PWR CAL potentiometer R21 and their associated components. The fwd pwr input on connector J1-3, a dc voltage representing the forward power of the transmitter with a superimposed ac voltage proportional to the

modulation depth, is applied across smoothing capacitor C19, through loading resistors R2/R9 and applied to the non-inverting gate of U1A-3. Capacitor C3 filters the modulation component while charging to a dc level that is representative of the carrier level. The output on U1A-1 is applied through resistor R17 and FWD PWR CAL potentiometer R21 and passed through connector J1-4 to TEST meter M1 on the front panel. FWD PWR CAL potentiometer R21 provides a calibration adjustment for the forward power indication on TEST meter M1 (refer to special calibration procedures in section 5). The output on U1A-1 is also applied to the non-inverting input of U1D and passed to fwd pwr (remote) connector J1-5. The forward power (remote) output on J1-5 is not available, in this instance, for external use. Audio Monitoring: The audio monitoring circuit is comprised of buffer amplifiers U1B/U2B/U2A and their associated components. The fwd pwr input on connector J1-3, a dc voltage representing the forward power of the transmitter with a superimposed ac voltage proportional to the modulation depth, is applied through loading resistor R2 and applied to the non-inverting gate of buffer amplifier U1B. The detected modulated audio signal is applied to the non-inverting input of audio amplifier U2B. Resistors R28/R29/R30 and capacitor C8 set the gain of U2B. The output on U2B-7 is coupled through capacitor C9 and passed to audio connector J1-6 and is used to drive speaker LS1 on the transmitter's front panel. Buffer amplifier U2A-1 provides a filtered audio output, on audio remote connector J1-8, for external use. Monitor's +15 Vdc (A) Supply: The B+ voltage is applied through connector 13-1, resistors R1/R4 and across 15 volt zener diode CR3. The three components provide the + 15 vdc for the monitor circuits. Low Carrier Level Detector: The low carrier level detector circuit is comprised of comparator U3C,CARRIER THRESH potentiometer RlO and their associated components. Under normal operating conditions, a portion of the forward power from the output buffer UlB-7, is applied to the wiper of potentiometer RlO. Potentiometer RIO is normally set for the desired minimum carrier level (normally to detect a -3.0 dB drop on the intended carrier level). The dc voltage on the wiper of potentiometer

RIO is applied through resistor R18, across capacitor C5 and passed to non-inverting input of U3C-l1. Capacitor C5 filters out the modulation component of the rf carrier and charges to the mean dc level which is representative of the f carrier level. The reference voltage on U3C-ll represents the carner threshold level which is compared to the voltage level, established by resistors R22/R23, on the inverting gate of U3C-1O. The output on U3C-13 will be a high impedance to ground, the high's potential will be applied to the base of transistor 06, transistor 06 will be forward biased and turn on. If the output on U3C-13 switches to a low impedance to ground, (drop of -3dB on the carrier level), the low potential will be applied to the base of transistor 06. Transistor 06 will be reversed biased and turn off. Low Modulation Depth Detector: The low modulation depth d~tector circuit consists of operational amplifier UlC, MOD THRESH potentiometer R8, a synchronous detector circuit comprised of transistor 01 and power MOSFET transistor 02,. comparator U3B and associated components. A sample of the forward power on J1-3 is applied thru the wiper of MOD THRESH potentiometer R8 and passed to the non-inverting input of UlC-lO. MOD THRESH potentiometer R8 is normally set for the desired minimum modulation level (normally to detect a -4.0 dB drop on the intended modulation depth). Power MOSFET 02 and transistor 01 will only detect signals that are in phase with the keyed tone input to transistor 01. Under normal operating conditions the ac output of UlC is applied to the inverting gate of U3B where it is compared to a bias voltage, established by resistors R24/R25, on the non-inverting gate of U3B. The output on U3B-2 is applied across a differentiating circuit consisting of resistor R33 and capacitor C7. The differentiating circuit produces a positive pulse, during each transition, which is applied to the base of transistor 06. THRESH lamp DSI will normally be flashing on and off at the keyed tone rate. When the positive pulses being applied to the base of transistor 04 are removed, 04 will be reversed biased and turned off. Transistor 05 will be

forward biased and turned on. THRESH lamp DSI will turn on. If Thresh lamp DSI remains turned on for a period longer than the shutdown time delay, the subject transmitter will shutdown (shutdown time delay is dependent on setting of DELAY potentiometer R41; adjustable between 20 and 80 seconds). Shutdown Control: The shutdown control circuit is comprised of operational amplifier U4B, DELAY potentiometer R4l, transistor 06 and their associated components. Under normal operating conditions, transistor Q6 will be switching on and off at the keyed tone rate (positive pulses from the differentiating circuit). When 06 turns on, capacitor ClO will discharge through 06 to ground and the voltage on the non-inverting gate of U4B-5 will be less positive than the voltage on the inverting gate of U4B-6. A low will appear on the output U4B-7 and shutdown alarm connector J 4-8. The SHUTDOWN ALARM lamp, on the front panel, will remain turned off. The low output on U4B-7 will also be applied to the base of transistor 07. Transistor 07 will be reversed biased and turned off. The inhibit control signal on connector J4-7 will be an open collector. If the positive pulse, from the low modulation detector circuit is not present, (loss of keying, -3dB drop on the carrier level or a decrease of 4.0 dB on the intended modulation depth) on the base of transistor 06 before the shutdown circuit's time delay has elapsed (between 20 and 80 seconds), transistor 06 will remain turned off. Capacitor ClO will begin charging thru resistor R45/R44 and DELAY potentiometer R41. When the voltage on the noninverting gate of U4B-5 exceeds the bias voltage on U4B-6, the output on U4B-7 will go high. The high output of U4B-7 is applied thru shutdown alarm connector J4-8 and passed to a shutdown alarm lamp on the front panel. The lamp will turn on. The high on the output on U4B-7 will also be applied thru resistor R50 to the base of transistor Q7. Q7 will be forward biased and turn on. A ground potential will be passed to inhibit connector 14-7 and passed to a low dc voltage inhibiting circuit within power supply assembly AI. The transmitter will shutdown. Overmodulation Detector: The overmodulation detector circuit is comprised of operational amplifier U5A, comparator U5B, OVERMOD CAL potentiometer R56, transistor Q9 and their associated components.

Under normal operating conditions, a dc voltage proportional to the carrier level with a superimposed ac voltage proportional to the modulating level is applied through rf current sample connector J2-1 and passed to a detector circuit consisting of diode CR8 and capacitor C12. The detected signal is passed across loading resistor R53 and a limiting circuit consisting of diode CR9 and resistor R54. The limiting circuit maintains the input to U5A's negative gate to + 15 vdc. Resistor R55 and OVERMOD CAL potentiometer R56 establish the reference threshold on the positive gate of U5A-3. The output on U5A-1 will be low, transistor Q9 will be reverse biased and turned off. The overmod alarm lamp will be turned off. If the voltage being applied to U5A-2 becomes more positive than the reference voltage at U5A-3, the output on U5A-1 will go high. Transistor Q9 will be forward biased and turn on. Capacitor C13 will discharge causing the input on U5B-6 to become more positive than the reference voltage on U5B-5. The output on U5B-7 will go high and be applied to the overmod alarm connector 12-3. The overmod-alarm lamp on the front panel will turn on. Reflected Power/Refl Pwr Cal: The reflected power monitoring and calibration circuit is comprised of buffer amplifiers U8NU8B, REFL PWR CAL potentiometer R80 and their associated components. Under normal operating conditions a dc voltage representing the reflected power of the transmitter is passed through reft pwr connector J1-1 and applied across capacitor C25, through load resistors R63/R66 and passed to the noninverting gate of U8B-6. Capacitor C25 will charge through resistor R63 to an average value representing the reflected power. The output on U8B-7 is applied through resistor R 76 and REFL PWR CAL potentiometer R80 and passed to reft pwr connector J2-7 for internal use. REFL PWR CAL potentiometer R80 provides adjustment during calibration for the reflected power indication being provided by TEST meter M1 on front panel. The output on U8B-7 is also applied through buffer U8A and passed to reft pwr (remote) connector 12-3 for external use. SWR Protection: The SWR protection circuit is comprised of operational amplifier U9B, inverter U7A, transistor Qll, comparator U9A and their

associated components. Under normal operating conditions (no reflected power) the output on U9B-7 will be low (ground) and the circuit will have no influence. If the voltage level representing the reflected power on U9B-5 becomes more positive than the reference voltage level (established by resistors R68/R70 and SWR THRESH potentiometer R69) on U9B-6, the output on U9B-7 will go high. The output voltage level on U9B-7 will depend on the dc level of the reflected power sample. Capacitor C17 shapes the transient response time providing a lower gain by connecting resistor R74 in parallel with resistor R 75 to protect against unwanted fluctuations. The output on U9B-7 is passed to SWR cutback connector 13-2 and applied to a linear attenuator circuit within the mod driver pwb. When the output on U9B-7 is high, the input to comparator U9A's non-inverting gate will be more positive than the reference voltage level (approximately 0.6 vdc established by resistor R79 and diode CRll), on U9A's inverting gate. The output on U9A-1 will go high. This output is passed to four separate circuits. One portion of U9A's output will be applied through resistor R82 and forward bias (turn on) transistor Q11. A ground control signal will be passed to the SWR alarm (remote) connector 13-3 for external use. The output on U9A-1 is also passed through inverter U7 A and passed to diode CR14. When U7A's output is low (SWR present), diode CR14 will be forward biased and turn on. A low (ground) control signal will be passed to SWR standby connector 13-5 and initiates a standby 2 keyed code indicating a SWR condition. The high control signal, representing a high SWR condition, on the output of U9A-1 will also be passed thru resistor R83 and passed to the SWR alarm lamp on the front panel. The lamp will turn on indicating a high SWR condition exists. A high output on U9A-1 will be applied to comparator U3D-9, U3D's output will go high, transistor 06 will be forward biased and turn on. The shutdown control circuit will be inhibited and the subject transmitter will not shutdown when a high SWR condition is present. Battery Control: The battery control circuit is comprised of buffer amplifier U6A, transistor OlO and their associated components. When the

subject transmitter's power source is being generated from an ac source, the input on battery status connector 13-7 will be low. A low will be applied through U6A to the base of transistor 010, causing it to be reversed biased and turned off. The battery status output on connector 13-8 will be an open collector. The battery-alarm lamp on the front panel will be turned off. If the ac power source fails, the battery status input on 13-7 will switch to a high. The output on U6A-1 will go high and transistor 010 will be forward biased and turn on. A ground control signal will be applied to battery status (remote) connector 13-8 for external use. A high battery status. control signal will be applied to the base of transistor 03 causing it to be forward biased and turn on. Transistor 03 and its associated components form a pulsing circuit which momentarily turns on transistor 06, through diode CR18, to reset the shutdown circuits when ac power is restored and the transmitter had been operating from a dc power source (battery). Mod% Control: The mod% control circuit consists of operational amplifiers U6B/C/D and their associated components. The input on if voltage sample connector J2-6, a dc voltage proportional to the intended carrier level is applied through the filtering circuit where the rf carrier frequency will be removed but the audio information will be passed. One output of U6D is applied to the non-inverting gate of U6C, a second output "is applied through resistor "R78 to 100% mod ref connector J2-4 and passed to a set 100% MOD potentiometer on the front paneL A peak detector circuit, comprising U6C, diode CR13, resistor R81 and capacitor C18, detects the peak output on U6D-14 and applies the dc signal through buffer U6B to mod % connector 13-6. When the test switch on the front panel is set to MOD-READ, the meter will be connected between the 100% mod ref line on connector J2-4 and the mod % on 13-6. For 100% adjustment on the test meter, the test switch on the front panel is set to MOD-REF, the output on U6B will be double the output of U6D to compensate for the return line through the meter from the output of U6D. Bypass Control: Under normal operating conditions the bypass input on J44 will be at ground potentiaL The bypass circuit will have no influence. If the ground potential is removed from J4-4, transistor 07 will remain off

regardless of the output from comparator U4A The shutdown circuit will be inhibited and the transmitter will remain operating. g. HARMONIC FILTER (A7) (see figure SD-9): The harmonic filter assembly is a passband filter which attenuates the harmonics on the square wave output from the modulator/power amplifier circuits. The subject filter has a flat response characteristic over the operating bandwidth. The band-pass is selected through external link connections to TB1 thru TB4 (refer to section 3 for details). Provision is made to automatically inhibit the rf output from the mainside of the transmitter and select the rf output from the standby-side (optional feature, for a dual transmitter only), in the event that the main-side of the transmitter fails. Current Probe: The current probe circuit consists of transformer T1 and its associated components. The if in (main Tx) input on connector 11 is applied across transformer T1 and passed through tapped inductor L1, frequency select capacitors A1C1 thru A1ClO and A2C1 thru A2ClO, across transformers TIm, applied through if out connector J2 and passed to the antenna system. A sample of the rf current is applied through transformer T1's secondary, resistors R1JR2 and through if current sample terminals 1 and 2 on TB5 for use within the overmodulation circuitry in the monitor pwb AS. Forward/Reflected Power Probe: The forward/reflected power probe circuit consists of transformers TIm and their associated components. Transformer TI senses the output voltage and transformer T3 and resistors A3R1/R2 sense the output current. When the output voltage and output current are in phase, the output on reft pwr terminal TB6-3 will be zero. The output on fwd pwr terminal TB6-1, a dc voltage detected by diode A3CR2 and representing the forward power of the transmitter, is passed to circuits within monitor pwb assembly AS. If the output voltage and current are out of phase, a dc voltage detected by diode A1CR1 and representing the reflected power of the transmitter, is applied through TB6-3 and passed to monitor pwb assembly AS. This sam pel waveform is passed through terminals 4 and 5 on TB6 and passed to RF MON connector 11 on the front panel. Relay K1 is for use on a dual transmitter only. If the main-side of a dual

transmitter fails, the +24 vdc input on TB6-6 will be inhibited, relay K1 (normally energized) will de-energize. -The if in (stby tx) input on connector 13 will be applied through if out connector J2. The if in (main TX) on connector 11 will be inhibited by the contacts of relay Kl. Current transformer T4 and a separate secondary winding of transformer T2 provide voltage or current waveform outputs (as selected by RF MON switch S1) for monitoring purposes. Rf Mon Switching: RF MON switch A7S1 allows selection of either the voltage or the current waveform to be monitored on rf monitor bnc connector 11 on the transmitter front panel. The following description provides the necessary information for the setting of the RF MON switch A7Sl. The high capacItIve reactance of the antenna is tuned at the carrier frequency by the ATU loading coils to produce a series resonant circuit. The resulting net antenna resistance is then transformed to 50 ohms in a matching transformer to provide the required load impedance for the transmitter. When the antenna is very short compared with the wavelength of the operating frequency, the series resonant circuit has na extreme1y high"Q.Under these conditions a perfect match may occur at the carrier frequency but the sidebands may be badly mismatched causing a standing wave on the feeder cable at the sideband frequencies, Depending upon the length of the feeder cable, the impedance at the sideband frequencies may appear higher or lower than 50 ohms at the transmitter output. If the sideband impedance appears low, the current waveform should be selected by RF MON switch A7S1 to prevent excessive current overloading of the transmitter. If the sideband impedance appears high, the voltage waveform should be selected by RF MON switch A7S1 to prevent excessive voltages occurring at the sideband frequency. The correct setting of RF MON switch A7S1 is made by choosing the waveform which displays the greater modulation depth. The phenomenon which results from the use of an inefficient antenna, produces a bandpass filter effect which reduces the modulation depth of the

radiated signal. Under no circumstances should the modulation level, as measured on either the current or voltage probe, be adjusted beyond 95 percent in an effort to offset the sideband attenuation which occurs in the antenna. This will cause excessive dissipation and distortion to occur and would create spurious emissions which do not comply with national an/or internation specifications. h. FREQUENCY SYNTHESIZER PWB (A4A3) (see figure SD-10): The frequency synthesizer pwb contains the following circuits; a 4.096MHz oscillator; a (PLL) divide by N divider; a low pass filter; a +8 vdc regulator; a +5 vdc regulator; a voltage controlled oscillator; a binary counter; a frequency selector and a balanced drive circuit. When installed, the subject pwb, provides the assigned carrier frequency for the transmitter. 4.096 MHz Oscillator: The 4.096MHz oscillator consists of transistors 01/02, crystal Yl and their associated components. A stable 4.096 MHz frequency is developed by transistor 01 and crystal Y1, applied thru buffer amplifier transistor 02 and passed to the osc in input of divide-by-N divider U2. The output of the 4.096MHz oscillator can be monitored at test point TPl. +8 Vdc Regulator: The +8 vdc regulator consists of +8.0 volt regulator U1 and its associated components. The + 15 vdc input on J1-2 is applied to regulator U1-1 and reduced to a regulated +8.0 volt dc supply for the divide by N divider circuit. The output of the +8 vdc regulator can be monitored at test point TP2. Divide by 'N' Divider: Parallel-input, phase-locked-loop, U2 and sections 1 thru 10 of Sl form the divide-by-N circuit. U2's RA inputs are connected to divide the 4.096MHz osc in frequency by 1024 and provide a 4000Hz reference frequency. This reference frequency is applied to one input of an integral phase detecting comparator. The frequency of the signal applied to U2/1's fiN input, from voltage-controlled oscillator U5, is divided by N (which is the sum of the binary number assigned the open sections of binary

switch Sl). The resultant is applied to the second input of U2's integral phase detecting comparator as the controlled frequency. - When the controlled frequency and the reference frequency (4000Hz) are equal, U2's phase R and phase V outputs will both essentially be a high level with extremely short duration, low level, in-phase, pulses at the reference frequency. - When the controlled frequency is higher than the reference frequency or the phase of the controlled frequency is leading; the duration of the phase V output's low level pulses will increase in proportion to the frequency/phase differential. The duration of the phase R output pulse will remain minimal. - 3 When the controlled frequency is less than the reference frequency or the phase of the controlled frequency is lagging; the duration of the phase R output's low level pulses will increase in proportion to the frequency/phase differential. The duration of the phase V output pulse will remain ininimal. - The setting of switch Sl's sections (1 thru 10) is dictated by the required carrier frequency. Refer to paragraph 3.8.7 for switch setting information. Low Pass Filter: Operational amplifiers U3NU3B and their associated components form a four-pole, low pass filter that applies a dc control voltage to varactor CR3, which in turn determines CR3's capacitance. - When CR3's capacitance results in voltage controlled oscillator U6's output being the desired frequency, U3B's non-inverting and inverting inputs will both be a high level; with short duration, low level, inphase, 4000Hz pulses. The low pass filter's output will be a dc control voltage to maintains this capacitance. - If voltage controlled oscillator U6's output frequency goes high, indicating the capacitance of CR3 is low, the duration of the low level pulses applied to U3B's non-inverting input will increase. The low pass filter's dc control voltage output will be reduced and cause CR3's

capacitance to increase. - If voltage controlled oscillator U6's output frequency goes low, indicating the capacitance of CR3 is high, the duration of the low level pulses applied to U3B's inverting input will increase. The low pass filter's dc control voltage output will be increased and cause CR3's capacitance to decrease +5 Vdc Regulator: Voltage regulator U4 and its associated components form the +5 vdc regulator. It reduces the + 15 vdc applied to its input to a regulated +5.0 vdc for the voltage controlled oscillator. TP3 provides a convenient test point to measure the regulated +5 vdc output. Voltage Controlled Oscillator: Varactor CR3, oscillator U5 and associated components form the voltage controlled oscillator. The capacitance of varactor CR3 which is in U5's LlC tank circuit, is determined by the magnitude of the dc control voltage applied to it by the low pass filter. When the dc control voltage goes more positive, CR3's capacitance will decrease and cause U5's output frequency to increase. Conversely, when the dc control voltage goes less positive, CR3's capacitance will increase and cause U5's output frequency to decrease. Binary Divider: 12-bit binary counter U6 and its associated components form the binary divider. Voltage controlled oscillator U5's output frequency is applied to U6's clock input. The Q2 (+4), Q3 (+8) and Q4 ( + 16) outputs are applied to carrier frequency selector U7. Frequency Selector: 4-channel analog multiplexer U7 and its associated components form the carrier frequency selector. The settings of sections 11 and 12 of switch S2, determine which X input of U7 is passed as its output. Refer to paragraph 3.8.7 for switch setting information. Balanced Drive: Transistors Q3/Q4 and their associated components form the balanced drive. The output of the balanced drive can be monitored at test point TP4.