ESSCIRC 2002

A Low-Voltage Fully Balanced OTA with Common Mode Feedforward and Inherent Common Mode Feedback Detector
Ahmed Nader Mohieldin Edgar Snchez-Sinencio Jos Silva-Martnez

Department of Electrical Engineering, Texas A&M University, College Station, Texas 77843, USA Abstract
A pseudo differential fully balanced CMOS OTA architecture with inherent common mode detection is proposed. Through judicious arrangement, the commonmode feedback circuit can be economically implemented. The OTA achieves a good CMRR and is suitable for low voltage operation. As an example of the applications of th the proposed OTA, a 100MHz 4 order linear phase OTA-C filter is presented. The measured group delay ripple is 3%, the filter dynamic range is 45dB. It consumes 42.9mW per complex poles. proposed. It is shown that a separate CMFB circuit can be avoided with appropriate arrangement of cascaded pseudo differential OTAs, for example in a filter. This approach takes advantage of the OTAs used for the differential mode operation to render low common mode gain without extra circuitry. The proposed OTA has inherently the common mode detector, hence the CMFB is economically realized.

2. Proposed OTA architecture

In general operational transconductance amplifiers can be divided into two main groups: Fully Differential (FD) and Pseudo Differential (PD). FD is based on a differential pair with tail current source and PD is based on two independent inverters without tail current source. Avoiding the voltage drop across the tail current source, in a PD structure, allows achieving wider linear input range and makes the architecture attractive for low voltage applications. Removing the tail current source, however, results in a poor rejection to common mode noise. Using a common mode feedforward (CMFF) technique, ACM at low frequency is in the order of unity [2]. A separate transconductance is often used for common mode detection [3]. This approach adds more load to the driving stage due to the connection of two input transistors, one for the differential transconductance and the other one for the common mode transconductance, thus doubling the input capacitance. The CMFF improves the rejection to common mode signals but it is incapable to fix the DC common mode output voltage. Figure 1 shows the circuit implementation of the proposed OTA. It can be described as a conventional three current mirror single ended OTA, without the tail current, plus the additional branches (dashed lines). Thus the OTA becomes fully balanced [4] and fully symmetric with enhanced features to be described.

1. Introduction
In general, a fully differential structure has an improved dynamic range over its single ended counterpart. This is due to better common mode noise rejection, better distortion performance, and increased output voltage swing. One important disadvantage of fully differential structures is the need of an extra common mode feedback (CMFB) circuit. A CMFB circuit is needed for two reasons: (1) To fix the common mode voltage (Vcm) at different high impedance nodes. (2) to suppress the common mode signal components, on the whole band of differential operation that tends to saturate different stages. A CMFB circuit is classically performed by means of a CMFB loop. The CMFB loop has to be designed carefully to avoid potential stability problems. This often increases the complexity of the design, the power consumption, and the silicon area used. The frequency response of the differential path is also degraded due to the added parasitic components involved in conventional CMFB schemes. In some cases and due to the system configuration, the CMFB requirements can be relaxed. For instance, if the common mode gain is sufficiently small, as would be the case of a conventional differential pair based OTA with a tail current, the CMFB bandwidth might be reduced. Its primary function will be to set the common mode voltage and it will not consume much power. Nevertheless, for good power supply rejection, a wide bandwidth CMFB is needed. In other cases, when the output is loaded by low impedance, the DC output voltage is well defined and assuming that the common mode gain is small enough, there may be no need for the CMFB circuitry as would be the case of filters built using lossy integrators [1]. In this work, a practical pseudo differential OTA is

2.1 Inherent common mode detection

It can be shown, using the quadratic I-V characteristics of a transistor (neglecting all short channel effects), that current (I1+ I2) in Figure 1 provides the information about the common mode level of the inputs as follows: v2 K W 2 (1) I 1 + I 2 = 2. P (V dd V icm VTP ) + d 2 L 1 4 + where Vi =Vicm+vd/2, and Vi =Vicm-vd/2.

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Note that after extracting the common mode information, the common mode current (I1+ I2)/2 is subtracted at the output nodes of the OTA, yielding (for M4=BM2): I I K W (2) I 01 = 2 1 = B P [Vdd Vicm VTP ]vd 2 2 L 1 K W I od = I 01 I 02 = B P [Vdd Vicm VTP ]vd = Gm v d (3) 2 L 1
VDD

iod gm2 g m1 (4) = g m1 = vd g m 2 + sCZ 1 + s / nd1 where CZ is the total parasitic capacitance at node VZ. Thus the excess phase is given by: gm (s) =
= tan 1 nd 1

(5)

M3

M3

VX

M3

M3

Note that CZ as well as gm2 are functions of W2 , thus (5) involves an iterative design procedure. L2 can be chosen to be minimum to reduce the excess phase although it will sacrifice the DC gain.

VDD
I1 + I 2 2 I1 + I 2 2

2.4 Linearity issues

Note from (3) that the linearization of the output current depends on the cancellation of the quadratic components of the individual currents I1 and I2. Due to transistor mismatches, this cancellation is not perfect and some second order distortion will result. Even order harmonics can also appear, even neglecting all mismatches, due to the cross product of differential and common mode signals. Thus, the common mode signal has to be suppressed as much as possible [3]. The main nonlinearity contribution for the proposed OTA structure is due to short channel effects. For short channel devices, the effective carrier mobility (eff) is no longer constant and is a function of both the longitudinal and transversal electric fields. Considering the degradation of mobility due to these effects and the channel length modulation effect, the drain current I of a transistor in saturation region is given by:
2

Vout+
I I I 01 = 2 1 2 I1

Vi+
I1

M1

M1

ViI2

VoutI 02 =
I2

I1 I 2 2

I1

I2

M4

M4

M2

M2

VZ

M4

M4

VSS

Figure 1. Proposed OTA architecure

2.2 CMFB and CMFF arrangements

Although the CMFF provides rejection to the common mode components at the output, we still need to fix the DC common mode output voltage. In the proposed OTA architecture, CMFB can be implemented by judiciously connecting at least two of the proposed OTAs. This can be achieved by adding the four transistors M3 =M3 and M4 =M4, as shown in Figure 2. The signal common mode components are suppressed by the action of the CMFF. The DC level of the output is sensed at node VX of the next OTA, and fedback by M3 ; id3 is then compared with the proper current id4 fixing the DC output level to the required value. This arrangement has the advantage that the differential mode signals and the common mode signals share basically the same loop, and the transconductance of the CMFB loop is the same as the differential mode transconductance.
VDD

VDD
VX (from next stage)
VX (from next stage)

Vref

M1

M 3

M3

M3

VX

M3

M3

M 3

VDD

Vout+

I1

Vi+

M1

M1

Vi-

I2

Vout-

I1
VY

I2

M2

M4

M4

M4

M2

M2

VZ

M4

M4

M4

VY

K P W (V SG VTP ) (6) [1 + VSD ] 2 L 1 + (V SG VTP ) where KP=effCox, eff=0/(1+E/EC), EC=sat/0, and =1/LEC. L is the device electrical channel length, Cox is the oxide capacitance per unit channel area, is the output impedance constant, 0 is the low-field mobility, sat is the saturation carrier drift velocity, E is the longitudinal electric field, and EC is the critical electric field. Note that the value of in (6) must be modified to include the effect of the transversal electric field. The value of and have been determined for the used technology by a best fit to the simulated device -1 characteristics, with minimum length L, to be 0.4V and -1 0.1V , respectively. If a differential signal is applied, then: (7) VSG-|VTP|=Vov+(vd/2) (8) VSD=VDC-k(vd/2) where Vov=Vdd-Vicm-|VTP| is the overdrive voltage, and k is the gain from the input to node Vz (see Figure 2). Substituting (7) and (8) in (6), we have: I=

VSS

Figure 2. OTA with CMFF and CMFB (M4=BM2)

2.3 Frequency response and excess phase

The differential mode transconductance of the proposed OTA, for M4=M2, can be written as:

2 K W 1 + V DC V ov + v d / 2 vd (9) I= P 1 2 2 L 1 + V ov 1 + (v d / 2) where =/(1+Vov), and =k/(1+VDC). Using taylor series expansion, with Vd=VPeakcos(t), yields:

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HD3

( + ) 2 2Vov

+ Vov 321 2

1 Vov

2 V Peak

(10)

Neglecting channel length modulation effect (for k=1, <, and VDC>Vov) and substitute the value of in (10), yields:
HD3
2 .VPeak

16Vov (1 + Vov ) 2 (2 + Vov )

2 .Vin _ rms

8Vov (1 + Vov ) 2 (2 + Vov )

(11)

is compensated for stability purposes by the load capacitance CL, which is also used for differential mode operation. The CMFB is idealy transparent to differential signals and acts at low frequencies as a resistor of value 1/gCMFB (gCMFB=gm1 is the small signal CMFB transconductance) for common mode signals. Thus for M4=M2, the common mode gain, ACM, is computed as: g m1.g m 2 ( g 0 + sC X ) (15) ACM ( s ) =
( g m 2 + sCZ )( g m 3 + sC X )[(GCMFB ( s) + g 0 + sC L )]

A direct tradeoff between linearity and frequency response (excess phase) is observed from (11). The smaller is, the wider the linear range for a given HD3. This can be accomplished by increasing the length of the channel ( 1/L) which at the same time increases the parasitic capacitances. Increasing Vov also improves the linearity at the expense of power consumption.

Note that ACM, at low frequency, is much less than unity; this is a result of the action of both CMFB and CMFF circuits.

4. Filter architecture
A fourth order linear phase Bessel-Thompson OTA-C filter has been implemented. The requirement is a group delay error less than 3% for frequencies up to 1.5xf0, where f0=50MHz and f-3dB=2.1xf0. The block diagram of the filter with the required CMFB arrangement is shown in Figure 3.
VBP1+ VLP1+ Vin+
CMFF+CMFB
(Fig. 2)

2.5 Noise performance

The encircled transistors in Figure 2 contribute to common mode noise only due to the symmetric configuration and thus their effect can be neglected. Consider only the integrated thermal noise power, where 2 V n=(8KT.BW/3gm), the input referred noise becomes:
V n2_ rms g 2 g m3 2g m4 16 KT .BW .1 + m 2 + = + 3 g m1 g m1 g m1 B 2 g m1 B 2

+
C1 A

CMFF
(Fig. 1)

CMFF+CMFB

+
+ g m1 A _
C2 A

+
g m1 A

CMFF

(12)
Vin-

+ g m1 A _

_
g m2 A

_ +

+
_

_
VBP1Common Mode Information

_
VLP1-

where BW is the equivalent noise bandwidth. Increasing B will reduce the noise, increase the effective transconductance and consequently gCMFB, but it directly deteriorates the excess phase as CZ increases. The accuracy of the current mirror is also less for large values of B. In this design B is chosen to be unity to maintain the ability for high frequency operation. Increasing gm1 will also reduce the noise, the payment is in the power consumption in this case. Using (11) and (12), the following expression for the SNR can be obtained:
2 Vin _ rms 3.HD3 .Vov (1 + Vov )(2 + Vov ).g m1 SNR = 10 log 2 10 log g + 2 g m3 + 2 g m 4 V n _ rms 2.BW .KT . 1 + m 2 g m1

VBP2+
CMFF

+
_ +
g m1B

VLP2+

CMFF+CMFB

CMFF

CMFF+CMFB

+
+ g _ m1B
_

+
g m2 B C1B

+
+ g _ m1B

C2 B

_ VLP2-

_
VBP2-

(13)

Figure 3. Filter architecture

For a given HD3, the maximum input voltage, and consequently the SNR, can increased by increasing VOV. The transconductance gm1 needs also to be maximized to reduce the noise contribution of subsequent transistors.

3. CMFB loop design considerations

The open loop gain of the CMFB, for M4=M2, is given by: g m1 g m2 g m3 G ( s ) (14) A ( s) = . . = CMFB
CMFB

g m 2 + sC Z g m 3 + sC X g o + sC L

g o + sC L

Note that the flow of the common mode information from one stage to the other is done in a natural way. The common mode level is sensed only once per output. Similarly, the output common mode level needs to be fixed only once for any number of OTAs sharing the same output. Thus, some of the fully fledged OTAs (with CMFB and CMFF) may be replaced by ones with CMFF only as that shown in Figure 1. For instance, gm2A, gm2B, the last stage of the first biquad, and the last stage of the second biquad do not need to have a CMFB since their outputs are common with other OTAs which will automatically fix the output DC level of the output.

where CX and CZ is the total parasitic capacitance at node VX and node VZ respectively, CL is the load capacitance, g0 is the output conductance. ACMFB should be made as high as possible at DC, and its bandwidth should be as high as the differential mode bandwidth. The CMFB loop

5. Measurement results
The filter has been fabricated in AMI 0.5m CMOS process. The chip micrograph is shown in Figure 4. It

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occupies a small area of 450x350 m . The transconductance, and consequently the 3dB frequency of the filter, can be tuned by changing Vicm. This is achieved by changing the CMFB reference voltage Vref (see Figure 2). Figure 5 shows the measured phase response of the filter. The group delay is shown in Figure 6. The measured group delay ripple is about 3% for frequencies up to 100 MHz. Figure 7 shows the filter output spectrum for a differential input signal of amplitude 350 mVpp and frequency 30 MHz. The total inband integrated output noise is about 700 Vrms. This corresponds to 45 dB of dynamic range (DR) for 0.5% + THD at 30 MHz. The measured CMRR, PSRR , and PSRR at 10MHz is 45 dB, 26 dB, and 35 dB, respectively, and is 32 dB, 21 dB, and 28 dB, respectively, at 50MHz. The filter consumes 26 mA from a 1.65 V power supply. Table 1 contains a summary of different filter performance parameters compared with previously reported works in [5] and [6].

Figure 7. Spectrum for a 350mVpp 30 MHz input signal

area of 0.16mm only. The group delay ripple is 3% for frequencies up to the 3dB frequency. Measured results assured the good performance of the proposed transconductance building block and its suitability for high frequency and low voltage operation.
Table 1. Filter Performance Parameters
Filter type and order

[5] 7th Order 0.050 Equirriple

[6]* 7th Order 0.050 Equirriple

This Work 4th Order Bessel

f-3 dB

50 MHz

100 MHz
< 5% @ f < 2f-3dB 100 mVp-p -46 dB N/A > 40 dB

100 MHz
< 3% @ f < f-3dB 350 mVp-p -46 dB 700 Vrms 45 dB

Figure 4. Chip micrograph

Ripple on < 2% @ group delay f < 1.5f-3dB Max Input 200 mVp-p THD -46 dB Output noise 1.7 mVrms DR 32 dB Power supply 3V Current drain 27 mA Technology 0.72m CMOS * Include filter boost

3V
40 mA
0.29m BiCMOS

3.3 V
26 mA
0.5m CMOS

Figure 5. Phase response

Figure 6. Group delay

6. Conclusions
A pseudo differential fully symmetric fully balanced OTA architecture has been presented. The proposed OTA features very attractive linearity properties and inherent common mode detection. It has been demonstrated that the structure made it easy to incorporate the CMFB arrangement. This is done at minimum cost of area and power consumption. The same principle can be applied to any OTA with CMFF to incorporate the detection of the common mode information of the previous stage for CMFB stabilization. th A 100 MHz 4 order linear phase OTA-C filter has been implemented in 0.5m CMOS process and occupies an

[1] A. Schaumann, Avoiding common mode feedback in continuous-time Gm-C filters by use of lossy integrators, IEEE International Symposium on Circuits and Systems, vol. 5, pp.281-284, 1994. [2] W. M. Snelgrove and A. Shoval, A balanced 0.9 m CMOS transconductance-C filter tunable over the VHF range, IEEE J. Solid-State Circuits, vol. 27, no. 30, pp.314-323, March 1992. [3] F. Rezzi, A. Baschirotto, and R. Castello, A 3V 12-55 MHz BiCMOS pseudo differential continuous-time filter, IEEE J. Solid-State Circuits, vol. 42, no. 11, pp.896-903, November 1995. [4] T. Itakura, T. Ueno, H. Tanimoto, and T. Arai, A 2 Vp-p linear input range fully balanced CMOS transconductor and its application to a 2.5V 2.5MHz Gm-C LPF, IEEE Custom Integrated Circuits, pp.509-512, 1999. [5] W. Dehaene, M.S.J. Steyaert, and W. Sansen, A 50 MHz standard CMOS pulse equalizer for hard disk read channels, IEEE J. Solid-State Circuits, vol. 32, no. 7, pp.977-988, July 1997. [6] N. Rao, V. Balan, and R. Contreras, A 3V 10-100MHz continuous-time seventh order 0.050 equiripple linear phase filter, IEEE J. Solid-State Circuits, vol. 34, no. 11, pp.16761682, Nov. 1999.

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References