EE143 F05 Lecture 21

Basic Structure of CMOS Inverter

Professor N Cheung, U.C. Berkeley 1

EE143 F05 Lecture 21

The MOSIS
CMOS Process

MOSIS is a foundry
service that provides
standard CMOS
fabrication

P-well CMOS

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EE143 F05 Lecture 21

Pattern mask opening

For p-well implant

Shallow implantation
of boron

Diffusion drive-in
To form p-well in
oxidizing ambient

Remove masking oxide

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EE143 F05 Lecture 21

Pad oxide growth and CVD Si3N4.

Pattern field oxide regions

Blanket implant of Boron for p

channel stop inside p-well

Protect p-well regions with

photoresist.
Implant Ph to form n channel
stop outside p-well regions

LOCOS Oxidation

Thermal oxidation of gate SiO2

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EE143 F05 Lecture 21

CVD poly-Si !!
Pattern poly-Si gates

Protect ALL n-channel

transistors with photoresist.

Boron implantation to
form source/drain of p-
channel transistors and
contacts to p-well
Professor N Cheung, U.C. Berkeley 5
EE143 F05 Lecture 21

Protect ALL p-channel

transistors with photoresist.

Arsenic implantation to form

source/drain of n-channel
transistors and contacts to n-
substrate

CVD SiO2
(Low-temperature oxide)

Pattern and etch contact

openings to source/drain, well
contact, and substrate contact.
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EE143 F05 Lecture 21

Metal 1 deposition

Pattern and etch

Metal 1 interconnects

CVD SiO2

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EE143 F05 Lecture 21

Pattern and etch contact

openings to Metal 1.

Metal 2 deposition.

Pattern, and etch Metal 2

interconnects.

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EE143 F05 Lecture 21

3D view of a CMOS inverter after contact etch.

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EE143 F05 Lecture 21

Well Engineering

P-tub

N-tub

Twin Tub

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EE143 F05 Lecture 21

Twin Well CMOS Process Flow

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EE143 F05 Lecture 21

Retrograde Well
- formed by high energy (>200keV) implantation

C(x) Conventional well (depth and profile

controlled by diffusion drive-in)

Retrograde well (depth and profile

controlled by implantation
energy and dose)

Professor N Cheung, U.C. Berkeley 12

EE143 F05 Lecture 21

Conventional vs Retrograde Well

1) Very low thermal budget for well formation

(no need for diffusion drive-in)

2) Retrograde Well is formed AFTER field oxidation

⇒ small lateral diffusion and localized high conc under FOX
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EE143 F05 Lecture 21

Example: Formation of Channel Stop and Retrograde Well

in a single step

Retrograde well
Channel stop
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EE143 F05 Lecture 21

Multiple Implants for Well Engineering

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EE143 F05 Lecture 21

Basic Silicon-on-Insulator (SOI) CMOS Process Flow

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EE143 F05 Lecture 21

SOI Process Flow (continued)

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EE143 F05 Lecture 21

Self-Aligned Channel V-gate by Optical Lithography

(SALVO) Process

Smallest feature
printable by
lithography
Normal
Oxide spacer poly-Si gate S/D implant

CVD oxide CVD oxide

n+ n+ n+
n+
SiO2
Angled Thermal
TiSi2 Implant gate oxide
n+ pocket
* Sub-50nm channels
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EE143 F05 Lecture 21

SALVO Process Flow

or

See HW#9 Problem

Chang et al, IEDM 2000
Professor N Cheung, U.C. Berkeley 19