Prepared by: Kenneth Joachim Llanto Last Updated: 08/25/11

Review Fixed Bias Voltage Divider Bias Emitter Stabilized Bias

A term defined as a control of voltage or current. Transistors must be biased correctly in order to produce the desired circuit voltages or current.

14 Saturation Region 12 10 IC in mA 8 6 4 2

100 mA
Active Region

80 mA
60 mA 40 mA 20 mA 0 mA

0 2 4 6 8 10 12 14 16 18 VCE in Volts

Cut-off Region

Load Line

14 IC(SAT) 12 10 IC in mA 8 6 4 2

100 mA 80 mA
Q - point 60 mA 40 mA 20 mA

VCE(OFF) 0 mA 0 2 4 6 8 10 12 14 16 18
VCE in Volts

Operating point (Quiescent point or Q pt.)

A fixed point on the collector curve and determines the operating region of the transistor (saturation, active or cut-off) The term quiescent means inactive, quiet or still.

DC loadline
A line that represents all the possible locations of the Q. point. A straight line that connects the saturation point and the cut-off point. A visual summary of all the possible transistor operation points

If the transistor is used as an amplifier, the operating point is at the active region and normally located near the center of the load line. If the transistor is at the active region:
VBE = 0.7V B-E junction is forward biased. VBC = negative voltage B-C junction is reverse biased.

Input Loop Equation

Vcc IBRB VBE 0

Output Loop Equation

Vcc ICRC VCE 0

Note:

= I C / IB

Sample Problem. Determine the following for a fixed bias circuit. Given the following. Vcc = 15V, RB = 180k. RC = 1K. Silicon Transistor. = 100
(a) IBQ (b) ICQ

(c) VCEQ

IC(SAT) is the Saturation (maximum) current

VCE(OFF) ) is the Cut-off

voltage at (zero) current

VCC - VCE IC = RC
14 12 10 IC in mA 8 6 4 2

A graph of this equation produces a load line.

100 mA

80 mA
60 mA

40 mA 20 mA
0 mA

0 2 4 6 8 10 12 14 16 18 VCE in Volts

12 V IC = 1 kW
1 kW Mental short RB RC

12 V

VCC

VBB

12 V

12 V This is the = 12 mA IC = Saturation (maximum) current. 1 kW 14 12 10 IC in mA 8 6 4 2 100 mA

80 mA
60 mA

40 mA 20 mA
0 mA

0 2 4 6 8 10 12 14 16 18 VCE in Volts

1 kW Mental open 12 V

RC

RB

VCC

VBB

12 V

VCE(cutoff) = VCC
14 12 10 IC in mA 8 6 4 2 100 mA

80 mA
60 mA

40 mA 20 mA
0 mA

0 2 4 6 8 10 12 14 16 18 VCE in Volts

Exercise: Determine the following for a fixed bias circuit. Given the following. Vcc = 12V, RB = 220K. RC = 220. Silicon Transistor. = 150
(a) IBQ (b) ICQ

(c) VCEQ
(d) IC(SAT) (e) VCE(OFF)

Exercise: Determine the following for a fixed bias circuit. Given the following. Vcc = 18V, RB = 390k. RC = 150. Silicon Transistor. = 100
(a) IBQ (b) ICQ

(c) VCEQ
(d) IC(SAT) (e) VCE(OFF)

Q point is very unstable:

collector current (IC) and collector-emitter voltage(VCE) is greatly affected by any change in beta() beta() is also affected by changes in temperature This makes the fixed bias the least popular biasing technique

Most Popular biasing technique because of its stability Is practically immune to changes in beta() if designed properly

VB =

RB2 x VCC RB1 +RB2

VE = VB -VBE IE = VE / RE IE IC VC = VCC - IC RC VCE = VCC - IC (RC + RE)

DC load line Endpoints:

IC(SAT) =

VCC RC + RE

VCE(CUT-OFF) = VCC

Sample Problem. Determine the following for a voltage divider bias circuit. Given the following. Vcc = 18V, RB1 = 33k, RB2 = 5.6k, RC = 1.5k, RE = 390, = 200 (a) VBQ (b) VEQ
(c) IEQ (d) ICQ (e)VCEQ

(f) IC(SAT)
(g) VCE(OFF) (h) Construct the dc load line

Exercise: Determine the following for a voltage divider bias circuit. Given the following: Vcc = 24V, RB1 = 8.2k, RB2 = 1.2k, RC = 1k, RE = 240, = 100 (a) VBQ (b) VEQ
(c) IEQ (d) ICQ (e)VCEQ (f) IC(SAT) (g) VCE(OFF)

(h) Construct the dc load line

Similar to fixed bias but with the addition of a resistor at the emitter terminal Provides more stability to temperature variations

Input Loop Equation

Output Loop Equation

Note:

= I C / IB

DC load line Endpoints:

IC(SAT) =

VCC RC + RE

VCE(CUT-OFF) = VCC

Sample Problem. Determine the following for a emitter stabilized bias circuit. Given the following. Vcc = 20V, RB = 430k, RC = 2k, RE = 1k, = 50 (a) IBQ (e)VCEQ

(b) VEQ
(c) ICQ (d) IEQ

(f) IC(SAT)
(g) VCE(OFF) (h) Construct the dc load line

Exercise: Determine the following for an emitter stabilized bias circuit. Given the following. Vcc = 18V, RB = 910k, RC = 2.2k, RE = 1.1k, = 220 (a) IBQ (e)VCEQ

(b) VEQ
(c) ICQ (d) IEQ

(f) IC(SAT)
(g) VCE(OFF) (h) Construct the dc load line

Lecture notes by Engr. Emmanuel Guevara Lecture notes by Engr. Amante Garcia Lecture notes by Engr. Angelo dela Cruz Electronic Devices and Circuit Theory by Boylestad and Nashelsky Grobs Basic Electronics by Schultz Electronic Principles by Malvino and Bates