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Data Sheet
High Performance, Enhanced FLASH
Microcontrollers with 10-Bit A/D
• The PICmicro family meets the specifications contained in the Microchip Data Sheet.
• Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
• Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
RA3/AN3/VREF+
RA2/AN2/VREF-
MCLR/VPP
RB5/PGM
PLCC
RB7/PGD
RB6/PGC
RA1/AN1
RA0/AN0
RB4
NC
NC
6
5
4
3
2
1
44
43
42
41
40
RA4/T0CKI 7 39 RB3/CCP2*
RA5/AN4/SS/LVDIN 8 38 RB2/INT2
RE0/RD/AN5 9 37 RB1/INT1
RE1/WR/AN6 10 PIC18F442 36 RB0/INT0
RE2/CS/AN7 11 35 VDD
VDD 12 PIC18F452 34 VSS
VSS 13 33 RD7/PSP7
OSC1/CLKI 14 32 RD6/PSP6
OSC2/CLKO/RA6 15 31 RD5/PSP5
RC0/T1OSO/T1CKI 16 30 RD4/PSP4
NC 171 29 RC7/RX/DT
19
20
21
22
23
24
25
26
27
28
8
RC1/T1OSI/CCP2*
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
NC
RC1/T1OSI/CCP2*
RC3/SCK/SCL
RC4/SDI/SDA
RC6/TX/CK
RC2/CCP1
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC5/SDO
NC
TQFP
44
43
42
41
40
39
38
37
36
35
34
RC7/RX/DT 1 33 NC
RD4/PSP4 2 32 RC0/T1OSO/T1CKI
RD5/PSP5 3 31 OSC2/CLKO/RA6
RD6/PSP6 4 30 OSC1/CLKI
RD7/PSP7 5 PIC18F442 29 VSS
VSS 6 28 VDD
VDD 7 PIC18F452 27 RE2/AN7/CS
RB0/INT0 8 26 RE1/AN6/WR
RB1/INT1 9 25 RE0/AN5/RD
RB2/INT2 10 24 RA5/AN4/SS/LVDIN
RB3/CCP2* 11 23 RA4/T0CKI
12
13
14
15
16
17
18
19
20
21
22
NC
NC
RB4
RB5/PGM
RB6/PGC
RB7/PGD
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
DIP
MCLR/VPP 1 40 RB7/PGD
RA0/AN0 2 39 RB6/PGC
RA1/AN1 3 38 RB5/PGM
RA2/AN2/VREF- 4 37 RB4
RA3/AN3/VREF+ 5 36 RB3/CCP2*
RA4/T0CKI 6 35 RB2/INT2
RA5/AN4/SS/LVDIN 7 34 RB1/INT1
PIC18F442
PIC18F452
RE0/RD/AN5 8 33 RB0/INT0
RE1/WR/AN6 9 32 VDD
RE2/CS/AN7 10 31 VSS
VDD 11 30 RD7/PSP7
VSS 12 29 RD6/PSP6
OSC1/CLKI 13 28 RD5/PSP5
OSC2/CLKO/RA6 14 27 RD4/PSP4
RC0/T1OSO/T1CKI 15 26 RC7/RX/DT
RC1/T1OSI/CCP2* 16 25 RC6/TX/CK
RC2/CCP1 17 24 RC5/SDO
RC3/SCK/SCL 18 23 RC4/SDI/SDA
RD0/PSP0 19 22 RD3/PSP3
RD1/PSP1 20 21 RD2/PSP2
DIP, SOIC
MCLR/VPP 1 28 RB7/PGD
RA0/AN0 2 27 RB6/PGC
RA1/AN1 3 26 RB5/PGM
RA2/AN2/VREF- 4 25 RB4
RA3/AN3/VREF+ 5 24 RB3/CCP2*
PIC18F242
PIC18F252
RA4/T0CKI 6 23 RB2/INT2
RA5/AN4/SS/LVDIN 7 22 RB1/INT1
VSS 8 21 RB0/INT0
OSC1/CLKI 9 20 VDD
OSC2/CLKO/RA6 10 19 VSS
RC0/T1OSO/T1CKI 11 18 RC7/RX/DT
RC1/T1OSI/CCP2* 12 17 RC6/TX/CK
RC2/CCP1 13 16 RC5/SDO
RC3/SCK/SCL 14 15 RC4/SDI/SDA
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
• The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter-
ature number) you are using.
PORTA
Table Pointer <2> Data Latch
21 RA0/AN0
8 8 8 Data RAM RA1/AN1
21 inc/dec logic RA2/AN2/VREF-
RA3/AN3/VREF+
21 Address Latch RA4/T0CKI
20 PCLATU PCLATH (2) RA5/AN4/SS/LVDIN
Address Latch 12 RA6
Program Memory Address<12>
(up to 2 Mbytes) PCU PCH PCL
Program Counter 4 12 4
Data Latch BSR FSR0 Bank0, F
16 inc/dec
Decode logic
Table Latch
8 PORTB
ROM Latch
RB0/INT0
RB1/INT1
RB2/INT2
Instruction
Register RB3/CCP2(1)
RB4
8 RB5/PGM
Instruction RB6/PCG
Decode & RB7/PGD
Control PRODH PRODL
OSC2/CLKO
OSC1/CLKI 3
8 x 8 Multiply
Power-up
Timer 8
Master Addressable
CCP1 CCP2 Synchronous USART Data EEPROM
Serial Port
Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.
2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF instruction).
3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations
are device dependent.
8
ROM Latch PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
Instruction RC2/CCP1
Register RC3/SCK/SCL
RC4/SDI/SDA
8 RC5/SDO
Instruction
Decode & RC6/TX/CK
Control RC7/RX/DT
PRODH PRODL
OSC2/CLKO
OSC1/CLKI 3
8 x 8 Multiply
Power-up PORTD
Timer 8
RD0/PSP0
T1OSCI Timing Oscillator BIT OP WREG RD1/PSP1
T1OSCO Generation Start-up Timer 8 RD2/PSP2
8 8
Power-on RD3/PSP3
Reset RD4/PSP4
8
RD5/PSP5
4X PLL Watchdog RD6/PSP6
Timer ALU<8>
RD7/PSP7
Brown-out
Precision 8
Reset PORTE
Voltage
Reference Low Voltage
MCLR Programming RE0/AN5/RD
Master
CCP2 Synchronous Addressable Parallel Slave Port Data EEPROM
CCP1
Serial Port USART
Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.
2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF instruction).
3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations
are device dependent.
MCLR/VPP 1 2 18
MCLR I ST Master Clear (Reset) input. This pin is an active
low RESET to the device.
VPP P Programming voltage input.
NC — — — These pins should be left unconnected.
OSC1/CLKI 13 14 30
OSC1 I ST Oscillator crystal input or external clock
source input. ST buffer when configured in
RC mode, CMOS otherwise.
CLKI I CMOS External clock source input. Always
associated with pin function OSC1. (See
related OSC1/CLKIN, OSC2/CLKOUT pins.)
OSC2/CLKO/RA6 14 15 31
OSC2 O — Oscillator crystal output. Connects to crystal
or resonator in Crystal Oscillator mode.
CLKO O — In RC mode, OSC2 pin outputs CLKOUT,
which has 1/4 the frequency of OSC1 and
denotes the instruction cycle rate.
RA6 I/O TTL General Purpose I/O pin.
PORTA is a bi-directional I/O port.
RA0/AN0 2 3 19
RA0 I/O TTL Digital I/O.
AN0 I Analog Analog input 0.
RA1/AN1 3 4 20
RA1 I/O TTL Digital I/O.
AN1 I Analog Analog input 1.
RA2/AN2/VREF- 4 5 21
RA2 I/O TTL Digital I/O.
AN2 I Analog Analog input 2.
VREF- I Analog A/D Reference Voltage (Low) input.
RA3/AN3/VREF+ 5 6 22
RA3 I/O TTL Digital I/O.
AN3 I Analog Analog input 3.
VREF+ I Analog A/D Reference Voltage (High) input.
RA4/T0CKI 6 7 23
RA4 I/O ST/OD Digital I/O. Open drain when configured as output.
T0CKI I ST Timer0 external clock input.
RA5/AN4/SS/LVDIN 7 8 24
RA5 I/O TTL Digital I/O.
AN4 I Analog Analog input 4.
SS I ST SPI Slave Select input.
LVDIN I Analog Low Voltage Detect Input.
RA6 (See the OSC2/CLKO/RA6 pin.)
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open Drain (no P diode to VDD)
SLEEP
RS(2)
C2(1) PIC18FXXX
OSC2
1.0 MHz 15 pF 15 pF
4.0 MHz 15 pF 15 pF
2.3 RC Oscillator
HS 4.0 MHz 15 pF 15 pF
8.0 MHz 15-33 pF 15-33 pF For timing-insensitive applications, the “RC” and
“RCIO” device options offer additional cost savings.
20.0 15-33 pF 15-33 pF
The RC oscillator frequency is a function of the supply
MHz
voltage, the resistor (REXT) and capacitor (CEXT) val-
25.0 TBD TBD ues and the operating temperature. In addition to this,
MHz the oscillator frequency will vary from unit to unit due to
These values are for design guidance only. normal process parameter variation. Furthermore, the
See notes following this table. difference in lead frame capacitance between package
types will also affect the oscillation frequency, espe-
Crystals Used
cially for low CEXT values. The user also needs to take
32.0 kHz Epson C-001R32.768K-A ± 20 PPM into account variation due to tolerance of external R
200 kHz STD XTL 200.000KHz ± 20 PPM and C components used. Figure 2-3 shows how the
R/C combination is connected.
1.0 MHz ECS ECS-10-13-1 ± 50 PPM
4.0 MHz ECS ECS-40-20-1 ± 50 PPM In the RC oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
8.0 MHz Epson CA-301 8.000M-C ± 30 PPM may be used for test purposes or to synchronize other
20.0 MHz Epson CA-301 20.000M-C ± 30 PPM logic.
An external clock source may also be connected to the The RCIO oscillator mode functions like the RC mode,
OSC1 pin in the HS, XT and LP modes, as shown in except that the OSC2 pin becomes an additional gen-
Figure 2-2. eral purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6).
Phase
OSC2 Comparator
FIN Loop
VCO
Crystal Filter
Osc
FOUT SYSCLK
MUX
OSC1 Divide by 4
PIC18FXXX
Main Oscillator
OSC2
Tosc/4
SLEEP 4 x PLL
TOSC TSCLK
MUX
OSC1
Timer1 Oscillator
TT1P
T1OSO
T1OSCEN
Enable Clock
T1OSI Oscillator Source
Legend
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
FIGURE 2-8: TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR
Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
TT1P
T1OSI 1 2 3 4 5 6 7 8
Tscs
OSC1
TOSC
Internal
System TDLY
Clock
SCS
(OSCCON<0>)
Program PC PC + 2 PC + 4
Counter
Note 1: Delay on internal system clock is eight oscillator cycles for synchronization.
The sequence of events that takes place when switch- If the main oscillator is configured for an external crys-
ing from the Timer1 oscillator to the main oscillator will tal (HS, XT, LP), then the transition will take place after
depend on the mode of the main oscillator. In addition an oscillator start-up time (TOST) has occurred. A timing
to eight clock cycles of the main oscillator, additional diagram, indicating the transition from the Timer1 oscil-
delays may take place. lator to the main oscillator for HS, XT and LP modes, is
shown in Figure 2-9.
FIGURE 2-9: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)
Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3
TT1P
T1OSI
OSC1 1 2 3 4 5 6 7 8
TOST TSCS
OSC2
TOSC
Internal System
Clock
SCS
(OSCCON<0>)
Program Counter PC PC + 2 PC + 6
FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL)
Q4 Q1 TT1P Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
T1OSI
OSC1
TOST
TPLL
OSC2
TOSC TSCS
PLL Clock
1 2 3 4 5 6 7 8
Input
Internal System
Clock
SCS
(OSCCON<0>)
Program Counter PC PC + 2 PC + 4
FIGURE 2-11: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TT1P
T1OSI TOSC
OSC1 1 2 3 4 5 6 7 8
OSC2
Internal System
Clock
SCS
(OSCCON<0>)
TSCS
Program Counter PC PC + 2 PC + 4
2.8 Power-up Delays With the PLL enabled (HS/PLL oscillator mode), the
time-out sequence following a Power-on Reset is differ-
Power up delays are controlled by two timers, so that ent from other oscillator modes. The time-out sequence
no external RESET circuitry is required for most appli- is as follows: First, the PWRT time-out is invoked after
cations. The delays ensure that the device is kept in a POR time delay has expired. Then, the Oscillator
RESET, until the device power supply and clock are Start-up Timer (OST) is invoked. However, this is still
stable. For additional information on RESET operation, not a sufficient amount of time to allow the PLL to lock
see the “Reset” section. at high frequencies. The PWRT timer is used to provide
The first timer is the Power-up Timer (PWRT), which an additional fixed 2ms (nominal) time-out to allow the
optionally provides a fixed delay of 72 ms (nominal) on PLL ample time to lock to the incoming clock frequency.
power-up only (POR and BOR). The second timer is
the Oscillator Start-up Timer (OST), intended to keep
the chip in RESET until the crystal oscillator is stable.
External Reset
MCLR
SLEEP
WDT WDT
Module Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Reset S
BOREN
OST/PWRT
OST
Chip_Reset
10-bit Ripple Counter R Q
OSC1
PWRT
On-chip
RC OSC(1) 10-bit Ripple Counter
Enable PWRT
Enable OST(2)
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
2: See Table 3-1 for time-out situations.
VDD
3.5 Brown-out Reset (BOR)
A configuration bit, BOREN, can disable (if clear/
D R programmed) or enable (if set) the Brown-out Reset cir-
R1 cuitry. If VDD falls below parameter D005 for greater
MCLR than parameter #35, the brown-out situation will reset
C PIC18FXXX the chip. A RESET may not occur if VDD falls below
parameter D005 for less than parameter #35. The chip
will remain in Brown-out Reset until VDD rises above
BVDD. If the Power-up Timer is enabled, it will be
invoked after VDD rises above BVDD; it then will keep
Note 1: External Power-on Reset circuit is required the chip in RESET for an additional time delay (param-
only if the VDD power-up slope is too slow. eter #33). If VDD drops below BVDD while the Power-up
The diode D helps discharge the capacitor Timer is running, the chip will go back into a Brown-out
quickly when VDD powers down. Reset and the Power-up Timer will be initialized. Once
2: R < 40 kΩ is recommended to make sure that VDD rises above BVDD, the Power-up Timer will exe-
the voltage drop across R does not violate cute the additional time delay.
the device’s electrical specification.
3: R1 = 100Ω to 1 kΩ will limit any current flow- 3.6 Time-out Sequence
ing into MCLR from external capacitor C, in
On power-up, the time-out sequence is as follows:
the event of MCLR/VPP pin breakdown due to
Electrostatic Discharge (ESD) or Electrical
First, PWRT time-out is invoked after the POR time
Overstress (EOS). delay has expired. Then, OST is activated. The total
time-out will vary based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
3.2 Power-up Timer (PWRT) the PWRT disabled, there will be no time-out at all.
Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and
The Power-up Timer provides a fixed nominal time-out
Figure 3-7 depict time-out sequences on power-up.
(parameter #33) only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator. Since the time-outs occur from the POR pulse, if MCLR
The chip is kept in RESET as long as the PWRT is is kept low long enough, the time-outs will expire.
active. The PWRT’s time delay allows VDD to rise to an Bringing MCLR high will begin execution immediately
acceptable level. A configuration bit is provided to (Figure 3-5). This is useful for testing purposes or to
enable/disable the PWRT. synchronize more than one PIC18FXXX device operat-
ing in parallel.
The power-up time delay will vary from chip-to-chip due
to VDD, temperature and process variation. See DC Table 3-2 shows the RESET conditions for some
parameter #33 for details. Special Function Registers, while Table 3-3 shows the
RESET conditions for all the registers.
TABLE 3-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Program RCON
Condition RI TO PD POR BOR STKFUL STKUNF
Counter Register
Power-on Reset 0000h 0--1 1100 1 1 1 0 0 u u
MCLR Reset during normal 0000h 0--u uuuu u u u u u u u
operation
Software Reset during normal 0000h 0--0 uuuu 0 u u u u u u
operation
Stack Full Reset during normal 0000h 0--u uu11 u u u u u u 1
operation
Stack Underflow Reset during 0000h 0--u uu11 u u u u u 1 u
normal operation
MCLR Reset during SLEEP 0000h 0--u 10uu u 1 0 u u u u
WDT Reset 0000h 0--u 01uu 1 0 1 u u u u
WDT Wake-up PC + 2 u--u 00uu u 0 0 u u u u
Brown-out Reset 0000h 0--1 11u0 1 1 1 1 0 u u
(1)
Interrupt wake-up from SLEEP PC + 2 u--u 00uu u 1 0 u u u u
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0'
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0x000008h or 0x000018h).
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
FIGURE 3-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
IINTERNAL POR
TPWRT
PLL TIME-OUT
INTERNAL RESET
High Priority Interrupt Vector 0008h High Priority Interrupt Vector 0008h
Low Priority Interrupt Vector 0018h Low Priority Interrupt Vector 0018h
On-chip
Program Memory
3FFFh
4000h
On-chip
User Memory Space
7FFFh
Read ’0’ 8000h
Read ’0’
1FFFFFh 1FFFFFh
200000h 200000h
Note 1: Bit 7 and bit 6 can only be cleared in user software or by a POR.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2 Internal
Phase
Q3 Clock
Q4
PC PC PC+2 PC+4
OSC2/CLKOUT
(RC mode)
Execute INST (PC-2)
Fetch INST (PC) Execute INST (PC)
Fetch INST (PC+2) Execute INST (PC+2)
Fetch INST (PC+4)
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
4.7 Instructions in Program Memory aries, the data contained in the instruction is a word
address. The word address is written to PC<20:1>,
The program memory is addressed in bytes. Instruc- which accesses the desired byte address in program
tions are stored as two bytes or four bytes in program memory. Instruction #2 in Figure 4-5 shows how the
memory. The Least Significant Byte of an instruction instruction “GOTO 000006h’ is encoded in the program
word is always stored in a program memory location memory. Program branch instructions which encode a
with an even address (LSB =’0’). Figure 4-5 shows an relative address offset operate in the same manner.
example of how instruction words are stored in the pro- The offset value stored in a branch instruction repre-
gram memory. To maintain alignment with instruction sents the number of single word instructions that the
boundaries, the PC increments in steps of 2 and the PC will be offset by. Section 19.0 provides further
LSB will always read ’0’ (see Section 4.4). details of the instruction set.
The CALL and GOTO instructions have an absolute pro-
gram memory address embedded into the instruction.
Since instructions are always stored on word bound-
Word Address
LSB = 1 LSB = 0 ↓
Program Memory 000000h
Byte Locations → 000002h
000004h
000006h
Instruction 1: MOVLW 055h 0Fh 55h 000008h
Instruction 2: GOTO 000006h EFh 03h 00000Ah
F0h 00h 00000Ch
Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh
F4h 56h 000010h
000012h
000014h
CASE 2:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes
1111 0100 0101 0110 ; 2nd operand becomes NOP
0010 0100 0000 0000 ADDWF REG3 ; continue code
00h 000h
= 0000 Access RAM 07Fh
Bank 0 080h
FFh GPR
0FFh
00h 100h
= 0001 GPR
Bank 1
FFh 1FFh
200h
GPR
2FFh
300h
Access Bank
00h
Access RAM low
7Fh
= 0010 Access RAM high 80h
Bank 2 Unused
to (SFRs)
= 1110 Read ’00h’ FFh
Bank 14
When a = 0,
the BSR is ignored and the
Access Bank is used.
The first 128 bytes are General
Purpose RAM (from Bank 0).
The second 128 bytes are
Special Function Registers
EFFh (from Bank 15).
00h F00h
= 1111 Unused F7Fh
Bank 15
SFR F80h
FFh FFFh
When a = 1,
the BSR is used to specify the
RAM location that the instruc-
tion uses.
00h 000h
= 0000 Access RAM
Bank 0 07Fh
GPR 080h
FFh 0FFh
00h 100h
= 0001 GPR
Bank 1
FFh 1FFh
00h 200h
= 0010
Bank 2 GPR
FFh 2FFh
00h 300h
= 0011
Bank 3 GPR
FFh 3FFh
400h
= 0100
Bank 4 GPR Access Bank
4FFh 00h
00h 500h Access RAM low
= 0101 7Fh
Bank 5 GPR
Access RAM high 80h
FFh 5FFh (SFR’s)
600h FFh
When a = 0,
= 0110
Bank 6 Unused the BSR is ignored and the
= 1110 to Read ’00h’ Access Bank is used.
Bank 14 The first 128 bytes are General
Purpose RAM (from Bank 0).
The second 128 bytes are
Special Function Registers
EFFh (from Bank 15).
00h F00h
= 1111 Unused F7Fh
Bank 15 F80h
FFh SFR
FFFh
When a = 1,
the BSR is used to specify the
RAM location that the instruc-
tion uses.
Value on
Details
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR,
on page:
BOR
Value on
Details
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR,
on page:
BOR
Data
Memory(1)
0h
RAM
Instruction
Executed
Opcode Address
FFFh
12
BSR<3:0> 12 12
Instruction
4 8
Fetched
Opcode File FSR
Indirect Addressing
11 FSR Register 0
Location Select
0000h
Data
Memory(1)
0FFFh
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Instruction: TBLRD*
Program Memory
Table Pointer(1)
Table Latch (8-bit)
TBLPTRU TBLPTRH TBLPTRL
TABLAT
Program Memory
(TBLPTR)
Instruction: TBLWT*
Program Memory
Holding Registers
Table Pointer(1) Table Latch (8-bit)
TBLPTRU TBLPTRH TBLPTRL TABLAT
Program Memory
(TBLPTR)
Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by
TBLPTRL<2:0>. The process for physically writing data to the Program Memory Array is discussed in
Section 5.5.
5.2 Control Registers The FREE bit, when set, will allow a program memory
erase operation. When the FREE bit is set, the erase
Several control registers are used in conjunction with operation is initiated on the next WR command. When
the TBLRD and TBLWT instructions. These include the: FREE is clear, only writes are enabled.
• EECON1 register The WREN bit, when set, will allow a write operation.
• EECON2 register On power-up, the WREN bit is clear. The WRERR bit is
• TABLAT register set when a write operation is interrupted by a MCLR
• TBLPTR registers Reset or a WDT Time-out Reset during normal opera-
tion. In these situations, the user can check the
5.2.1 EECON1 AND EECON2 REGISTERS WRERR bit and rewrite the location. It is necessary to
reload the data and address registers (EEDATA and
EECON1 is the control register for memory accesses. EEADR), due to RESET values of zero.
EECON2 is not a physical register. Reading EECON2 Control bits RD and WR initiate read and write opera-
will read all '0's. The EECON2 register is used exclu- tions, respectively. These bits cannot be cleared, only
sively in the memory write and erase sequences. set, in software. They are cleared in hardware at the
Control bit CFGS determines if the access will be a pro- completion of the read or write operation. The inability
gram or data EEPROM memory access. When clear, to clear the WR bit in software prevents the accidental
any subsequent operations will operate on the data or premature termination of a write operation. The RD
EEPROM memory. When set, any subsequent opera- bit cannot be set when accessing program memory
tions will operate on the program memory. (EEPGD = 1).
Control bit EEFS determines if the access will be to the
configuration/calibration registers or to program
Note: Interrupt flag bit EEIF, in the PIR2 register,
memory/data EEPROM memory. When set, subse-
is set when the write is complete. It must
quent operations will operate on configuration regis-
be cleared in software.
ters, regardless of EEPGD (see “Special Features of
the CPU”, Section 19.0). When clear, memory selec-
tion access is determined by EEPGD.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
TABLE 5-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
ERASE - TBLPTR<21:6>
WRITE - TBLPTR<21:3>
READ - TBLPTR<21:0>
Program Memory
TABLAT
Write Register
8 8 8 8
Program Memory
5.5.2 WRITE VERIFY grammed if needed.The WRERR bit is set when a write
operation is interrupted by a MCLR Reset, or a WDT
Depending on the application, good programming Time-out Reset during normal operation. In these situ-
practice may dictate that the value written to the mem- ations, users can check the WRERR bit and rewrite the
ory should be verified against the original value. This location.
should be used in applications where excessive writes
can stress bits near the specification limit. 5.5.5 PROTECTION AGAINST SPURIOUS
WRITES
5.5.3 MAXIMIZING ENDURANCE
To protect against spurious writes to FLASH program
For applications that will exceed 10% of the minimum
memory, the write initiate sequence must also be fol-
specified cell endurance (parameters D120 and D120A),
lowed. See “Special Features of the CPU”
every location should be refreshed within intervals not
(Section 19.0) for more detail.
exceeding 1/10 of this specified cell endurance. Please
refer to AN790 (DS00790) for more details. 5.6 FLASH Program Operation During
5.5.4 UNEXPECTED TERMINATION OF Code Protection
WRITE OPERATION See “Special Features of the CPU” (Section 19.0) for
If a write is terminated by an unplanned event, such as details on code protection of FLASH program memory.
loss of power or an unexpected RESET, the memory
location just programmed should be verified and repro-
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
6.4 Writing to the Data EEPROM cution (i.e., runaway programs). The WREN bit should
Memory be kept clear at all times, except when updating the
EEPROM. The WREN bit is not cleared by hardware
To write an EEPROM data location, the address must
After a write sequence has been initiated, EECON1,
first be written to the EEADR register and the data writ-
EEADR and EDATA cannot be modified. The WR bit
ten to the EEDATA register. Then the sequence in
will be inhibited from being set unless the WREN bit is
Example 6-2 must be followed to initiate the write cycle.
set. The WREN bit must be set on a previous instruc-
The write will not initiate if the above sequence is not tion. Both WR and WREN cannot be set with the same
exactly followed (write 55h to EECON2, write AAh to instruction.
EECON2, then set WR bit) for each byte. It is strongly
At the completion of the write cycle, the WR bit is
recommended that interrupts be disabled during this
cleared in hardware and the EEPROM Write Complete
code segment.
Interrupt Flag bit (EEIF) is set. The user may either
Additionally, the WREN bit in EECON1 must be set to enable this interrupt, or poll this bit. EEIF must be
enable writes. This mechanism prevents accidental cleared by software.
writes to data EEPROM due to unexpected code exe-
Program Time
Cycles
Routine Multiply Method Memory
(Max) @ 40 MHz @ 10 MHz @ 4 MHz
(Words)
Without hardware multiply 13 69 6.9 µs 27.6 µs 69 µs
8 x 8 unsigned
Hardware multiply 1 1 100 ns 400 ns 1 µs
Without hardware multiply 33 91 9.1 µs 36.4 µs 91 µs
8 x 8 signed
Hardware multiply 6 6 600 ns 2.4 µs 6 µs
Without hardware multiply 21 242 24.2 µs 96.8 µs 242 µs
16 x 16 unsigned
Hardware multiply 24 24 2.4 µs 9.6 µs 24 µs
Without hardware multiply 52 254 25.4 µs 102.6 µs 254 µs
16 x 16 signed
Hardware multiply 36 36 3.6 µs 14.4 µs 36 µs
XXXXIF IPEN
XXXXIE GIEL/PEIE
XXXXIP
IPEN
Additional Peripheral Interrupts
High Priority Interrupt Generation
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
Note 1: This bit is reserved on PIC18F2X2 devices; always maintain this bit clear.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Note 1: This bit is reserved on PIC18F2X2 devices; always maintain this bit clear.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Note 1: This bit is reserved on PIC18F2X2 devices; always maintain this bit set.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Data
RD LATA Bus
Data RD LATA
Bus D Q
D Q
WR LATA VDD
or CK Q I/O pin(1)
PORTA N
Data Latch CK Q P
WR LATA
D Q VSS or Data Latch
PORTA
N I/O pin(1)
WR TRISA Schmitt D Q
CK Q
Trigger
TRIS Latch Input
Buffer CK Q VSS
WR
TRISA TRIS Latch
RD TRISA
TTL
Q D Input
RD TRISA Buffer
ENEN
ECRA6 or
RD PORTA RCRA6
Enable
Q D
TMR0 Clock Input
EN
Note 1: I/O pins have protection diodes to VDD and VSS.
RD PORTA
Four of the PORTB pins, RB7:RB4, have an interrupt- Note 1: I/O pins have diode protection to VDD and VSS.
on-change feature. Only pins configured as inputs can 2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (INTCON2<7>).
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB Port Change
Interrupt with flag bit, RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of PORTB (except with the
MOVFF instruction). This will end the mismatch
condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
TRIS Latch
D Q
TTL
WR TRIS Input
CK Buffer
RD TRIS
Q D
RD Port EN
RB0/INT
CCP Output(3) 1
VDD
P
0
Enable(3)
CCP Output
Data Latch
Data Bus I/O pin(1)
D Q
WR LATB or
WR PORTB N
CK
TRIS Latch VSS
D
TTL
WR TRISB Input
CK Q Buffer
RD TRISB
RD LATB
Q D
RD PORTB EN
RD PORTB
CCP2 Input(3)
Schmitt Trigger
Buffer
CCP2MX = 0
Note 1: I/O pin has diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate DDR bit(s) and clear the RBPU bit (INTCON2<7>).
3: The CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (=’0’) in the configuration register.
Port/Peripheral Select(2)
VDD
Peripheral Data Out
RD LATC
0
Data Latch
Data Bus
D Q P
WR LATC or
WR PORTC 1
CK Q I/O pin(1)
TRIS Latch
D Q
WR TRISC
CK Q N
RD TRISC Schmitt
VSS Trigger
Peripheral Output
Enable(3)
Q D
EN
RD PORTC
Peripheral Data In
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
LATC LATC Data Output Register xxxx xxxx uuuu uuuu
TRISC PORTC Data Direction Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged
RD0/PSP0 bit0 ST/TTL(1) Input/output port pin or parallel slave port bit0.
RD1/PSP1 bit1 ST/TTL(1) Input/output port pin or parallel slave port bit1.
(1)
RD2/PSP2 bit2 ST/TTL Input/output port pin or parallel slave port bit2.
RD3/PSP3 bit3 ST/TTL(1) Input/output port pin or parallel slave port bit3.
RD4/PSP4 bit4 ST/TTL(1) Input/output port pin or parallel slave port bit4.
RD5/PSP5 bit5 ST/TTL(1) Input/output port pin or parallel slave port bit5.
(1)
RD6/PSP6 bit6 ST/TTL Input/output port pin or parallel slave port bit6.
RD7/PSP7 bit7 ST/TTL(1) Input/output port pin or parallel slave port bit7.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port mode.
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu
LATD LATD Data Output Register xxxx xxxx uuuu uuuu
TRISD PORTD Data Direction Register 1111 1111 1111 1111
TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTD.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Chip Select
TTL CS
Write
TTL WR
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
PORTD Port Data Latch when written; Port pins when read xxxx xxxx uuuu uuuu
LATD LATD Data Output bits xxxx xxxx uuuu uuuu
TRISD PORTD Data Direction bits 1111 1111 1111 1111
PORTE — — — — — RE2 RE1 RE0 ---- -000 ---- -000
LATE — — — — — LATE Data Output bits ---- -xxx ---- -uuu
TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111
GIE/ PEIE/ 0000 000x 0000 000u
INTCON TMR0IF INT0IE RBIE TMR0IF INT0IF RBIF
GIEH GIEL
PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 00-- 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Data Bus
FOSC/4 0
8
0
Sync with
1 Internal TMR0
RA4/T0CKI pin Clocks
Programmable 1
Prescaler
T0SE (2 TCY delay)
3 PSA
Set Interrupt
T0PS2, T0PS1, T0PS0 Flag bit TMR0IF
T0CS on Overflow
Note: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FOSC/4 0
0
Sync with Set Interrupt
1 Internal TMR0L TMR0
Clocks High Byte Flag bit TMR0IF
T0CKI pin Programmable 1 on Overflow
Prescaler 8
T0SE (2 TCY delay)
3
Read TMR0L
T0PS2, T0PS1, T0PS0
T0CS PSA Write TMR0L
8
8
TMR0H
Data Bus<7:0>
Note: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
Timer0 can operate as a timer or as a counter. The prescaler assignment is fully under software con-
Timer mode is selected by clearing the T0CS bit. In trol, (i.e., it can be changed “on-the-fly” during program
Timer mode, the Timer0 module will increment every execution).
instruction cycle (without prescaler). If the TMR0 regis-
ter is written, the increment is inhibited for the following
10.3 Timer0 Interrupt
two instruction cycles. The user can work around this The TMR0 interrupt is generated when the TMR0 reg-
by writing an adjusted value to the TMR0 register. ister overflows from FFh to 00h in 8-bit mode, or FFFFh
Counter mode is selected by setting the T0CS bit. In to 0000h in 16-bit mode. This overflow sets the TMR0IF
Counter mode, Timer0 will increment, either on every bit. The interrupt can be masked by clearing the
rising or falling edge of pin RA4/T0CKI. The increment- TMR0IE bit. The TMR0IE bit must be cleared in soft-
ing edge is determined by the Timer0 Source Edge ware by the Timer0 module Interrupt Service Routine
Select bit (T0SE). Clearing the T0SE bit selects the ris- before re-enabling this interrupt. The TMR0 interrupt
ing edge. Restrictions on the external clock input are cannot awaken the processor from SLEEP, since the
discussed below. timer is shut-off during SLEEP.
When an external clock input is used for Timer0, it must 10.4 16-Bit Mode Timer Reads and
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
Writes
phase clock (TOSC). Also, there is a delay in the actual TMR0H is not the high byte of the timer/counter in
incrementing of Timer0 after synchronization. 16-bit mode, but is actually a buffered version of the
high byte of Timer0 (refer to Figure 10-2). The high byte
10.2 Prescaler of the Timer0 counter/timer is not directly readable nor
An 8-bit counter is available as a prescaler for the Timer0 writable. TMR0H is updated with the contents of the
module. The prescaler is not readable or writable. high byte of Timer0 during a read of TMR0L. This pro-
vides the ability to read all 16-bits of Timer0 without
The PSA and T0PS2:T0PS0 bits determine the pres- having to verify that the read of the high and low byte
caler assignment and prescale ratio. were valid due to a rollover between successive reads
Clearing bit PSA will assign the prescaler to the Timer0 of the high and low byte.
module. When the prescaler is assigned to the Timer0 A write to the high byte of Timer0 must also take place
module, prescale values of 1:2, 1:4,..., 1:256 are through the TMR0H buffer register. Timer0 high byte is
selectable. updated with the contents of TMR0H when a write
When assigned to the Timer0 module, all instructions occurs to TMR0L. This allows all 16-bits of Timer0 to be
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF updated at once.
TMR0, BSF TMR0, x....etc.) will clear the prescaler
count.
Note: Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
TMR0L Timer0 Module Low Byte Register xxxx xxxx uuuu uuuu
TMR0H Timer0 Module High Byte Register 0000 0000 0000 0000
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 1111 1111
TRISA — PORTA Data Direction Register -111 1111 -111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
TMR1H
8
8
Write TMR1L
CCP Special Event Trigger
Read TMR1L
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
Value on
Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR, BOR
RESETS
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Sets Flag
TMR2
Output(1) bit TMR2IF
Prescaler RESET
FOSC/4 TMR2
1:1, 1:4, 1:16
2 Postscaler
Comparator
EQ 1:1 to 1:16
T2CKPS1:T2CKPS0
PR2 4
TOUTPS3:TOUTPS0
Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock.
Value on
Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR, BOR
RESETS
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
TMR2 Timer2 Module Register 0000 0000 0000 0000
T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
PR2 Timer2 Period Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
T1OSC (3)
T1OSO/
T13CKI 1
Synchronize
Prescaler
T1OSCEN FOSC/4 1, 2, 4, 8 det
Enable Internal 0
T1OSI Oscillator(1) Clock 2
TMR3CS SLEEP Input
T3CKPS1:T3CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
TMR3H
8
8
Write TMR3L
Read TMR3L
CCP Special Trigger
8 T3CCPx Synchronized
Set TMR3IF Flag bit TMR3 0
on Overflow Timer3 CLR Clock Input
High Byte TMR3L
1
To Timer1 Clock Input TMR3ON
On/Off T3SYNC
T1OSC
T1OSO/
T13CKI 1
Synchronize
Prescaler
T1OSCEN FOSC/4 1, 2, 4, 8 det
Enable Internal 0
T1OSI Oscillator(1) Clock 2 SLEEP Input
T3CKPS1:T3CKPS0
TMR3CS
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
Value on Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other
BOR RESETS
GIE/ PEIE/
INTCON TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
GIEH GIEL
PIR2 — — — EEIF BCLIF LVDIF TMR3IF CCP2IF ---0 0000 ---0 0000
PIE2 — — — EEIE BCLIE LVDIE TMR3IE CCP2IE ---0 0000 ---0 0000
IPR2 — — — EEIP BCLIP LVDIP TMR3IP CCP2IP ---1 1111 ---1 1111
TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu
TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu
T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Capture Capture TMR1 or TMR3 time-base. Time-base can be different for each CCP.
The compare could be configured for the special event trigger,
Capture Compare
which clears either TMR1 or TMR3 depending upon which time-base is used.
The compare(s) could be configured for the special event trigger,
Compare Compare
which clears TMR1 or TMR3 depending upon which time-base is used.
PWM PWM The PWMs will have the same frequency and update rate
(TMR2 interrupt).
PWM Capture None
PWM Compare None
TMR1
and T3CCP2 Enable
Edge Detect
TMR1H TMR1L
CCP1CON<3:0>
Q’s
and TMR1
Enable
Edge Detect
T3CCP2
T3CCP1 TMR1H TMR1L
CCP2CON<3:0>
Q’s
Q S Output
Logic Comparator
RC2/CCP1 pin R Match
TRISC<2>
Output Enable CCP1CON<3:0> T3CCP2 0 1
Mode Select
Q S Output Comparator
RC1/CCP2 pin Logic Match
R
TRISC<1> CCPR2H CCPR2L
Output Enable CCP2CON<3:0>
Mode Select
Value on Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other
BOR RESETS
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
(1)
PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
TRISC PORTC Data Direction Register 1111 1111 1111 1111
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu
CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu
CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
PIR2 — — — EEIE BCLIF LVDIF TMR3IF CCP2IF ---0 0000 ---0 0000
PIE2 — — — EEIF BCLIE LVDIE TMR3IE CCP2IE ---0 0000 ---0 0000
IPR2 — — — EEIP BCLIP LVDIP TMR3IP CCP2IP ---1 1111 ---1 1111
TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu
TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2x2 devices; always maintain these bits clear.
log ---------------
F OSC
F PWM
PWM Resolution (max) = -----------------------------bits
log ( 2 )
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
TMR2 = PR2 cleared.
PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16) 16 4 1 1 1 1
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 14 12 10 8 7 6.58
Value on Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other
BOR RESETS
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
TRISC PORTC Data Direction Register 1111 1111 1111 1111
TMR2 Timer2 Module Register 0000 0000 0000 0000
PR2 Timer2 Module Period Register 1111 1111 1111 1111
T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu
CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu
CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear.
• Serial Peripheral Interface (SPI) Figure 15-1 shows the block diagram of the MSSP
module when operating in SPI mode.
• Inter-Integrated Circuit (I2C)
- Full Master mode
FIGURE 15-1: MSSP BLOCK DIAGRAM
- Slave mode (with general address call) (SPI MODE)
The I2C interface supports the following modes in hard- Internal
ware: Data Bus
• Master mode Read Write
• Multi-Master mode
• Slave mode SSPBUF reg
Edge
Select
2
Clock Select
SSPM3:SSPM0
SMP:CKE 4
RC3/SCK/
SCL/LVDIN 2 (
TMR2 output
2
)
Edge
Select Prescaler TOSC
4, 16, 64
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
SDO SDI
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
SCK Modes
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Input
Sample
(SMP = 1)
SSPIF
Next Q4 cycle
SSPSR to after Q2↓
SSPBUF
The SS pin allows a Synchronous Slave mode. The To emulate two-wire communication, the SDO pin can
SPI must be in Slave mode with SS pin control be connected to the SDI pin. When the SPI needs to
enabled (SSPCON1<3:0> = 04h). The pin must not operate as a receiver the SDO pin can be configured as
be driven low for the SS pin to function as an input. an input. This disables transmissions from the SDO.
The Data Latch must be high. When the SS pin is The SDI can always be left as an input (SDI function),
low, transmission and reception are enabled and since it cannot create a bus conflict.
the SDO pin is driven. When the SS pin goes high,
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDI bit0
(SMP = 0) bit7 bit7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
SSPSR to after Q2↓
SSPBUF
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDI
(SMP = 0) bit7 bit0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
SSPSR to after Q2↓
SSPBUF
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
SDI
(SMP = 0) bit7 bit0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2↓
SSPSR to
SSPBUF
INTCON GIE/GIEH PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
GIEL
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
TRISC PORTC Data Direction Register 1111 1111 1111 1111
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
TRISA — PORTA Data Direction Register --11 1111 --11 1111
SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the MSSP in SPI mode.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices; always maintain these bits clear.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE
mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
15.4.3.3 Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3/SCK/SCL is held
low, regardless of SEN (see “Clock Stretching”,
Section 15.4.4, for more detail). By stretching the clock,
the master will be unable to assert another clock pulse
until the slave is done preparing the transmit data.The
transmit data must be loaded into the SSPBUF register,
which also loads the SSPSR register. Then pin RC3/
SCK/SCL should be enabled by setting bit CKP
(SSPCON1<4>). The eight data bits are shifted out on
the falling edge of the SCL input. This ensures that the
SDA signal is valid during the SCL high time
(Figure 15-9).
DS39564A-page 138
PIC18FXX2
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPIF
Bus Master
(PIR1<3>) terminates
transfer
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
Advance Information
SSPOV (SSPCON<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
Data in SCL held low P
sampled while CPU
responds to SSPIF
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
Cleared in software Cleared in software
From SSPIF ISR From SSPIF ISR
SSPBUF is written in software SSPBUF is written in software
Advance Information
CKP
I2C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
DS39564A-page 139
PIC18FXX2
FIGURE 15-10:
DS39564A-page 140
Clock is held low until Clock is held low until
update of SSPADD has update of SSPADD has
taken place taken place
Receive First Byte of Address Receive Second Byte of Address Receive Data Byte Receive Data Byte
R/W = 0 ACK
PIC18FXX2
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
Bus Master
terminates
SSPIF transfer
(PIR1<3>)
Cleared in software Cleared in software Cleared in software
Cleared in software
BF (SSPSTAT<0>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
Advance Information
UA (SSPSTAT<1>)
Bus Master
terminates
Clock is held low until Clock is held low until transfer
update of SSPADD has update of SSPADD has Clock is held low until
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S Sr P
SSPIF
(PIR1<3>)
Cleared in software Cleared in software Cleared in software
BF (SSPSTAT<0>)
Advance Information
UA is set indicating that Cleared by hardware when Cleared by hardware when
the SSPADD needs to be SSPADD is updated with low SSPADD is updated with high
updated byte of address byte of address.
DS39564A-page 141
PIC18FXX2
PIC18FXX2
15.4.4 CLOCK STRETCHING 15.4.4.3 Clock Stretching for 7-bit Slave
Transmit Mode
Both 7- and 10-bit Slave modes implement automatic
clock stretching during a transmit sequence. 7-bit Slave Transmit mode implements clock stretching
by clearing the CKP bit after the falling edge of the
The SEN bit (SSPCON2<0>) allows clock stretching to
ninth clock, if the BF bit is clear. This occurs, regard-
be enabled during receives. Setting SEN will cause
less of the state of the SEN bit.
the SCL pin to be held low at the end of each data
receive sequence. The user’s ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCL line
15.4.4.1 Clock Stretching for 7-bit Slave low, the user has time to service the ISR and load the
Receive Mode (SEN = 1) contents of the SSPBUF before the master device can
In 7-bit Slave Receive mode, on the falling edge of the initiate another transmit sequence (see Figure 15-9).
ninth clock at the end of the ACK sequence, if the BF Note 1: If the user loads the contents of SSPBUF,
bit is set, the CKP bit in the SSPCON1 register is auto- setting the BF bit before the falling edge of
matically cleared, forcing the SCL output to be held the ninth clock, the CKP bit will not be
low. The CKP being cleared to ‘0’ will assert the SCL cleared and clock stretching will not occur.
line low. The CKP bit must be set in the user’s ISR
2: The CKP bit can be set in software,
before reception is allowed to continue. By holding the
regardless of the state of the BF bit.
SCL line low, the user has time to service the ISR and
read the contents of the SSPBUF before the master 15.4.4.4 Clock Stretching for 10-bit Slave
device can initiate another receive sequence. This will
Transmit Mode
prevent buffer overruns from occurring (see
Figure 15-13). In 10-bit Slave Transmit mode, clock stretching is con-
trolled during the first two address sequences by the
Note 1: If the user reads the contents of the state of the UA bit, just as it is in 10-bit Slave Receive
SSPBUF before the falling edge of the mode. The first two addresses are followed by a third
ninth clock, thus clearing the BF bit, the address sequence, which contains the high order bits
CKP bit will not be cleared and clock of the 10-bit address and the R/W bit set to ‘1’. After
stretching will not occur. the third address sequence is performed, the UA bit is
2: The CKP bit can be set in software, not set, the module is now configured in transmit
regardless of the state of the BF bit. The mode, and clock stretching is controlled by the BF flag,
user should be careful to clear the BF bit as in 7-bit Slave Transmit mode (see Figure 15-11).
in the ISR before the next receive
sequence, in order to prevent an overflow
condition.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA DX DX-1
SCL
Master device
CKP asserts clock
Master device
de-asserts clock
WR
SSPCON
DS39564A-page 144
Clock is not held low
PIC18FXX2
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPIF
Bus Master
(PIR1<3>) terminates
transfer
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
Advance Information
SSPOV (SSPCON<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
CKP
CKP
If BF is cleared written
prior to the falling to ‘1’ in
edge of the 9th clock, software
CKP will not be reset BF is set after falling
to ‘0’ and no clock edge of the 9th clock,
stretching will occur CKP is reset to ‘0’ and
clock stretching occurs
I2C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION 7-BIT ADDRESS)
SSPIF
Bus Master
(PIR1<3>) terminates
Cleared in software Cleared in software Cleared in software transfer
Cleared in software
BF (SSPSTAT<0>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
UA (SSPSTAT<1>)
Advance Information
UA is set indicating that Cleared by hardware when Cleared by hardware when
the SSPADD needs to be SSPADD is updated with low SSPADD is updated with high
updated byte of address after falling edge byte of address after falling edge
of ninth clock. of ninth clock.
DS39564A-page 145
PIC18FXX2
PIC18FXX2
15.4.5 GENERAL CALL ADDRESS If the general call address matches, the SSPSR is
SUPPORT transferred to the SSPBUF, the BF flag bit is set (eighth
bit), and on the falling edge of the ninth bit (ACK bit),
The addressing procedure for the I2C bus is such that the SSPIF interrupt flag bit is set.
the first byte after the START condition usually deter-
mines which device will be the slave addressed by the When the interrupt is serviced, the source for the inter-
master. The exception is the general call address, rupt can be checked by reading the contents of the
which can address all devices. When this address is SSPBUF. The value can be used to determine if the
used, all devices should, in theory, respond with an address was device specific or a general call address.
Acknowledge. In 10-bit mode, the SSPADD is required to be updated
The general call address is one of eight addresses for the second half of the address to match, and the UA
reserved for specific purposes by the I2C protocol. It bit is set (SSPSTAT<1>). If the general call address is
consists of all 0’s with R/W = 0. sampled when the GCEN bit is set, while the slave is
configured in 10-bit Address mode, then the second
The general call address is recognized when the Gen- half of the address is not necessary, the UA bit will not
eral Call Enable bit (GCEN) is enabled (SSPCON2<7> be set, and the slave will begin receiving data after the
set). Following a START bit detect, 8-bits are shifted Acknowledge (Figure 15-15).
into the SSPSR and the address is compared against
the SSPADD. It is also compared to the general call
address and fixed in hardware.
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
SSPIF
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV (SSPCON1<6>) ’0’
Internal SSPM3:SSPM0
Data Bus SSPADD<6:0>
Read Write
SSPBUF Baud
Rate
Generator
SDA Shift
Clock Arbitrate/WCOL Detect
SDA in Clock
SSPSR
(hold off clock source)
MSb LSb
Receive Enable
Acknowledge
Generate
SCL
SSPM3:SSPM0 SSPADD<6:0>
FSCL
FCY FCY*2 BRG VALUE
(2 rollovers of BRG)
Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
SDA DX DX-1
BRG decrements on
Q2 and Q4 cycles
BRG
03h 02h 01h 00h (hold off) 03h 02h
Value
SCL
TBRG
S
Set S (SSPSTAT<3>)
Write to SSPCON2
SDA = 1,
occurs here. At completion of START bit,
SDA = 1, SCL = 1
hardware clear RSEN bit
SCL (no change) and set SSPIF
1st bit
SDA
Falling edge of ninth clock Write to SSPBUF occurs here
End of Xmit
TBRG
SCL TBRG
Sr = Repeated START
DS39564A-page 154
Write SSPCON2<0> SEN = 1 ACKSTAT in
START condition begins SSPCON2 = 1
From slave clear ACKSTAT bit SSPCON2<6>
PIC18FXX2
SEN = 0
Transmitting Data or Second Half
Transmit Address to Slave R/W = 0 of 10-bit Address ACK
SDA A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0
BF (SSPSTAT<0>)
Advance Information
SEN
PEN
R/W
I 2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
Write to SSPCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
Write to SSPCON2<0> (SEN = 1)
Begin START Condition ACK from Master Set ACKEN, start Acknowledge sequence
Master configured as a receiver SDA = ACKDT = 0 SDA = ACKDT = 1
SEN = 0 by programming SSPCON2<3>, (RCEN = 1)
Bus Master
ACK is not sent terminates
transfer
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL S P
Data shifted in on falling edge of CLK Set SSPIF at end
of receive Set SSPIF interrupt
Set SSPIF interrupt at end of Acknow-
Set SSPIF interrupt ledge sequence
at end of receive
at end of Acknowledge
SSPIF sequence
Set P bit
Cleared in software Cleared in software Cleared in software Cleared in software (SSPSTAT<4>)
SDA = 0, SCL = 1 Cleared in
while CPU software and SSPIF
responds to SSPIF
Advance Information
BF
(SSPSTAT<0>) Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
SSPOV
ACKEN
I 2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
DS39564A-page 155
PIC18FXX2
PIC18FXX2
15.4.12 ACKNOWLEDGE SEQUENCE 15.4.13 STOP CONDITION TIMING
TIMING
A STOP bit is asserted on the SDA pin at the end of a
An Acknowledge sequence is enabled by setting the receive/transmit by setting the STOP sequence enable
Acknowledge sequence enable bit, ACKEN bit, PEN (SSPCON2<2>). At the end of a receive/trans-
(SSPCON2<4>). When this bit is set, the SCL pin is mit the SCL line is held low after the falling edge of the
pulled low and the contents of the Acknowledge data bit ninth clock. When the PEN bit is set, the master will
are presented on the SDA pin. If the user wishes to gen- assert the SDA line low. When the SDA line is sampled
erate an Acknowledge, then the ACKDT bit should be low, the baud rate generator is reloaded and counts
cleared. If not, the user should set the ACKDT bit before down to 0. When the baud rate generator times out, the
starting an Acknowledge sequence. The baud rate gen- SCL pin will be brought high, and one TBRG (baud rate
erator then counts for one rollover period (TBRG) and the generator rollover count) later, the SDA pin will be
SCL pin is de-asserted (pulled high). When the SCL pin de-asserted. When the SDA pin is sampled high while
is sampled high (clock arbitration), the baud rate gener- SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG
ator counts for TBRG. The SCL pin is then pulled low. Fol- later, the PEN bit is cleared and the SSPIF bit is set
lowing this, the ACKEN bit is automatically cleared, the (Figure 15-24).
baud rate generator is turned off and the MSSP module
then goes into IDLE mode (Figure 15-23). 15.4.13.1 WCOL Status Flag
If the user writes the SSPBUF when a STOP sequence
15.4.12.1 WCOL Status Flag is in progress, then the WCOL bit is set and the con-
If the user writes the SSPBUF when an Acknowledge tents of the buffer are unchanged (the write doesn’t
sequence is in progress, then WCOL is set and the con- occur).
tents of the buffer are unchanged (the write doesn’t occur).
TBRG TBRG
SDA D0 ACK
SCL 8 9
SSPIF
Cleared in
Set SSPIF at the end Cleared in software
of receive software Set SSPIF at the end
of Acknowledge sequence
Note: TBRG = one baud rate generator period.
SDA ACK
P
TBRG TBRG TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup STOP condition.
In multi-master operation, the SDA line must be moni- If a START, Repeated START, STOP, or Acknowledge
tored for arbitration, to see if the signal level is the condition was in progress when the bus collision
expected output level. This check is performed in hard- occurred, the condition is aborted, the SDA and SCL
ware, with the result placed in the BCLIF bit. lines are de-asserted, and the respective control bits in
the SSPCON2 register are cleared. When the user ser-
The states where arbitration can be lost are: vices the bus collision Interrupt Service Routine, and if
• Address Transfer the I2C bus is free, the user can resume communication
• Data Transfer by asserting a START condition.
• A START Condition The master will continue to monitor the SDA and SCL
• A Repeated START Condition pins. If a STOP condition occurs, the SSPIF bit will be set.
• An Acknowledge Condition A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the I2C
bus can be taken when the P bit is set in the SSPSTAT reg-
ister, or the bus is IDLE and the S and P bits are cleared.
SDA
BCLIF
SDA
SCL
Set SEN, enable START SEN cleared automatically because of bus collision.
condition if SDA = 1, SCL=1 SSP module reset into IDLE state.
SEN
SDA sampled low before
START condition. Set BCLIF.
S bit and SSPIF set because
BCLIF SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared in software.
SSPIF
TBRG TBRG
SDA
FIGURE 15-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S Set SSPIF
Less than TBRG
TBRG
SCL S
SCL pulled low after BRG
Time-out
SEN
Set SEN, enable START
sequence if SDA = 1, SCL = 1
BCLIF ’0’
SSPIF
SDA = 0, SCL = 1 Interrupts cleared
Set SSPIF in software
SDA
SCL
RSEN
BCLIF
Cleared in software
S '0'
SSPIF '0'
TBRG TBRG
SDA
SCL
S ’0’
SSPIF
PEN
BCLIF
P ’0’
SSPIF ’0’
SDA
PEN
BCLIF
P ’0’
SSPIF ’0’
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x
SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.
0.3 NA — — NA — — NA — — NA — —
1.2 NA — — 1.221 +1.73 255 1.202 +0.16 207 1.202 +0.16 129
2.4 2.441 -1.70 255 2.404 +0.16 129 2.404 +0.16 103 2.404 +0.16 64
9.6 9.615 -0.16 64 9.469 -1.36 32 9.615 +0.16 25 9.766 +1.73 15
19.2 18.94 +1.38 32 19.53 +1.73 15 19.23 +0.16 12 19.53 +1.73 7
76.8 78.13 -1.70 7 78.13 +1.73 3 83.33 +8.51 2 78.13 +1.73 1
96 89.29 +7.52 6 104.2 +8.51 2 NA — — NA — —
300 312.5 -4.00 1 312.5 +4.17 0 NA — — NA — —
500 625.0 -20.0 0 NA — — NA — — NA — —
HIGH 2.441 — 255 312.5 — 0 250 — 0 156.3 — 0
LOW 625.0 — 0 1.221 — 255 0.977 — 255 0.6104 — 255
FOSC = 7.15909 MHz FOSC = 5.0688 MHz FOSC = 4 MHz FOSC = 3.579545 MHz
BAUD
RATE Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG
% % % %
(K) Rate value Rate value Rate value Rate value
Error Error Error Error
(K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal)
0.3 NA — — 0.31 +3.13 255 0.3005 -0.17 207 0.301 +0.23 185
1.2 1.203 +0.23 92 1.2 0 65 1.202 +1.67 51 1.190 -0.83 46
2.4 2.380 -0.83 46 2.4 0 32 2.404 +1.67 25 2.432 +1.32 22
9.6 9.322 -2.90 11 9.9 +3.13 7 NA — — 9.322 -2.90 5
19.2 18.64 -2.90 5 19.8 +3.13 3 NA — — 18.64 -2.90 2
76.8 NA — — 79.2 +3.13 0 NA — — NA — —
96 NA — — NA — — NA — — NA — —
300 NA — — NA — — NA — — NA — —
500 NA — — NA — — NA — — NA — —
HIGH 111.9 — 0 79.2 — 0 62.500 — 0 55.93 — 0
LOW 0.437 — 255 0.3094 — 255 3.906 — 255 0.2185 — 255
9.6 9.766 -1.70 255 9.615 +0.16 129 9.615 +0.16 103 9.615 +0.16 64
19.2 19.231 -0.16 129 19.230 +0.16 64 19.230 +0.16 51 18.939 -1.36 32
38.4 38.461 -0.16 64 37.878 -1.36 32 38.461 +0.16 25 39.062 +1.7 15
57.6 58.139 -0.93 42 56.818 -1.36 21 58.823 +2.12 16 56.818 -1.36 10
115.2 113.64 1.38 21 113.63 -1.36 10 111.11 -3.55 8 125 +8.51 4
250 250 0 9 250 0 4 250 0 3 NA — —
625 625 0 3 625 0 1 NA — — 625 0 0
1250 1250 0 1 1250 0 0 NA — — NA — —
FOSC = 7.16MHz FOSC = 5.068 MHz FOSC = 4 MHz FOSC = 3.579545 MHz
BAUD
RATE Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG
% % % %
(K) Rate value Rate value Rate value Rate value
Error Error Error Error
(K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal)
SPBRG
TX9
Baud Rate Generator
TX9D
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
START bit bit 0 bit 1 bit 7/8 STOP bit
Word 1
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
Word 1
TRMT bit Transmit Shift Reg
(Transmit Shift
Reg. Empty Flag)
Write to TXREG
Word 1 Word 2
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
START bit bit 0 bit 1 bit 7/8 STOP bit START bit bit 0
TXIF bit
(Interrupt Reg. Flag) Word 1 Word 2
Value on Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other
BOR RESETS
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x
TXREG USART Transmit Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'.
Shaded cells are not used for Asynchronous Transmission.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits
clear.
RX9
RC7/RX/DT
Pin Buffer Data
and Control Recovery
RX9D RCREG Register
FIFO
SPEN
8
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, caus-
ing the OERR (overrun) bit to be set.
Value on Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other
BOR RESETS
INTCON GIE/GIEH PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
GIEL
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x
RCREG USART Receive Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'.
Shaded cells are not used for Asynchronous Reception.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits
clear.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
’1’ ’1’
TXEN bit
Note: Sync Master mode; SPBRG = ’0’. Continuous transmission of two 8-bit words.
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7
RC6/TX/CK pin
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = ’1’ and bit BRGH = ’0’.
Synchronous Slave mode differs from the Master mode 1. Enable the synchronous slave serial port by set-
in the fact that the shift clock is supplied externally at ting bits SYNC and SPEN and clearing bit
the RC6/TX/CK pin (instead of being supplied internally CSRC.
in Master mode). This allows the device to transfer or 2. Clear bits CREN and SREN.
receive data while in SLEEP mode. Slave mode is 3. If interrupts are desired, set enable bit TXIE.
entered by clearing bit CSRC (TXSTA<7>). 4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting enable bit
16.4.1 USART SYNCHRONOUS SLAVE
TXEN.
TRANSMIT
6. If 9-bit transmission is selected, the ninth bit
The operation of the Synchronous Master and Slave should be loaded in bit TX9D.
modes are identical, except in the case of the SLEEP 7. Start transmission by loading data to the TXREG
mode. register.
If two words are written to the TXREG and then the 8. If using interrupts, ensure that the GIE and PEIE
SLEEP instruction is executed, the following will occur: bits in the INTCON register (INTCON<7:6>) are
a) The first word will immediately transfer to the set.
TSR register and transmit.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
Value on Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other
BOR RESETS
INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
GIEH GIEL
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x
RCREG USART Receive Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as '0'.
Shaded cells are not used for Synchronous Slave Reception.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits
clear.
bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits (ADCON0 bits in bold)
ADCON1 ADCON0
Clock Conversion
<ADCS2> <ADCS1:ADCS0>
0 00 FOSC/2
0 01 FOSC/8
0 10 FOSC/32
0 11 FRC (clock derived from the internal A/D RC oscillator)
1 00 FOSC/4
1 01 FOSC/16
1 10 FOSC/64
1 11 FRC (clock derived from the internal A/D RC oscillator)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
ADCON1 ADCON0
Clock Conversion
<ADCS2> <ADCS1:ADCS0>
0 00 FOSC/2
0 01 FOSC/8
0 10 FOSC/32
0 11 FRC (clock derived from the internal A/D RC oscillator)
1 00 FOSC/4
1 01 FOSC/16
1 10 FOSC/64
1 11 FRC (clock derived from the internal A/D RC oscillator)
PCFG
AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VREF+ VREF- C/R
<3:0>
0000 A A A A A A A A VDD VSS 8/0
0001 A A A A VREF+ A A A AN3 VSS 7/1
0010 D D D A A A A A VDD VSS 5/0
0011 D D D A VREF+ A A A AN3 VSS 4/1
0100 D D D D A D A A VDD VSS 3/0
0101 D D D D VREF+ D A A AN3 VSS 2/1
011x D D D D D D D D — — 0/0
1000 A A A A VREF+ VREF- A A AN3 AN2 6/2
1001 D D A A A A A A VDD VSS 6/0
1010 D D A A VREF+ A A A AN3 VSS 5/1
1011 D D A A VREF+ VREF- A A AN3 AN2 4/2
1100 D D D A VREF+ VREF- A A AN3 AN2 3/2
1101 D D D D VREF+ VREF- A A AN3 AN2 2/2
1110 D D D D D D D A VDD VSS 1/0
1111 D D D D VREF+ VREF- D A AN3 AN2 1/2
A = Analog input D = Digital I/O
C/R = # of analog input channels / # of A/D voltage references
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Note: On any device RESET, the port pins that are multiplexed with analog functions (ANx) are
forced to be an analog input.
111
AN7*
110
AN6*
101
AN5*
100
AN4
VAIN
(Input Voltage) 011
AN3
010
10-bit AN2
Converter
A/D 001
AN1
PCFG0 000
VDD AN0
VREF+
Reference
Voltage
VREF-
VSS
CPIN I LEAKAGE
VAIN CHOLD = 120 pF
5 pF VT = 0.6V ± 500 nA
VSS
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b0
Conversion Starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
17.4.1 A/D RESULT REGISTERS Format Select bit (ADFM) controls this justification.
Figure 17-4 shows the operation of the A/D result justi-
The ADRESH:ADRESL register pair is the location fication. The extra bits are loaded with ’0’s. When an
where the 10-bit A/D result is loaded at the completion A/D result will not overwrite these locations (A/D
of the A/D conversion. This register pair is 16-bits wide. disable), these registers may be used as two general
The A/D module gives the flexibility to left or right justify purpose 8-bit registers.
the 10-bit result in the 16-bit result register. The A/D
10-bit Result
ADFM = 1 ADFM = 0
7 2107 0 7 0765 0
0000 00 0000 00
Value on
Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR, BOR
RESETS
GIE/ PEIE/
INTCON TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
GIEH GIEL
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
(1)
PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
PIR2 — — — EEIF BCLIF LVDIF TMR3IF CCP2IF ---0 0000 ---0 0000
PIE2 — — — EEIE BCLIE LVDIE TMR3IE CCP2IE ---0 0000 ---0 0000
IPR2 — — — EEIP BCLIP LVDIP TMR3IP CCP2IP ---1 1111 ---1 0000
ADRESH A/D Result Register xxxx xxxx uuuu uuuu
ADRESL A/D Result Register xxxx xxxx uuuu uuuu
ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/ — ADON 0000 00-0 0000 00-0
DONE
ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
PORTA — RA6 RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
TRISA — PORTA Data Direction Register --11 1111 --11 1111
PORTE — — — — — RE2 RE1 RE0 ---- -000 ---- -000
LATE — — — — — LATE2 LATE1 LATE0 ---- -xxx ---- -uuu
TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear.
VA
VB
Voltage
Legend:
VA = LVD trip point
VB = Minimum valid device
operating voltage
TA TB
Time
The block diagram for the LVD module is shown in supply voltage is equal to the trip point, the voltage
Figure 18-2. A comparator uses an internally gener- tapped off of the resistor array is equal to the 1.2V
ated reference voltage as the set point. When the internal reference voltage generated by the voltage
selected tap output of the device voltage crosses the reference module. The comparator then generates an
set point (is lower than), the LVDIF bit is set. interrupt signal setting the LVDIF bit. This voltage is
Each node in the resistor divider represents a “trip software programmable to any one of 16 values (see
point” voltage. The “trip point” voltage is the minimum Figure 18-2). The trip point is selected by program-
supply voltage level at which the device can operate ming the LVDL3:LVDL0 bits (LVDCON<3:0>).
before the LVD module asserts an interrupt. When the
VDD LVDIN
LVD Control
Register
16 to 1 MUX
LVDIF
The LVD module has an additional feature that allows LVDIN (Figure 18-3). This gives users flexibility,
the user to supply the trip voltage to the module from because it allows them to configure the Low Voltage
an external source. This mode is enabled when bits Detect interrupt to occur at any voltage in the valid
LVDL3:LVDL0 are set to 1111. In this state, the com- operating range.
parator input is multiplexed from the external input pin,
FIGURE 18-3: LOW VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM
VDD
VDD
LVD Control
Register
16 to 1 MUX
LVDIN LVDEN
Externally Generated
Trip Point
LVD
VxEN
BODEN
EN
BGAP
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
VDD
.
VLVD
LVDIF
Enable LVD
CASE 2:
VDD
VLVD
LVDIF
Enable LVD
Default/
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed
Value
300001h CONFIG1H — — OSCSEN — — FOSC2 FOSC1 FOSC0 --1- -111
300002h CONFIG2L — — — — BORV1 BORV0 BODEN PWRTEN ---- 1111
300003h CONFIG2H — — — — WDTPS2 WDTPS1 WDTPS0 WDTEN ---- 1111
300005h CONFIG3H — — — — — — — CCP2MX ---- ---1
300006h CONFIG4L DEBUG — — — — LVP — STVREN 1--- -1-1
300008h CONFIG5L — — — — CP3 CP2 CP1 CP0 ---- 1111
300009h CONFIG5H CPD CPB — — — — — — 11-- ----
30000Ah CONFIG6L — — — — WRT3 WRT2 WRT1 WRT0 ---- 1111
30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 111- ----
30000Ch CONFIG7L — — — — EBTR3 EBTR2 EBTR1 EBTR0 ---- 1111
30000Dh CONFIG7H — EBTRB — — — — — — -1-- ----
3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 (1)
3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 0100
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition.
Shaded cells are unimplemented, read as ‘0’.
Note 1: See Register 19-14 for DEVID1 values.
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit P =Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit P =Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit P =Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit P =Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
19.2 Watchdog Timer (WDT) The WDT time-out period values may be found in the
Electrical Specifications section under parameter #31.
The Watchdog Timer is a free running on-chip RC oscil- Values for the WDT postscaler may be assigned using
lator, which does not require any external components. the configuration bits.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKI pin. That means that the WDT will run, Note: The CLRWDT and SLEEP instructions clear
even if the clock on the OSC1/CLKI and OSC2/CLKO/ the WDT and the postscaler, if assigned to
RA6 pins of the device has been stopped, for example, the WDT and prevent it from timing out and
by execution of a SLEEP instruction. generating a device RESET condition.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
Note: When a CLRWDT instruction is executed
in SLEEP mode, a WDT time-out causes the device to
and the postscaler is assigned to the WDT,
wake-up and continue with normal operation (Watch-
the postscaler count will be cleared, but the
dog Timer Wake-up). The TO bit in the RCON register
postscaler assignment is not changed.
will be cleared upon a WDT time-out.
The Watchdog Timer is enabled/disabled by a device 19.2.1 CONTROL REGISTER
configuration bit. If the WDT is enabled, software exe-
cution may not disable this function. When the WDTEN Register 19-14 shows the WDTCON register. This is a
configuration bit is cleared, the SWDTEN bit enables/ readable and writable register, which contains a control
disables the operation of the WDT. bit that allows software to override the WDT enable
configuration bit, only when the configuration bit has
disabled the WDT.
Legend:
R = Readable bit W = Writable bit
U = Unimplemented bit, read as ‘0’ - n = Value at POR reset
8 - to - 1 MUX WDTPS2:WDTPS0
WDT
Time-out
Note: WDPS2:WDPS0 are bits in register CONFIG2H.
19.3 Power-down Mode (SLEEP) External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
Power-down mode is entered by executing a SLEEP execution and will cause a “wake-up”. The TO and PD
instruction. bits in the RCON register can be used to determine the
If enabled, the Watchdog Timer will be cleared, but cause of the device RESET. The PD bit, which is set on
keeps running, the PD bit (RCON<3>) is cleared, the power-up, is cleared when SLEEP is invoked. The TO
TO (RCON<4>) bit is set, and the oscillator driver is bit is cleared, if a WDT time-out occurred (and caused
turned off. The I/O ports maintain the status they had wake-up).
before the SLEEP instruction was executed (driving When the SLEEP instruction is being executed, the next
high, low or hi-impedance). instruction (PC + 2) is pre-fetched. For the device to
For lowest current consumption in this mode, place all wake-up through an interrupt event, the corresponding
I/O pins at either VDD or VSS, ensure no external cir- interrupt enable bit must be set (enabled). Wake-up is
cuitry is drawing current from the I/O pin, power-down regardless of the state of the GIE bit. If the GIE bit is
the A/D and disable external clocks. Pull all I/O pins clear (disabled), the device continues execution at the
that are hi-impedance inputs, high or low externally, to instruction after the SLEEP instruction. If the GIE bit is
avoid switching currents caused by floating inputs. The set (enabled), the device executes the instruction after
T0CKI input should also be at VDD or VSS for lowest the SLEEP instruction and then branches to the inter-
current consumption. The contribution from on-chip rupt address. In cases where the execution of the
pull-ups on PORTB should be considered. instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
The MCLR pin must be at a logic high level (VIHMC).
INT pin
INTF flag
(INTCON<1>) Interrupt Latency(3)
GIEH bit
(INTCON<7>) Processor in
SLEEP
INSTRUCTION FLOW
PC PC PC+2 PC+4 PC+4 PC + 4 0008h 000Ah
Instruction Inst(PC + 2) Inst(PC + 4) Inst(0008h) Inst(000Ah)
Fetched Inst(PC) = SLEEP
Instruction Inst(PC + 2) Dummy Cycle Dummy Cycle Inst(0008h)
Executed Inst(PC - 1) SLEEP
000000h
Boot Block Boot Block CPB, WRTB, EBTRB
0001FFh
000200h
Block 0 Block 0 CP0, WRT0, EBTR0
001FFFh
002000h
Block 1 Block 1 CP1, WRT1, EBTR1
003FFFh
004000h
Unimplemented
Block 2 CP2, WRT2, EBTR2
Read 0s
005FFFh
006000h
Unimplemented
Block 3 CP3, WRT3, EBTR3
Read 0s
007FFFh
008000h
Unimplemented Unimplemented
Read 0s Read 0s (Unimplemented Memory Space)
1FFFFFh
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
300008h CONFIG5L — — — — CP3 CP2 CP1 CP0
300009h CONFIG5H CPD CPB — — — — — —
30000Ah CONFIG6L — — — — WRT3 WRT2 WRT1 WRT0
30000Bh CONFIG6H WRTD WRTB WRTC — — — — —
30000Ch CONFIG7L — — — — EBTR3 EBTR2 EBTR1 EBTR0
30000Dh CONFIG7H — EBTRB — — — — — —
Legend: Shaded cells are unimplemented.
TBLPTR = 000FFF
WRT0,EBTR0 = 01
007FFFh
000000h
WRTB,EBTRB = 11
0001FFh
000200h
TBLPTR = 000FFF
WRT0,EBTR0 = 10
001FFFh
002000h
PC = 002FFE TBLRD * WRT1,EBTR1 = 11
003FFFh
004000h
WRT2,EBTR2 = 11
005FFFh
006000h
WRT3,EBTR3 = 11
007FFFh
Results: All Table Reads from external blocks to Blockn are disabled whenever EBTRn = ‘0’.
TABLAT register returns a value of “0”.
007FFFh
Results: Table Reads permitted within Blockn, even when EBTRBn = ‘0’.
TABLAT register returns the value of the data at the location TBLPTR.
Field Description
a RAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb Bit address within an 8-bit file register (0 to 7)
BSR Bank Select Register. Used to select the current RAM bank.
d Destination select bit;
d = 0: store result in WREG,
d = 1: store result in file register f.
dest Destination either the WREG register or the specified register file location
f 8-bit Register file address (0x00 to 0xFF)
fs 12-bit Register file address (0x000 to 0xFFF). This is the source address.
fd 12-bit Register file address (0x000 to 0xFFF). This is the destination address.
k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value)
label Label name
mm The mode of the TBLPTR register for the Table Read and Table Write instructions
Only used with Table Read and Table Write instructions:
* No Change to register (such as TBLPTR with Table reads and writes)
*+ Post-Increment register (such as TBLPTR with Table reads and writes)
*- Post-Decrement register (such as TBLPTR with Table reads and writes)
+* Pre-Increment register (such as TBLPTR with Table reads and writes)
n The relative address (2’s complement number) for relative branch instructions, or the direct address for Call/
Branch and Return instructions
PRODH Product of Multiply high byte
PRODL Product of Multiply low byte
s Fast Call / Return mode select bit.
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
u Unused or Unchanged
WREG Working register (accumulator)
x Don't care (0 or 1)
The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all
Microchip software tools.
TBLPTR 21-bit Table Pointer (points to a Program Memory location)
TABLAT 8-bit Table Latch
TOS Top-of-Stack
PC Program Counter
PCL Program Counter Low Byte
PCH Program Counter High Byte
PCLATH Program Counter High Byte Latch
PCLATU Program Counter Upper Byte Latch
GIE Global Interrupt Enable bit
WDT Watchdog Timer
TO Time-out bit
PD Power-down bit
C, DC, Z, OV, N ALU status bits Carry, Digit Carry, Zero, Overflow, Negative
[ ] Optional
( ) Contents
→ Assigned to
< > Register bit field
∈ In the set of
italics User defined term (font is courier)
Literal operations
15 8 7 0
OPCODE k (literal) MOVLW 0x7F
Control operations
CALL, GOTO and Branch operations
15 8 7 0
OPCODE n<7:0> (literal) GOTO Label
15 12 11 0
1111 n<19:8> (literal)
15 8 7 0
OPCODE S n<7:0> (literal) CALL MYFUNC
15 12 11 0
n<19:8> (literal)
S = Fast bit
15 11 10 0
OPCODE n<10:0> (literal) BRA MYFUNC
15 8 7 0
OPCODE n<7:0> (literal) BC MYFUNC
Cycles: 1 Words: 1
Cycles: 2 Words: 1
BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set
Syntax: [ label ] BTFSC f,b[,a] Syntax: [ label ] BTFSS f,b[,a]
Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255
0≤b≤7 0≤b<7
a ∈ [0,1] a ∈ [0,1]
Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1
Status Affected: None Status Affected: None
Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff
Description: If bit 'b' in register ’f' is 0, then the Description: If bit 'b' in register 'f' is 1, then the
next instruction is skipped. next instruction is skipped.
If bit 'b' is 0, then the next instruction If bit 'b' is 1, then the next instruction
fetched during the current instruction fetched during the current instruc-
execution is discarded, and a NOP is tion execution, is discarded and a
executed instead, making this a two- NOP is executed instead, making this
cycle instruction. If ‘a’ is 0, the a two-cycle instruction. If ‘a’ is 0, the
Access Bank will be selected, over- Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the the bank will be selected as per the
BSR value (default). BSR value (default).
Words: 1 Words: 1
Cycles: 1(2) Cycles: 1(2)
Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed
by a 2-word instruction. by a 2-word instruction.
Q Cycle Activity: Q Cycle Activity:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read Process Data No Decode Read Process Data No
register ’f’ operation register ’f’ operation
If skip: If skip:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
No No No No No No No No
operation operation operation operation operation operation operation operation
If skip and followed by 2-word instruction: If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
No No No No No No No No
operation operation operation operation operation operation operation operation
No No No No No No No No
operation operation operation operation operation operation operation operation
Cycles: 1 Words: 1
Description: Clears the contents of the specified Encoding: 0000 0000 0000 0100
register. If ‘a’ is 0, the Access Bank Description: CLRWDT instruction resets the
will be selected, overriding the BSR Watchdog Timer. It also resets the
value. If ‘a’ = 1, then the bank will postscaler of the WDT. Status bits
be selected as per the BSR value TO and PD are set.
(default). Words: 1
Words: 1 Cycles: 1
Cycles: 1 Q Cycle Activity:
Q Cycle Activity: Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Decode No Process No
Decode Read Process Write operation Data operation
register ’f’ Data register ’f’
Example: CLRWDT
Example: CLRF FLAG_REG,1
Before Instruction
Before Instruction WDT Counter = ?
FLAG_REG = 0x5A After Instruction
After Instruction WDT Counter = 0x00
FLAG_REG = 0x00 WDT Postscaler = 0
TO = 1
PD = 1
Description: The contents of register ’f’ are com- Encoding: 0110 001a ffff ffff
plemented. If ’d’ is 0, the result is Description: Compares the contents of data
stored in W. If ’d’ is 1, the result is memory location 'f' to the contents
stored back in register ’f’ (default). If of W by performing an unsigned
‘a’ is 0, the Access Bank will be subtraction.
selected, overriding the BSR value. If 'f' = W, then the fetched instruc-
If ‘a’ = 1, then the bank will be tion is discarded and a NOP is exe-
selected as per the BSR value cuted instead, making this a two-
(default). cycle instruction. If ‘a’ is 0, the
Words: 1 Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
Cycles: 1 the bank will be selected as per the
Q Cycle Activity: BSR value (default).
Q1 Q2 Q3 Q4 Words: 1
Decode Read Process Write to Cycles: 1(2)
register ’f’ Data destination
Note: 3 cycles if skip and followed
Example: COMF REG, 0, 0 by a 2-word instruction.
Before Instruction Q Cycle Activity:
REG = 0x13
Q1 Q2 Q3 Q4
After Instruction
Decode Read Process No
REG = 0x13
register ’f’ Data operation
W = 0xEC
If skip:
Q1 Q2 Q3 Q4
No No No No
operation operation operation operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No No No No
operation operation operation operation
No No No No
operation operation operation operation
CPFSGT Compare f with W, skip if f > W CPFSLT Compare f with W, skip if f < W
Syntax: [ label ] CPFSGT f [,a] Syntax: [ label ] CPFSLT f [,a]
Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255
a ∈ [0,1] a ∈ [0,1]
Operation: (f) − (W), Operation: (f) – (W),
skip if (f) > (W) skip if (f) < (W)
(unsigned comparison) (unsigned comparison)
Status Affected: None Status Affected: None
Encoding: 0110 010a ffff ffff Encoding: 0110 000a ffff ffff
Description: Compares the contents of data Description: Compares the contents of data
memory location ’f’ to the contents memory location 'f' to the contents
of the W by performing an of W by performing an unsigned
unsigned subtraction. subtraction.
If the contents of ’f’ are greater than If the contents of 'f' are less than
the contents of WREG, then the the contents of W, then the fetched
fetched instruction is discarded and instruction is discarded and a NOP
a NOP is executed instead, making is executed instead, making this a
this a two-cycle instruction. If ‘a’ is two-cycle instruction. If ‘a’ is 0, the
0, the Access Bank will be Access Bank will be selected. If ’a’
selected, overriding the BSR value. is 1, the BSR will not be overridden
If ‘a’ = 1, then the bank will be (default).
selected as per the BSR value Words: 1
(default).
Cycles: 1(2)
Words: 1 Note: 3 cycles if skip and followed
Cycles: 1(2) by a 2-word instruction.
Note: 3 cycles if skip and followed Q Cycle Activity:
by a 2-word instruction.
Q1 Q2 Q3 Q4
Q Cycle Activity: Decode Read Process No
Q1 Q2 Q3 Q4 register ’f’ Data operation
Decode Read Process No If skip:
register ’f’ Data operation Q1 Q2 Q3 Q4
If skip: No No No No
Q1 Q2 Q3 Q4 operation operation operation operation
No No No No If skip and followed by 2-word instruction:
operation operation operation operation Q1 Q2 Q3 Q4
If skip and followed by 2-word instruction: No No No No
Q1 Q2 Q3 Q4 operation operation operation operation
No No No No No No No No
operation operation operation operation operation operation operation operation
No No No No
operation operation operation operation Example: HERE CPFSLT REG, 1
NLESS :
Example: HERE CPFSGT REG, 0 LESS :
NGREATER : Before Instruction
GREATER : PC = Address (HERE)
Before Instruction W = ?
PC = Address (HERE) After Instruction
W = ? If REG < W;
After Instruction PC = Address (LESS)
If REG ≥ W;
If REG > W; PC = Address (NLESS)
PC = Address (GREATER)
If REG ≤ W;
PC = Address (NGREATER)
Words: 2
Cycles: 2 (3)
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process No
register ’f’ Data operation
(src)
Decode No No Write
operation operation register ’f’
No dummy (dest)
read
Description: The eight-bit literal ’k’ is loaded into Encoding: 0110 111a ffff ffff
W. Description: Move data from W to register ’f’.
Words: 1 Location ’f’ can be anywhere in the
256 byte bank. If ‘a’ is 0, the
Cycles: 1 Access Bank will be selected, over-
Q Cycle Activity: riding the BSR value. If ‘a’ = 1, then
Q1 Q2 Q3 Q4 the bank will be selected as per the
Decode Read Process Write to W
BSR value (default).
literal ’k’ Data Words: 1
Cycles: 1
Example: MOVLW 0x5A
Q Cycle Activity:
After Instruction Q1 Q2 Q3 Q4
W = 0x5A Decode Read Process Write
register ’f’ Data register ’f’
Cycles: 1
Example:
Q Cycle Activity:
Q1 Q2 Q3 Q4
None.
Decode Read Process Write
register ’f’ Data register ’f’
POP Pop Top of Return Stack PUSH Push Top of Return Stack
Syntax: [ label ] POP Syntax: [ label ] PUSH
Operands: None Operands: None
Operation: (TOS) → bit bucket Operation: (PC+2) → TOS
Status Affected: None Status Affected: None
Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101
Description: The TOS value is pulled off the Description: The PC+2 is pushed onto the top of
return stack and is discarded. The the return stack. The previous TOS
TOS value then becomes the previ- value is pushed down on the stack.
ous value that was pushed onto the This instruction allows to implement
return stack. a software stack by modifying TOS,
This instruction is provided to and then push it onto the return
enable the user to properly manage stack.
the return stack to incorporate a Words: 1
software stack.
Cycles: 1
Words: 1
Q Cycle Activity:
Cycles: 1
Q1 Q2 Q3 Q4
Q Cycle Activity: Decode PUSH PC+2 No No
Q1 Q2 Q3 Q4 onto return operation operation
Decode No POP TOS No stack
operation value operation
Example: PUSH
Example: POP Before Instruction
GOTO NEW
TOS = 00345Ah
Before Instruction PC = 000124h
TOS = 0031A2h
Stack (1 level down) = 014332h After Instruction
PC = 000126h
After Instruction TOS = 000126h
Stack (1 level down) = 00345Ah
TOS = 014332h
PC = NEW
After Interrupt
PC = TOS Before Instruction
W = WS W = 0x07
BSR = BSRS
STATUS = STATUSS After Instruction
GIE/GIEH, PEIE/GIEL = 1
W = value of kn
RLNCF Rotate Left f (no carry) RRCF Rotate Right f through Carry
Syntax: [ label ] RLNCF f [,d [,a] Syntax: [ label ] RRCF f [,d [,a]
Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255
d ∈ [0,1] d ∈ [0,1]
a ∈ [0,1] a ∈ [0,1]
Operation: (f<n>) → dest<n+1>, Operation: (f<n>) → dest<n-1>,
(f<7>) → dest<0> (f<0>) → C,
Status Affected: N, Z (C) → dest<7>
Description: The contents of register ’f’ are Encoding: 0011 00da ffff ffff
rotated one bit to the left. If ’d’ is 0, Description: The contents of register 'f' are
the result is placed in W. If ’d’ is 1, rotated one bit to the right through
the result is stored back in register the Carry Flag. If 'd' is 0, the result
'f' (default). If ’a’ is 0, the Access is placed in W. If 'd' is 1, the result
Bank will be selected, overriding is placed back in register 'f'
the BSR value. If ’a’ is 1, then the (default). If ‘a’ is 0, the Access
bank will be selected as per the Bank will be selected, overriding
BSR value (default). the BSR value. If ’a’ is 1, then the
register f
bank will be selected as per the
BSR value (default).
Words: 1 C register f
Cycles: 1
Words: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4 Cycles: 1
Decode Read Process Write to Q Cycle Activity:
register ’f’ Data destination Q1 Q2 Q3 Q4
Decode Read Process Write to
Example: RLNCF REG, 1, 0 register ’f’ Data destination
Before Instruction
REG = 1010 1011 Example: RRCF REG, 0, 0
After Instruction Before Instruction
REG = 0101 0111 REG = 1110 0110
C = 0
After Instruction
REG = 1110 0110
W = 0111 0011
C = 0
The PRO MATE II device programmer has program- 21.12 PICDEM 2 Low Cost PIC16CXX
mable VDD and VPP supplies, which allow it to verify Demonstration Board
programmed memory at VDD min and VDD max for max-
imum reliability. It has an LCD display for instructions The PICDEM 2 demonstration board is a simple dem-
and error messages, keys to enter commands and a onstration board that supports the PIC16C62,
modular detachable socket assembly to support various PIC16C64, PIC16C65, PIC16C73 and PIC16C74
package types. In stand-alone mode, the PRO MATE II microcontrollers. All the necessary hardware and soft-
device programmer can read, verify, or program ware is included to run the basic demonstration pro-
PICmicro devices. It can also set code protection in this grams. The user can program the sample
mode. microcontrollers provided with the PICDEM 2 demon-
stration board on a PRO MATE II device programmer,
21.10 PICSTART Plus Entry Level or a PICSTART Plus development programmer, and
Development Programmer easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 2 demonstration
The PICSTART Plus development programmer is an board to test firmware. A prototype area has been pro-
easy-to-use, low cost, prototype programmer. It con- vided to the user for adding additional hardware and
nects to the PC via a COM (RS-232) port. MPLAB connecting it to the microcontroller socket(s). Some of
Integrated Development Environment software makes the features include a RS-232 interface, push button
using the programmer simple and efficient. switches, a potentiometer for simulated analog input, a
The PICSTART Plus development programmer sup- serial EEPROM to demonstrate usage of the I2CTM bus
ports all PICmicro devices with up to 40 pins. Larger pin and separate headers for connection to an LCD
count devices, such as the PIC16C92X and module and a keypad.
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus development programmer is CE
compliant.
24CXX/
25CXX/
HCSXXX
PIC14000
MCP2510
PIC16C5X
PIC16C6X
PIC16C7X
PIC16C8X
PIC17C4X
MCRFXXX
PIC16F62X
PIC16F8XX
PIC16C7XX
PIC16C9XX
PIC17C7XX
PIC18CXX2
PIC18FXXX
PIC12CXXX
PIC16CXXX
MPLAB® Integrated
TABLE 21-1:
Development Environment
á
á
á
á
á
á
á
á
á
á
á
á
á
MPLAB® C17 C Compiler
á á
á á
MPLAB® C18 C Compiler
MPASMTM Assembler/
Software Tools
MPLINKTM Object Linker
á
á
á á
á á
á á
á á
á á
á á
á á
á á
á á
á á
á á
á á
á á
á á á
á á á
ICEPICTM In-Circuit Emulator
á
á
á
á
á
á
á
á
MPLAB® ICD In-Circuit
* *
Debugger
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
PRO MATE® II
Universal Device Programmer **
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
PICDEMTM 2 Demonstration † †
Board
á
á
á
á
DEVELOPMENT TOOLS FROM MICROCHIP
PICDEMTM 3 Demonstration
Advance Information
Board
á
á
PICDEMTM 17 Demonstration
Board
á
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB® ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77.
** Contact Microchip Technology Inc. for availability date.
DS39564A-page 255
PIC18FXX2
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
6.0V
5.5V
5.0V PIC18FXXX
4.5V
Voltage
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
40 MHz
Frequency
6.0V
5.5V
5.0V
4.5V PIC18LFXXX
Voltage
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
4 MHz 40 MHz
Frequency
FMAX = (20.0 MHz/V) (VDDAPPMIN - 2.0 V) + 4 MHz
Note: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application.
VDD
(LVDIF can be
VLVD cleared in software)
(LVDIF set by hardware)
LVDIF
VDD/2
RL Pin CL
VSS
CL
Pin
RL = 464Ω
VSS CL = 50 pF for all pins except OSC2/CLKOUT
and including D and E outputs as ports
OSC1
1 3 3 4 4
2
CLKOUT
Q4 Q1 Q2 Q3
OSC1
10 11
CLKOUT
13 12
14 19 18
16
I/O Pin
(input)
17 15
20, 21
Note: Refer to Figure 22-4 for load conditions.
Param.
Symbol Characteristic Min Typ Max Units Conditions
No.
10 TosH2ckL
OSC1↑ to CLKOUT↓ — 75 200 ns (1)
11 TosH2ckH
OSC1↑ to CLKOUT↑ — 75 200 ns (1)
12 TckR CLKOUT rise time — 35 100 ns (1)
13 TckF CLKOUT fall time — 35 100 ns (1)
14 CLKOUT ↓ to Port out valid
TckL2ioV — — 0.5TCY + 20 ns (1)
15 Port in valid before CLKOUT ↑
TioV2ckH 0.25TCY + 25 — — ns (1)
16 Port in hold after CLKOUT ↑
TckH2ioI 0 — — ns (1)
17 TosH2ioV
OSC1↑ (Q1 cycle) to Port out valid — 50 150 ns
18 TosH2ioI
OSC1↑ (Q2 cycle) to PIC18FXXX 100 — — ns
18A Port input invalid PIC18LFXXX 200 — — ns
(I/O in hold time)
19 TioV2osH Port input valid to OSC1↑ 0 — — ns
(I/O in setup time)
20 TioR Port output rise time PIC18FXXX — 10 25 ns
20A PIC18LFXXX — — 60 ns
21 TioF Port output fall time PIC18FXXX — 10 25 ns
21A PIC18LFXXX — — 60 ns
22†† TINP INT pin high or low time Tcy — — ns
23†† TRBP RB7:RB4 change INT high or low time Tcy — — ns
24†† TRCP RC7:RC4 change INT high or low time 20 ns
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKOUT output is 4 x TOSC.
FIGURE 22-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34 34
I/O Pins
BVDD
VDD
35
VBGAP = 1.2V
VIRVST
TABLE 22-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
Symbol Characteristic Min Typ Max Units Conditions
No.
30 TmcL MCLR Pulse Width (low) 2 — — µs
31 TWDT Watchdog Timer Time-out Period 7 18 33 ms
(No Postscaler)
32 TOST Oscillation Start-up Timer Period 1024TOSC — 1024TOSC — TOSC = OSC1 period
33 TPWRT Power up Timer Period 28 72 132 ms
34 TIOZ I/O Hi-impedance from MCLR Low — 2 — µs
or Watchdog Timer Reset
35 TBOR Brown-out Reset Pulse Width 200 — — µs VDD ≤ BVDD (see
D005)
36 TIVRST Time for Internal Reference — 20 50 µs
Voltage to become stable
T0CKI
40 41
42
T1OSO/T1CKI
45 46
47 48
TMR0 or
TMR1
Note: Refer to Figure 22-4 for load conditions.
Param
Symbol Characteristic Min Max Units Conditions
No.
40 Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — ns
With Prescaler 10 — ns
41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — ns
With Prescaler 10 — ns
42 Tt0P T0CKI Period No Prescaler TCY + 10 — ns
With Prescaler Greater of: — ns N = prescale
20 nS or TCY + 40 value
N (1, 2, 4,..., 256)
45 Tt1H T1CKI Synchronous, no prescaler 0.5TCY + 20 — ns
High Time Synchronous, PIC18FXXX 10 — ns
with prescaler PIC18LFXXX 25 — ns
Asynchronous PIC18FXXX 30 — ns
PIC18LFXXX 50 — ns
46 Tt1L T1CKI Low Synchronous, no prescaler 0.5TCY + 5 — ns
Time Synchronous, PIC18FXXX 10 — ns
with prescaler PIC18LFXXX 25 — ns
Asynchronous PIC18FXXX 30 — ns
PIC18LFXXX TBD TBD ns
47 Tt1P T1CKI Synchronous Greater of: — ns N = prescale
input 20 nS or TCY + 40 value
period N (1, 2, 4, 8)
Asynchronous 60 — ns
Ft1 T1CKI oscillator input frequency range DC 50 kHz
48 Tcke2tmrI Delay from external T1CKI clock edge to 2TOSC 7TOSC —
timer increment
CCPx
(Capture Mode)
50 51
52
CCPx
(Compare or PWM Mode)
53 54
Param.
Symbol Characteristic Min Max Units Conditions
No.
50 TccL CCPx input low No Prescaler 0.5TCY + 20 — ns
time With PIC18FXXX 10 — ns
Prescaler PIC18LFXXX 20 — ns
51 TccH CCPx input No Prescaler 0.5TCY + 20 — ns
high time With PIC18FXXX 10 — ns
Prescaler PIC18LFXXX 20 — ns
52 TccP CCPx input period 3TCY + 40 — ns N = prescale
N value (1,4 or 16)
53 TccR CCPx output fall time PIC18FXXX — 25 ns
PIC18LFXXX — 45 ns
54 TccF CCPx output fall time PIC18FXXX — 25 ns
PIC18LFXXX — 45 ns
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 22-4 for load conditions.
Param.
Symbol Characteristic Min Max Units Conditions
No.
62 TdtV2wrH Data in valid before WR↑ or CS↑ 20 — ns
(setup time) 25 — ns Extended Temp. range
63 TwrH2dtI WR↑ or CS↑ to data–in invalid PIC18FXXX 20 — ns
(hold time) PIC18LFXXX 35 — ns
64 TrdL2dtV RD↓ and CS↓ to data–out valid — 80 ns
— 90 ns Extended Temp. range
65 TrdH2dtI RD↑ or CS↓ to data–out invalid 10 30 ns
66 TibfINH Inhibit of the IBF flag bit being cleared from — 3TCY
WR↑ or CS↑
SS
70
SCK
(CKP = 0)
71 72
78 79
SCK
(CKP = 1)
79 78
80
75, 76
Param.
Symbol Characteristic Min Max Units Conditions
No.
70 TssL2scH, SS↓ to SCK↓ or SCK↑ input
Tcy — ns
TssL2scL
71 TscH SCK input high time Continuous 1.25TCY + 30 — ns
71A (Slave mode) Single Byte 40 — ns (Note 1)
72 TscL SCK input low time Continuous 1.25TCY + 30 — ns
72A (Slave mode) Single Byte 40 — ns (Note 1)
73 TdiV2scH, Setup time of SDI data input to SCK edge
100 — ns
TdiV2scL
73A TB2B Last clock edge of Byte1 to the 1st clock edge (Note 2)
1.5TCY + 40 — ns
of Byte2
74 TscH2diL, Hold time of SDI data input to SCK edge
100 — ns
TscL2diL
75 TdoR SDO data output rise time PIC18FXXX — 25 ns
PIC18LFXXX — 45 ns
76 TdoF SDO data output fall time — 25 ns
78 TscR SCK output rise time PIC18FXXX — 25 ns
(Master mode) PIC18LFXXX — 45 ns
79 TscF SCK output fall time (Master mode) — 25 ns
80 TscH2doV, SDO data output valid after PIC18FXXX — 50 ns
TscL2doV SCK edge PIC18LFXXX — 100 ns
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
SS
81
SCK
(CKP = 0)
71 72
79
73
SCK
(CKP = 1)
80
78
75, 76
74
Note: Refer to Figure 22-4 for load conditions.
Param.
Symbol Characteristic Min Max Units Conditions
No.
71 TscH SCK input high time Continuous 1.25TCY + 30 — ns
71A (Slave mode) Single Byte 40 — ns (Note 1)
72 TscL SCK input low time Continuous 1.25TCY + 30 — ns
72A (Slave mode) Single Byte 40 — ns (Note 1)
73 TdiV2scH, Setup time of SDI data input to SCK edge
100 — ns
TdiV2scL
73A TB2B Last clock edge of Byte1 to the 1st clock edge
1.5TCY + 40 — ns (Note 2)
of Byte2
74 TscH2diL, Hold time of SDI data input to SCK edge
100 — ns
TscL2diL
75 TdoR SDO data output rise time PIC18FXXX — 25 ns
PIC18LFXXX 45 ns
76 TdoF SDO data output fall time — 25 ns
78 TscR SCK output rise time PIC18FXXX — 25 ns
(Master mode) PIC18LFXXX 45 ns
79 TscF SCK output fall time (Master mode) — 25 ns
80 TscH2doV, SDO data output valid after PIC18FXXX — 50 ns
TscL2doV SCK edge PIC18LFXXX 100 ns
81 TdoV2scH, SDO data output setup to SCK edge
TCY — ns
TdoV2scL
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
SS
70
SCK
(CKP = 0) 83
71 72
78 79
SCK
(CKP = 1)
79 78
80
75, 76 77
74
73
TABLE 22-13: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0))
Param.
Symbol Characteristic Min Max Units Conditions
No.
70 TssL2scH, SS↓ to SCK↓ or SCK↑ input TCY — ns
TssL2scL
71 TscH SCK input high time Continuous 1.25TCY + 30 — ns
71A (Slave mode) Single Byte 40 — ns (Note 1)
72 TscL SCK input low time Continuous 1.25TCY + 30 — ns
72A (Slave mode) Single Byte 40 — ns (Note 1)
73 TdiV2scH, Setup time of SDI data input to SCK edge 100 — ns
TdiV2scL
73A TB2B Last clock edge of Byte1 to the first clock edge of Byte2 1.5TCY + 40 — ns (Note 2)
74 TscH2diL, Hold time of SDI data input to SCK edge 100 — ns
TscL2diL
75 TdoR SDO data output rise time PIC18FXXX — 25 ns
PIC18LFXXX 45 ns
76 TdoF SDO data output fall time — 25 ns
77 TssH2doZ SS↑ to SDO output hi-impedance 10 50 ns
78 TscR SCK output rise time (Master mode) PIC18FXXX — 25 ns
PIC18LFXXX 45 ns
79 TscF SCK output fall time (Master mode) — 25 ns
80 TscH2doV, SDO data output valid after SCK edge PIC18FXXX — 50 ns
TscL2doV PIC18LFXXX 100 ns
83 TscH2ssH, SS ↑ after SCK edge 1.5TCY + 40 — ns
TscL2ssH
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
70
SCK
83
(CKP = 0)
71 72
SCK
(CKP = 1)
80
75, 76 77
SDI
MSb IN bit6 - - - -1 LSb IN
74
Note: Refer to Figure 22-4 for load conditions.
Param.
Symbol Characteristic Min Max Units Conditions
No.
70 TssL2scH, SS↓ to SCK↓ or SCK↑ input — ns
TCY
TssL2scL
71 TscH SCK input high time Continuous 1.25TCY + 30 — ns
71A (Slave mode) Single Byte 40 — ns (Note 1)
72 TscL SCK input low time Continuous 1.25TCY + 30 — ns
72A (Slave mode) Single Byte 40 — ns (Note 1)
73A TB2B Last clock edge of Byte1 to the first clock edge of Byte2 1.5TCY + 40 — ns (Note 2)
74 TscH2diL, Hold time of SDI data input to SCK edge — ns
100
TscL2diL
75 TdoR SDO data output rise time PIC18FXXX — 25 ns
PIC18LFXXX 45 ns
76 TdoF SDO data output fall time — 25 ns
77 TssH2doZ
SS↑ to SDO output hi-impedance 10 50 ns
78 TscR SCK output rise time PIC18FXXX — 25 ns
(Master mode) PIC18LFXXX — 45 ns
79 TscF SCK output fall time (Master mode) — 25 ns
80 TscH2doV, SDO data output valid after SCK PIC18FXXX — 50 ns
TscL2doV edge PIC18LFXXX — 100 ns
82 TssL2doV SDO data output valid after SS↓ PIC18FXXX — 50 ns
edge PIC18LFXXX — 100 ns
83 TscH2ssH, SS ↑ after SCK edge — ns
1.5TCY + 40
TscL2ssH
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
SCL
91 93
90 92
SDA
START STOP
Condition Condition
Param.
Symbol Characteristic Min Max Units Conditions
No.
90 TSU:STA START condition 100 kHz mode 4700 — ns Only relevant for Repeated
Setup time 400 kHz mode 600 — START condition
91 THD:STA START condition 100 kHz mode 4000 — ns After this period, the first
Hold time 400 kHz mode 600 — clock pulse is generated
92 TSU:STO STOP condition 100 kHz mode 4700 — ns
Setup time 400 kHz mode 600 —
93 THD:STO STOP condition 100 kHz mode 4000 — ns
Hold time 400 kHz mode 600 —
91 92
SDA
In
110
109 109
SDA
Out
Param.
Symbol Characteristic Min Max Units Conditions
No.
100 THIGH Clock high time 100 kHz mode 4.0 — µs PIC18FXXX must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — µs PIC18FXXX must operate at a
minimum of 10 MHz
SSP Module 1.5TCY —
101 TLOW Clock low time 100 kHz mode 4.7 — µs PIC18FXXX must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 — µs PIC18FXXX must operate at a
minimum of 10 MHz
SSP Module 1.5TCY —
102 TR SDA and SCL rise 100 kHz mode — 1000 ns
time 400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from
10 to 400 pF
103 TF SDA and SCL fall 100 kHz mode — 300 ns
time 400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from
10 to 400 pF
90 TSU:STA START condition 100 kHz mode 4.7 — µs Only relevant for Repeated
setup time 400 kHz mode 0.6 — µs START condition
91 THD:STA START condition hold 100 kHz mode 4.0 — µs After this period, the first clock
time 400 kHz mode 0.6 — µs pulse is generated
106 THD:DAT Data input hold time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 µs
107 TSU:DAT Data input setup time 100 kHz mode 250 — ns (Note 2)
400 kHz mode 100 — ns
92 TSU:STO STOP condition 100 kHz mode 4.7 — µs
setup time 400 kHz mode 0.6 — µs
109 TAA Output valid from 100 kHz mode — 3500 ns (Note 1)
clock 400 kHz mode — — ns
110 TBUF Bus free time 100 kHz mode 4.7 — µs Time the bus must be free
400 kHz mode 1.3 — µs before a new transmission can
start
D102 CB Bus capacitive loading — 400 pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast mode I2C bus device can be used in a standard mode I2C bus system, but the requirement TSU:DAT ≥ 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification) before the SCL line is
released.
SCL
91 93
90 92
SDA
START STOP
Condition Condition
Param.
Symbol Characteristic Min Max Units Conditions
No.
90 TSU:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for
Setup time 400 kHz mode 2(TOSC)(BRG + 1) — Repeated START
(1)
condition
1 MHz mode 2(TOSC)(BRG + 1) —
91 THD:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the
Hold time 400 kHz mode 2(TOSC)(BRG + 1) — first clock pulse is
generated
1 MHz mode(1) 2(TOSC)(BRG + 1) —
92 TSU:STO STOP condition 100 kHz mode 2(TOSC)(BRG + 1) — ns
Setup time 400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode(1) 2(TOSC)(BRG + 1) —
93 THD:STO STOP condition 100 kHz mode 2(TOSC)(BRG + 1) — ns
Hold time 400 kHz mode 2(TOSC)(BRG + 1) —
(1)
1 MHz mode 2(TOSC)(BRG + 1) —
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
SDA
Out
Param.
Symbol Characteristic Min Max Units Conditions
No.
100 THIGH Clock high time 100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode(1) 2(TOSC)(BRG + 1) — ms
101 TLOW Clock low time 100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode(1) 2(TOSC)(BRG + 1) — ms
102 TR SDA and SCL 100 kHz mode — 1000 ns CB is specified to be from
rise time 400 kHz mode 20 + 0.1CB 300 ns 10 to 400 pF
1 MHz mode(1) — 300 ns
103 TF SDA and SCL 100 kHz mode — 300 ns CB is specified to be from
fall time 400 kHz mode 20 + 0.1CB 300 ns 10 to 400 pF
1 MHz mode(1) — 100 ns
90 TSU:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for
setup time 400 kHz mode 2(TOSC)(BRG + 1) — ms Repeated START
1 MHz mode (1) 2(TOSC)(BRG + 1) — ms condition
91 THD:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first
hold time 400 kHz mode 2(TOSC)(BRG + 1) — ms clock pulse is generated
1 MHz mode (1) 2(TOSC)(BRG + 1) — ms
106 THD:DAT Data input 100 kHz mode 0 — ns
hold time 400 kHz mode 0 0.9 ms
1 MHz mode(1) TBD — ns
107 TSU:DAT Data input 100 kHz mode 250 — ns (Note 2)
setup time 400 kHz mode 100 — ns
1 MHz mode(1) TBD — ns
92 TSU:STO STOP condition 100 kHz mode 2(TOSC)(BRG + 1) — ms
setup time 400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode(1) 2(TOSC)(BRG + 1) — ms
109 TAA Output valid from 100 kHz mode — 3500 ns
clock 400 kHz mode — 1000 ns
1 MHz mode(1) — — ns
110 TBUF Bus free time 100 kHz mode 4.7 — ms Time the bus must be free
400 kHz mode 1.3 — ms before a new transmission
1 MHz mode (1)
TBD — ms can start
D102 CB Bus capacitive loading — 400 pF
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
2: A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter #107 ≥ 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to
the SDA line, parameter #102.+ parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode) before the SCL
line is released.
RC6/TX/CK
pin 121 121
RC7/RX/DT
pin
120
122
Note: Refer to Figure 22-4 for load conditions.
Param.
Symbol Characteristic Min Max Units Conditions
No.
120 TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock high to data out valid PIC18FXXX — 40 ns
PIC18LFXXX — 100 ns
121 Tckrf Clock out rise time and fall time PIC18FXXX — 20 ns
(Master mode) PIC18LFXXX — 50 ns
122 Tdtrf Data out rise time and fall time PIC18FXXX — 20 ns
PIC18LFXXX — 50 ns
RC6/TX/CK
pin 125
RC7/RX/DT
pin
126
Param.
Symbol Characteristic Min Max Units Conditions
No.
125 TdtV2ckl SYNC RCV (MASTER & SLAVE)
Data hold before CK ↓ (DT hold time) 10 — ns
126 TckL2dtl Data hold after CK ↓ (DT hold time) 15 — ns
Param
Symbol Characteristic Min Typ Max Units Conditions
No.
A01 NR Resolution — — 10 bit VREF = VDD ≥ 3.0V
— — TBD bit VREF = VDD < 3.0V
A03 EIL Integral linearity error — — <±1 LSb VREF = VDD ≥ 3.0V
— — TBD LSb VREF = VDD < 3.0V
A04 EDL Differential linearity error — — <±1 LSb VREF = VDD ≥ 3.0V
— — TBD LSb VREF = VDD < 3.0V
A05 EFS Full scale error — — <±1 LSb VREF = VDD ≥ 3.0V
— — TBD LSb VREF = VDD < 3.0V
A06 EOFF Offset error — — <±1 LSb VREF = VDD ≥ 3.0V
— — TBD LSb VREF = VDD < 3.0V
A10 — Monotonicity guaranteed(3) — VSS ≤ VAIN ≤ VREF
A20 VREF Reference voltage 0V — — V
A20A (VREFH - VREFL) 3V — — V For 10-bit resolution
A21 VREFH Reference voltage High AVss — AVDD + 0.3V V
A22 VREFL Reference voltage Low AVss - 0.3V — AVdd V
A25 VAIN Analog input voltage AVSS - 0.3V — Vref + 0.3V V
A30 ZAIN Recommended impedance of — — 10.0 kΩ
analog voltage source
A40 IAD A/D conversion PIC18FXXX — 180 — µA Average current
current (VDD) PIC18LFXXX — 90 — µA consumption when
A/D is on (Note 1)
A50 IREF VREF input current (Note 2) 10 — 1000 µA During VAIN acquisition.
Based on differential of
VHOLD to VAIN. To charge
CHOLD see Section 17.0.
— — 10 µA During A/D conversion cycle
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current
spec includes any such leakage from the A/D module.
VREF current is from RA2/AN2/VREF- and RA3/AN3/VREF+ pins or AVDD and AVSS pins, whichever is
selected as reference input.
2: Vss ≤ VAIN ≤ VREF
3: The A/D conversion result never decreases with an increase in the Input Voltage, and has no missing codes.
BSF ADCON0, GO
(Note 2)
131
Q4
130
A/D CLK 132
ADIF TCY
GO DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
2: This is a minimal RC delay (typically 100 nS), which also disconnects the holding capacitor from the analog input.
Param
Symbol Characteristic Min Max Units Conditions
No.
130 TAD A/D clock period PIC18FXXX 1.6 20(5) µs TOSC based, VREF ≥ 3.0V
(5)
PIC18LFXXX 3.0 20 µs TOSC based, VREF full range
PIC18FXXX 2.0 6.0 µs A/D RC mode
PIC18LFXXX 3.0 9.0 µs A/D RC mode
131 TCNV Conversion time 11 12 TAD
(not including acquisition time) (Note 1)
132 TACQ Acquisition time (Note 3) 15 — µs -40°C ≤ Temp ≤ 125°C
10 — µs 0°C ≤ Temp ≤ 125°C
135 TSWC Switching Time from convert → sample — (Note 4)
136 TAMP Amplifier settling time (Note 2) 1 — µs This may be used if the
“new” input voltage has not
changed by more than 1 LSb
(i.e., 5 mV @ 5.12V) from
the last sampled voltage (as
stated on CHOLD).
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 17.0 for minimum conditions, when input voltage has changed more than 1 LSb.
3: The time for the holding capacitor to acquire the “New” input voltage, when the voltage changes full scale
after the conversion (AVDD to AVSS, or AVSS to AVDD). The source impedance (RS) on the input channels is
50Ω.
4: On the next Q4 cycle of the device clock.
5: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
XXXXXXXXXXXXXXXXX PIC18F242-E/SO
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN 0110017
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
* Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
XXXXXXXXXXXXXXXXXX PIC18F442-I/P
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN 0112017
XXXXXXXXXX PIC18F452
XXXXXXXXXX -I/L
XXXXXXXXXX
YYWWNNN 0120017
XXXXXXXXXX PIC18F442
XXXXXXXXXX -E/PT
XXXXXXXXXX
YYWWNNN 0120017
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INDEX
A B
A/D ................................................................................... 179 Baud Rate Generator ....................................................... 149
A/D Converter Flag (ADIF Bit) ................................. 181 BC .................................................................................... 217
A/D Converter Interrupt, Configuring ....................... 182 BCF .................................................................................. 218
Acquisition Requirements ........................................ 182 BF .................................................................................... 153
ADCON0 Register .................................................... 179 Block Diagrams
ADCON1 Register ............................................ 179, 180 A/D Converter .......................................................... 181
ADRESH Register .................................................... 179 Analog Input Model .................................................. 182
ADRESH/ADRESL Registers .................................. 181 Baud Rate Generator .............................................. 149
ADRESL Register .................................................... 179 Capture Mode Operation ......................................... 117
Analog Port Pins .................................................. 97, 98 Compare Mode Operation ....................................... 118
Analog Port Pins, Configuring .................................. 184 Low Voltage Detect
Associated Registers ............................................... 186 External Reference Source ............................. 188
Block Diagram .......................................................... 181 Internal Reference Source ............................... 188
Block Diagram, Analog Input Model ......................... 182 MSSP
Configuring the Module ............................................ 182 I2C Mode ......................................................... 132
Conversion Clock (TAD) ........................................... 184 MSSP (SPI Mode) ................................................... 123
Conversion Status (GO/DONE Bit) .......................... 181 On-Chip Reset Circuit ................................................ 25
Conversions ............................................................. 185 Parallel Slave Port (PORTD and PORTE) ................. 98
Converter Characteristics ........................................ 284 PIC18F2X2 .................................................................. 8
Equations ................................................................. 183 PIC18F4X2 .................................................................. 9
Minimum Charging Time .................................. 183 PLL ............................................................................ 19
Examples PORTA
Calculating the Minimum Required RA3:RA0 and RA5 Port Pins ............................. 85
Acquisition Time ...................................... 183 RA4/T0CKI Pin .................................................. 86
Results Registers ..................................................... 185 RA6 Pin ............................................................. 86
Special Event Trigger (CCP) ............................ 118, 186 PORTB
TAD vs. Device Operating Frequencies .................... 184 RB2:RB0 Port Pins ............................................ 89
Timing Diagram ........................................................ 285 RB3 Pin ............................................................. 89
Use of the SSP2 Trigger .......................................... 186 RB7:RB4 Port Pins ............................................ 88
Absolute Maximum Ratings ............................................. 257 PORTC (Peripheral Output Override) ........................ 91
AC (Timing) Characteristics ............................................. 266 PORTD (I/O Mode) .................................................... 93
Load Conditions for Device Timing Specifications ... 267 PORTE (I/O Mode) .................................................... 95
Parameter Symbology ............................................. 266 PWM Operation (Simplified) .................................... 120
Temperature and Voltage Specifications ................. 267 Timer1 ..................................................................... 106
Timing Conditions .................................................... 267 Timer1 (16-bit R/W Mode) ....................................... 106
ADCON0 Register ............................................................ 179 Timer2 ..................................................................... 110
GO/DONE Bit ........................................................... 181 Timer3 ..................................................................... 112
ADCON1 Register .................................................... 179, 180 Timer3 (16-bit R/W Mode) ....................................... 112
ADDLW ............................................................................ 215 USART
ADDWF ............................................................................ 215 Asynchronous Receive .................................... 171
ADDWFC ......................................................................... 216 Asynchronous Transmit ................................... 169
ADRESH Register ............................................................ 179 Watchdog Timer ...................................................... 202
ADRESH/ADRESL Registers ........................................... 181 BN .................................................................................... 218
ADRESL Register ............................................................ 179 BNC ................................................................................. 219
AKS .................................................................................. 153 BNN ................................................................................. 219
Analog-to-Digital Converter. See A/D BNOV ............................................................................... 220
ANDLW ............................................................................ 216 BNZ .................................................................................. 220
ANDWF ............................................................................ 217 BOR. See Brown-out Reset.
Assembler BOV ................................................................................. 223
MPASM Assembler .................................................. 251 BRA ................................................................................. 221
BRG. See Baud Rate Generator.
Brown-out Reset (BOR) ..............................................26, 193
Timing Diagram ....................................................... 271
BSF .................................................................................. 221
BTFSC ............................................................................. 222
BTFSS ............................................................................. 222
BTG ................................................................................. 223
Bus Collision During a RESTART Condition ................... 160
Bus Collision During a START Condition ........................ 158
Bus Collision During a STOP Condition .......................... 161
BZ .................................................................................... 224
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