A PLD Based Delta-Sigma DAC

Delta-Sigma modulation is the simple, yet powerful, technique responsible for the extraordinary performance and low cost of today's audio CD players. The simplest Delta-Sigma DAC consists of a Delta-Sigma modulator and a one bit DAC. Since, both of these components can be realized using digital circuits, it is possible to implement a low precision Delta-Sigma DAC using a PLD. A better understanding of the Delta-Sigma DAC can be achieved by first examining the operation of an analog DAC. Figure 1 shows an analog DAC utilizing an R-2R resistor ladder. The DAC reference voltage is divided into binary weighted currents by the resistor ladder. The values of the bits in the digital input word are used to open or close the switches. Each switch applies its current to the output amplifier when a binary one is applied. A digital word with all ones would close all the switches providing the maximum current to the output amplifier. In contrast, a digital word of all zeroes would provide no current to the output amplifier. The output amplifier converts the sum of all the ladder currents into the output voltage, Vo. The performance of this circuit is critically dependent upon the ladder network. The resistors must be well matched to achieve high performance, but this becomes more and more difficult as the number of bits, and consequently the number of resistors, increases. In addition, temperature and aging adversely affect the performance of the entire analog circuit. An alternative to the R-2R resistor ladder is to use a Delta-Sigma () DAC. While the DAC avoids the pitfalls associated with the ladder network, it too has challenges that are unique to its architecture. Specifically, the output resolution, or quantization noise, of a DAC is directly related to its operating speed. A high resolution DAC requires very high speed operation. A complete DAC can be constructed from a Delta-Sigma modulator and a 1-bit D/A converter. The Delta-Sigma modulator translates each digital input word into a pulse train. The duty cycle, or the fraction of time that the signal is high, is proportional to the digital input word. An analogy to the Delta-Sigma modulator is that of modulating the intensity of light in a room by flipping the light switch off and on. If the switch is always on, then the room lighting is maximum. When the switch is off, the lighting in the room is minimum. If the switch is turned off and on using a 50% duty cycle, then on average, the light intensity is also about one half of the maximum. Figure 2 illustrates an analog waveform generated from the time average of a single bit. The modulator can be implemented in either analog or digital form. This technical brief will focus on the digital implementation. Figure 3 shows the block diagram of an 8-bit digital DAC. The feedback loop from the output of the quantizer to the input of the Delta block (B input), is subtracted from the A input to form the difference or Delta (). The 1-bit quantizer output is multiplied by -256 to scale and negate the 1-bit output. We can simplify the logic if we use two's complement arithmetic internally and straight binary coding for the A input. The A input and the corresponding output voltage are shown in the table below. Input A - Straight Binary Format Analog Output (V) +Full Scale - 1LSB Half Scale +1 LSB Half Scale Half Scale -1 LSB 0 Dec 255 129 128 127 0 Binary 0011111111 0010000001 0010000000 0001111111 0000000000

The internal two's complement format allows the Delta block to add the B input to the A input to perform the subtraction. The scaling and inversion of B becomes a trivial operation in digital logic. All we need to do is set B equal to -256 (1100000000) when the quantizer output is high, and set B to 0 (0000000000) when the quantizer output is low. All numbers within the DAC are represented using 10-bits to avoid problems with overflow. The Sigma block accumulates the difference between the input, A, and the feedback B (quantizer output). If the accumulated sum, , exceeds 511, the output of the 1-bit quantizer will be 1, otherwise it will be 0. When the quantizer output is 1, the feedback path causes 256 to be subtracted from the input value and the result is then accumulated in the Sigma block. In effect, every time the accumulated sum, , rolls over (i.e. hitting or exceeding 512) the value of 256 is

subtracted from the sum, causing the sum to fall below 512 again. The input value, A, continually adds to the sum, incrementing it, until it is greater than or equal to 512. At that point the quantizer block outputs a 1 for that cycle. Therefore, the size of the input, A, determines the rate at which , exceeds 511, and consequently determines the rate at which the quantizer block outputs ones and zeroes. Let's look at a few numerical examples of the DeltaSigma modulator in operation. First, let's set the input, A, to a value of 0. Sigma is assumed to be 256. The quantizer output is 0, and consequently Delta is also 0 since, A and B are both 0. After each successive clock period, the accumulated sum remains at a value of 256 since Delta is always 0. So, for an input value of 0, the quantizer outputs 0 continuously. For an input value of 1, let's assume Sigma is again 256, and the quantizer output is initially 0. During each successive clock period the accumulated sum, , increments by 1. After 256 clock cycles, Sigma will reach a value of 512 and the quantizer will output a value of 1. The quantizer output value of one will feedback to the Delta block causing -256 to be added to the input value of 1. The result, -255 will be added to the accumulated sum resulting in a value of 257. Since this value is below 512, the quantizer output will go to 0, and the Sigma block will continue to increment by 1, during each subsequent clock cycle. This sequence will repeat with the quantizer output going high for one clock cycle out of every 256. Let's look at another example in tabular form. In the table below the values for each block are given after each clock cycle. A 64 64 64 64 64 64 64 64 64 256 320 384 448 512 320 384 448 512 64 64 64 64 832 64 64 64 832 Q 0 0 0 0 1 0 0 0 1

In the previous example, the quantizer output goes high once every four clock cycles. In this example, an input value of 64, which is of the Full Scale output (i.e. 64/256) produces a waveform at the output of the quantizer with a duty cycle of . This is the function of the Delta-Sigma modulator. As one final example, consider an input value of 128. Assume Sigma is 256 and the quantizer output is initially 0. The first clock cycle will produce a Sigma of 384. Q will remain low and the second clock cycle will produce a Sigma of 512. Q will assert high and the next clock cycle will produce a Sigma of 384 (512+128-256). Q will assert low and the next clock cycle will produce a Sigma of 512. This cycle will repeat with Q toggling between one and zero every clock cycle. So an input of 128 (i.e. Full Scale), produces a 50% duty cycle output waveform, or 128 high pulse every 256 clock cycles. One final point before we leave the discussion of the Delta-Sigma modulator. In our first example we set the input to a value of 1. In this case the quantizer asserts high, for 1 cycle out of every 256 clock cycles. This corresponds to an 8-bit DAC, since it is able to resolve signals down to a resolution of 1 part in 256. Our Delta-Sigma modulator outputs a waveform with a duty cycle equivalent to the fraction created by dividing the input digital word by 256. The minimum resolution of a Delta-Sigma DAC is determined by the number of clock cycles used to process each input word. If we allowed our DAC to use 512 cycles to process each input, we could resolve down to 1 part in 512, the equivalent of a 9bit DAC. In general, the number of clock cycles required for a Delta-Sigma DAC to process a binary input word of length N is given by 2N. A 16-bit Delta-Sigma DAC requires 65,536 clock cycles to process each input word. To produce an audio signal at 10kHz, without violating Nyquist, this DAC must operate at 1.3 GHz! In practice, Delta-Sigma DAC's don't really have to operate at these extreme speeds. Fortunately most people have reduced sensitivity in the upper audio frequency range, and designers can lower the number of effective bits at the higher frequencies. Now that we have examined the Delta-Sigma modulator, we turn our attention to the 1-bit DAC. In reality we can only approximate a 1-bit DAC in a digital PLD, but the approximation is certainly sufficient for demonstration. Looking again at Figure

3 we see the 1-bit DAC simply outputs +5V when Q=1, and 0V when Q=0. This function is accomplished at the output pin of the PLD. When Q outputs a logic "1" the PLD produces a voltage of +5V and when Q outputs a logic "0" the PLD produces an output voltage of 0V. Of course this is not exactly correct, since digital devices, or PLD's specifically, will produce an output level dependent upon the voltage, temperature and process of the device as well as the characteristics of the output loading. If absolute voltage accuracy is required then the PLD output pin can be used to drive an analog switch and a voltage reference, providing a very stable output voltage. If, on the other hand, absolute accuracy is not critical, then the voltage, temperature, process and the output loading characteristics of a typical PLD will be stable enough to emulate a 1-bit DAC. One final issue needs to be addressed. Remember that a DAC outputs a time series of discrete levels, not a continuous waveform. The sampled data output from a DAC, such as the R-2R resistor ladder DAC, appears a stair step and must be filtered to produce the desired result. Likewise, the Delta-Sigma DAC produces a duty cycled, pulse modulated waveform that must also be filtered. DAC output filters are designed to pass the signal band of interest, while rejecting the sampling frequency. This eliminates the stair step response and smoothes the output waveform. As the DAC sampling frequency increases, relative to the signal bandwidth, the filter becomes easier to design. Figure 4 illustrates the relationship between the signal bandwidth, the sampling frequency and the filter requirements. Figure 4 does not show the effects of the sin(x)/x response caused by the DAC sampling. However, Figure 4 does illustrate the various images of the signal created at the sampling frequency and its harmonics. The DAC output, or reconstruction, filter response must include the signal bandwidth of interest while attenuating the sampling images. When the sampling images are close together, the slope of the filter response must be steep. Conversely, when the sampling images are very far apart, the slope of the reconstruction filter need not be steep at all. The number of poles in a filter determines the transition bandwidth, or the distance between the pass-band and the stop-band. As the transition band decreases, the number of poles, and consequently the complexity of the filter, increases. Therefore, as the DAC sampling

frequency increases, the sampling images get farther apart and the complexity of the filter can be reduced. The simplest low-pass filter consists of a single resistor and capacitor. If we assume the signal band of interest is 20kHz, an 8-bit DAC and a sampling rate eight times the signal rate then we can calculate the values for R, C and the DAC clock. An 8-bit Delta-Sigma DAC requires 256 clock cycles to generate 8-bit resolution. So, the DAC clock rate must be: 8 * 256 * 20kHz = 40.96 MHz.

Since the maximum frequency we wish to pass is 20kHz we can calculate the 3dB point of a simple low-pass filter as follows: F-3dB = 1 / ( 2 * * R * C ) Choosing a capacitor value of .01uF and solving for R: R = 1 / ( 20kHz * 2 * .01uF) = 795 . A series resistor of 795 , with a shunt capacitor of .01uF will have a -3dB frequency of 20kHz. This single pole, low pass filter will pass the signal band of interest, while providing nearly 65dB of attenuation to the nearest sampling image. A PLD based Delta-Sigma DAC can be used anytime it is more desirable to view a signal as an analog waveform rather than as a stream of digital numbers. For example, the error signal in a feedback loop would be easier to view in analog form. Simply add a few logic gates to a PLD, tack on a single resistor and capacitor, and suddenly those digital numbers take on a new look. Applications include the analog display of Sin and Cosine waveforms digitally produced in a PLD. Also, signal constellations for modulators or demodulators can be displayed using the XY mode of an oscilloscope.

Figure 1 - Block Diagram of R-2R DAC

Bn R 2R
1

B2 R 2R
1 0

B1 R 2R
1 0

B0 VREF 2R 2R
1 0

2R
0

+ -

VO

Figure 2 - Time Average of Delta-Sigma Modulator Output

2 2 1 1 1

5 2 9 6 2 9 6 3

6 4 2 0 8 6 4 2 0

Figure 3 - Block Diagram of Delta-Sigma DAC

Delta
8 A B
clk

Sigma
C D 1-bit Quantizer

1-bit DAC
+5V

*(-256)

Figure 4 - DAC Output Filter Response

Fs Filter Response

2Fs

Sampling Images Signal Frequency