Experiment No.

4(b) IMPLEMENTATIOM OF 4-BIT COMPARATOR CIRCUIT Objective: To compare values between two inputs List Of Major Equipments Sl No. 1 2 Theory : This circuit (74LS85) is used for comparison. It cons sts of a set of inputs A and B and a set of outputs A>B, i r u t (74 S m rs n nsis s t p t d d t t us B, us d A=B, A<B. Depending on the relative magnitudes of A and B, one of the three output will be high. In a 8-bit B, B. p n i g e ai e n u e d e e e t u l g . 8-b t comparison, the firs four bits of A and B are compared in one comparator circuit The output of this circuit m r s n e rst fo r s d e m r d e m r t ci c it. e t u i ci c i (E(A>B),E( =B)and E(A<B)) are respectively conn cted to the cascad ng inputs(Q(A B),Q(A B) and Q(A<B)) nnecte e s adin p t ( (A>B), (A=B) d < (E(A B),E(A= n E(A B)) e s e i l of second comparator circuit whic is given the remaining bits of both A and B as inp uts for comparison. But o d m r t ci c i ich v n e m i i g s bo h d p t m rs n t in o ur experiment, we are dealing with comparison between two four bit numbers using comparator circuit So r ei e t e a n wi m rs w n m r t ci c it. fo r t nu b r us n the firs four bits of each of A and B are taken as 0000. So if the firs four bits are fed into a comparator circuit, e rst fo r s c d e e e rst fo r s e d t m r t r u , its output will have logic high in the pin E (A=B) and logic low in the pins E (A<B) and E (A>B). So eventually t u l v g c gh e n (A B) d i e n < d (A B). it eve t a l the cascading inputs of second comparator circuit will have logic high at Q (A=B) and logic low at Q (A>B) and e s a i g p t c n m r t ci c i l v i gh i (A B) d (A B) Q (A<B). Hence while using a single comparator circuit, Q (A=B) is given 1 and the other two casca ing inputs i e us n n l m r t r u , (A B) n d e h r a cadi p t (A B). He c are given 0 e n Name 115W power Supply Logic Probe Manufacturer ELNOVA Taiwan Make Model No. E-61 Model-625 Specification 5V, 5A 50MHz Frequency Range

WORKING TABLE FOUR BIT COMPARATOR: COMPARATING INPUTS A3 B3 A3>B3 A3<B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A2 B2 X X A2>B2 A2<B2 A2=B2 A2=B2 A2=B2 A2=B2 A2=B2 A2=B2 A2=B2 A1 B1 X X X X A1>B1 A1<B1 A1=B1 A1=B1 A1=B1 A1=B1 A1=B1 A0 B0 X X X X X X A0>B0 A0<B0 A0=B0 A0=B0 A0=B0 CASCADING INPUTS A>B A=B A<B X X X X X X X X 1 0 0 X X X X X X X X 0 1 0 X X X X X X X X 0 0 1 OUTPUTS A>B 1 0 1 0 1 0 1 0 1 0 0 A=B 0 0 0 0 0 0 0 0 0 1 0 A<B 0 1 0 1 0 1 0 1 0 0 1

OBSERVATION TABLE: COMPARATING INPUTS A3 B3 A2 B2 A1 B1 A0 B0 CASCADING INPUTS A>B A=B A<B L L L L H H H H L L L L OUTPUTS A>B A=B A<B

FOUR BIT COMPARATOR CHIP

CONCLUSION : N L O 1. The truth table and observati table are same. e t l d ob e v tion l e m . 2. The I.C. chip has sixteen pins Out of these pins four are for input of A, four are for input of B, three are for e i x n ns. Ou e e n fo r e p t p t e e fo r e cascad ng inputs and three are for outputs. s adin p t d e e t us 3. The cascad ng input Q (A=B) is given logic high and other two inputs (Q(A>B) and Q(A<B)) are at logic low e s adin p t = v n g c gh d h r p t ( > d < e i as we are taking the firs four bits of each of A and B as e i g e rst fo r s c d i 0000. So whil using a single comparator chip Q A=B) is at logic high ile us n n l m r t i B)