The RF Receiver Front-End Chip Design with the Transformer Balun for DSRC Applications

Jhin-Fang Huang, Yong-Jhen Jiangn, and Ron-Yi Liu* Department of Electronic Engineering, National Taiwan University of Science and Technology #43, Sec.4, Keelung Rd., Taipei, 106, Taiwan, R.O.C. * Telecommunication Laboratories, Chung-Hwa Telecom Co., Ltd., Tauyan, Taiwan, R.O.C. Abstract A 0.18 m CMOS RF receiver front-end applying in DSRC systems is presented in this paper. The proposed receiver front-end includes the current-reused LNA, the folded Giber cell mixer, and the Colpitts VCO. Also, this paper presents the design methodology and application of the transformer balun for RFIC. The measured results of the proposed receiver front-end show the input return loss of 30.5 dB, the conversion gain of 17.5 dB, the (DSB) NF of 4.2 dB, and the third-order intercept point (IIP3) of 10 dBm at 5.8 GHz frequency. The chip area of the proposed receiver front-end including pads is 1.4 x 1.4 mm2 with the total power dissipation of 49.78 mW. Index Terms receiver, front-end, CMOS, DSRC, balun. appropriately amplifies the weak radio signal and doesnt increases too much noise to following circuits. Then, the mixer converts the RF signal from the LNA to the IF signal for baseband circuits to handle well. The VCO provides LO signal to the mixer for mixing IF signal. Since the LNA is single-ended output and the mixer is differential input, the passive balun is applied to convert single to differential form due to no power consumption required.

I. INTRODUCTION
ITS communication system has been widely developed for solving the traffic problem. This new communication technology can effectively improve the mobile safety and traffic efficiency in vehicle transportation. The dedicated short range communications (DSRC) protocol is defined in the physical layer of ITS, and the 5.8 GHz band is applied for the short distance communication applications. The 5.8 GHz frequency is located in the unlicensed industrial, scientific, and medical (ISM) band. The DSRC supports both public safety and private operations in vehicle to roadside and vehicle to vehicle communications. The DSRC system provides high speed radio link between the road side unit (RSU) and the onboard unit (OBU) with the narrow band communication. Meanwhile, the DSRC communication protocol has been developed worldwide and practically applied for the electronic toll collection (ETC) system. This paper begins with a discussion in Section II on the motivation for this work and proposed architecture. The measured results are summarized in Section III, and the conclusions are given in Section IV.

FIGURE 1. Circuit block of the proposed receiver front-end.

A. Transformer Balun
The physical layout of the proposed passive balun is shown in Fig. 2. This turn ratio (N) of the balun for the secondary coil to the first coil is 4:3, and it has width of 3 m and space of 2 m. To reduce the silicon substrate loss, the transformer balun is made of top metal.

II. CIRCUIT DESIGN

Recently, a fully integrated 0.25 m SiGe-BiCMOS transceiver for DSRC applications is demonstrated [1]. However, this SiGeBiCMOS chip design is more expensive than the CMOS one in addition to the larger power consumption is not practical for OBUs application under the supply voltage of 3.3 V. On the other hand, the active balun is applied to convert the single-ended output into the differential output between the LNA and the mixer [2], but the active balun requires extra power consumption in comparison with the passive balun. To reduce the chip area, the fully integrated receiver front-end with the active inductor is proposed [3]. Although using the active inductor can reduce large chip area, yet the local oscillator built in the receiver front-end has the large power consumption and bad phase noise performance. With those considerations, the CMOS receiver front-end chip design is presented for DSRC applications in this paper. The overall circuit block of this proposed receiver front-end is shown in Fig. 1. The LNA receives RF signal from the antenna, and FIGURE 2. Layout of the proposed passive balun. The center point of the secondary coil is taken to ground to eliminate the phase difference of terminal S1 and S2. Figure 3 shows the equivalent model of the balun. nP, nS1, and nS2 are the main coil, first minor coil, and second minor coil respectively.

FIGURE 3. Equivalent model of the balun.

978-1-4244-8499-7/11/$26.00 2011 IEEE

Firstly, decide the ratio of impendence between the main coil and the minor coil as shown in (1). Secondly, the turn ratio of the balun is obtained by (2). Finally, after considering the influence of the coupling factor (k), the real turn ratio can be obtained by (3).

third-order nonlinearity than connected to a current source.

n=

nS 1 nS 2 = = np nP

Z2 . Z1

(1)

N'=

nS 1 + nS 2 = 2n . nP
N= N' . k

(2)

(3)
FIGURE 5. Schematic of the proposed mixer.

B. LNA
Figure 4 shows the proposed current-reused LNA. The impendence of Ld1 is adequately large to provide a high impendence path to block the signal at the desired bandwidth, while the Cg2 and Lg2 provide a low impendence path. When the LNA operates in AC, it acts as two stage cascade CS amplifiers. On the contrary, when it operates in DC, this circuit acts as a cascode amplifier. Therefore, this architecture can amplify the input signal twice and only consumes one DC current path.

D. VCO
Figure 6 shows the proposed Colpitts VCO, which has better noise performance than the NMOS cross-coupled oscillator and the complementary cross-coupled oscillator [5]. By using gm-boosted technique [6], this Colpitts oscillator can be designed in less current consumption to achieve oscillation mechanism. The output of the VCO is connected to the buffer, formed by the common source amplifier with the LC load, to build enough output power for mixer to mixing well and let the operation of the VCO not influenced by mixer.

FIGURE 4. Schematic of the proposed LNA.

FIGURE 6. Schematic of the proposed VCO.

C. Mixer
Figure 5 depicts the proposed folded mixer, which has the advantages of better performing in low voltage operation than the common cascode mixer. From [4] we have the input referred flicker-noise voltage of the LO FETs Vn is:

III. MEASURED RESULTS

Figure 7 shows the measured input return loss of the receiver front-end, and the measured input return loss is 30.5 dB at 5.8 GHz and higher than 10 dB from 5.2 GHz to 6.9 GHz.

Vn =

2K f Weff Leff Cox f

(4)

, where Kf is a technology parameter, Weff and Leff are effective width and length respectively. Cox is the oxide capacitance with frequency f. To reduce flick noise, large LO transistors are needed but large transistors show larger parasitic capacitances at their source node, resulting in gain reduced, noise increased, and linearity decreased. So the center-tap inductor (Lc) is added to eliminate the parasitic capacitances. Also, the parallel load capacitors (CL1) and (CL2) are added to suppress high order harmonic. It gives a pole to mixer transfer function. The outputs of balun are coupled to the mixer input transistor gates of M1 and M2, whose source terminals are directly connected to ground and this circuit will produce lower

FIGURE 7. Measured S11 of the receiver front-end. Figure 8 shows the measured CG and P-1dB of the receiver frontend, and the measured CG and P-1dB is 17.5 dB and -20 dBm respectively.

Figure 12 shows the measured phase noise of the VCO, and the measured phase noise is -117.57 dBc/Hz at 1 MHz offset from a 5.8 GHz carrier.

FIGURE 8. Measured CG and P-1dB of the receiver front-end. Figure 9 shows the measured NF of the receiver front-end, and the measured NF is 4.2 dB at the intermediate frequency of 30 MHz. FIGURE 12. Measured phase noise of the VCO. Figure 13 shows the measured output power spectrum of the VCO, and the measured output power is -6.6 dBm at 5.8 GHz.

FIGURE 9. Measured NF of the receiver front-end. Figure 10 shows the measured IIP3 of the receiver front-end, and the measured IIP3 is -10 dBm. FIGURE 13. Measured output power spectrum of the VCO. Figure 14 shows the photomicrograph of the receiver front-end, and this chip is tested by on-wafer measurement. The chip area includes pads is 1.4 x 1.4 mm2.

FIGURE 10. Measured IIP3 of the receiver front-end. Figure 11 shows the measured tuning range of the VCO. The measured operating frequency can changes from 5.17 GHz to 5.97 GHz as the control voltage varied from 0 V to 1 V. FIGURE 14. Photomicrograph of the proposed receiver front-end. The current consumption flowing from the LNA-mixer, the core circuit and the output buffers of the VCO is 23 mA under the supply voltage of 1.5 V, 3.68 mA and 12.2 mA under the supply voltage of 1 V respectively. The FOM (figure of merit) of the receiver frontend is defined as follows [7]:
FOM = 20log( f RF ) + CG NF + IIP3 10log(PD ) .

(5)

FIGURE 11. Measured tuning range of the VCO.

, where f RF means the operating frequency and CG means the conversion gain. The symbol NF means the noise figure, and IIP 3 means the third-order intercept point. The symbol PD means

the dc power consumption. This proposed receiver front-end achieve the FOM of 211.6, and the performance of a receiver frontend is better with a more positive value in the FOM. Table 1 summarizes the measured performance of the proposed receiver front-end compared with other previously published papers. Obviously, our design achieves the performance of high linearity and low noise figure. TABLE I. PERFORMANCE COMPARISON OF THE RECEIVER FRONT-END.

is adopted to converting single to differential between the LNA and the mixer. Since no power consumption unlike the active balun, the passive balun has the remarkable performance at low power dissipation. So it is useful in the DSRC wireless communication systems applications. The Colpitts VCO built in the receiver frontend achieves low power dissipation, low phase noise, and wide tuning range. So it is suitable for providing the local oscillating signal to the receiver front-end.

ACKNOWLEDGMENT
Process ( m) fRF (GHz) PD (mW) CG (dB) NF (dB) IIP3 (dBm) FOM [3] CMOS 0.18 2.4 42 16.2 2.5 -19.7 195.4 [8] CMOS 0.18 5 37.56 17.8 11.9 -16 198.1 [9] CMOS 0.18 5 37.4 28.2 6.4 -21.5 208.6 This Work CMOS 0.18 5.8 49.78 17.5 4.2 -10 211.6 The authors would like to acknowledge the fabrication support and the chip fabrication provided by National Chip Implementation Center (CIC).

REFERENCES
N. Sasho, K. Minami, H. Fujita, T. Takahashi, K. Iimura, M. Abe, and A. Yasuda, Single-Chip 5.8GHz DSRC Transceiver with Dual-Mode of ASK and Pi/4-QPSK, in Proc. IEEE Radio and Wireless Symp., pp. 799-802, Jan. 2008. [2] C.-I. Shie, C.-H. Hsieh, and Y.-C. Chiang, UWB LNA and Mixer with an Active Balun in 0.18 m CMOS Process, in Proc. Asia Pacific Microw. Conf., pp. 1140-1143, Dec. 2009. [3] J.-T. Yang, D.-W. Shen, P.-J. Tsai, and M.-J. Wu, A CMOS Radio Frequency Receiver for Bluetooth Applications, in Proc. 1st Asia Quality Electronic Design Symp., pp. 352-356, Jul. 2009. [4] H. Darabi and A.A. Adibi, ": A Simple Physical Model", IEEE J. Solid-State Circuits, vol. 35, no. 1, pp. 15-25, Jan. 2000. [5] R. Aparicio and A. Hajimiri A noise-shifting differential Colpitts VCO, IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1728-1736, Dec. 2002. [6] X. Li, S. Shekhar, and D.J. Allstot, Gm-boosted commongate LNA and differential colpitts VCO/QVCO in 0.18- m CMOS, IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2609-2619, Dec. 2005. [7] V. Vorst and S. Mirabbasi, Low-voltage bulk-driven mixer with on-chip balun, in Proc. IEEE Int. Circuits and Systems symp., pp. 456-459, May 2008. [8] M.-C. Chen, Y. Ding, and C.-Y. Wu A 5-GHz CMOS Direct-conversion Receiver with Novel DC Offset Compensation Circuit, in Proc. The 4th regional interuniversity postgraduate electrical electronics engineering conf., Jul. 2006. [9] W.-Z. Chen, T.-L. Lee, and T.-Y. Lu, A 5-GHz directconversion receiver with I/Q phase and gain error calibration, in Proc. IEEE Radio Freq. Integr. Circuits Symp., pp. 201-204, Jun. 2005. [10] T. T. Ta, S. Kameda, T. Takagi, and K. Tsubouchi, A 5GHz Band Low Noise and Wide Tuning Range Si-CMOS VCO, in Proc. IEEE Radio Freq. Integr. Circuits Symp., pp. 57574, Jun. 2009. [11] J. Park, J. Park, Y. Choi, K. Sim, and D. Baek, Member, A Fully-Differential Complementary Hartley VCO in 0.18 m CMOS Technology, IEEE Microw. Wireless Compon. Lett., vol. 20, no. 2, pp. 91-93, Feb. 2010. [12] J.-A. Hou and Y.-H. Wang, A 5 GHz Differential Colpitts CMOS VCO Using the Bottom PMOS Cross-Coupled Current Source, IEEE Microw. Wireless Compon. Lett., vol. 19, no. 6, pp. 401-403, Jun. 2009. [1]

The FOM and the FOMT (figure of merit with tuning range) of the VCO is defined as follows respectively [10]:

FOM = L(fc ) 20log(

fo P ) +10log( dc ) . fc 1mW

(6)

TR(%) . FOMT = FOM 20log( ) 10

(7)

, where L ( f c ) means the phase noise and f 0 means the oscillating frequency. The symbol Pdc means the dc power consumption and

f c =1 MHz. The proposed VCO achieve the FOM of -187.18

dBc/Hz and the FOMT of -190.35 dBc/Hz respectively. The performance of a VCO is better with a more negative value in the FOM and the FOMT. Table 2 summarizes the measured performance of the proposed VCO in comparison with other published VCO papers. Obviously, our design achieves the performance of wide tuning range and low power dissipation. TABLE II. PERFORMANCE COMPARISON OF THE VCO. [10] CMOS 0.18 5.6 8.3 17.9 -110.8 @1MHz -176.57 -181.63 [11] CMOS 0.18 5.6 6.44 2.69 -122.7 @1MHz -189.6 -178.2 [12] CMOS 0.18 5.46 6.4 10.6 -120.2 @1MHz -186.88 -187.39 This Work CMOS 0.18 5.8 3.68 14.4 -117.57 @1MHz -187.18 -190.35

Process ( m) fo (GHz) Pdc (mW) T.R. (%) P.N. (dBc/Hz) FOM (dBc/Hz) FOMT (dBc/Hz)

IV. CONCLUSION
The on-chip balun is designed and successfully applied to the proposed receiver front-end in this paper. Also, the design and application of the transformer balun is presented. The passive balun