310 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO.

2, FEBRUARY 2010
A Modied SEPIC Converter for High-Power-Factor
Rectier and Universal Input Voltage Applications
Priscila Facco de Melo, Roger Gules, Member, IEEE, Eduardo F elix Ribeiro Romaneli,
and Rafael Christiano Annunziato
AbstractA high-power-factor rectier suitable for universal
line base on a modied version of the single-ended primary induc-
tance converter (SEPIC) is presented in this paper. The voltage
multiplier technique is applied to the classical SEPIC circuit, ob-
taining new operation characteristics as low-switch-voltage opera-
tion and high static gain at low line voltage. The new conguration
also allows the reduction of the losses associated to the diode re-
verse recovery current, and soft commutation is obtained with a
simple regenerative snubber circuit. The operation analysis, de-
sign procedure, and experimental results obtained from a 650-W
universal line power-factor-correction prototype of the proposed
converter are presented. The theoretical analysis and experimen-
tal results obtained with the proposed structure are compared with
the classical boost topology.
Index TermsACDC power conversion, switched circuits,
voltage multipliers.
I. INTRODUCTION
T
HE BOOST converter is the usual structure utilized in
high-power-factor (HPF) rectiers in order to improve
power factor (PF) and reduce the total current harmonic distor-
tion (THDi). However, for universal input voltage application,
the efciency can be reduced mainly in the lowest input volt-
age, and the worst operation condition must be considered in the
power converter design procedure [1]. The improvement of the
efciency at lower line voltage is important because the thermal
design and heat sinks size are dened considering the worst op-
eration point. Many works were developed in order to improve
the operation characteristics of the power converter utilized in
HPFuniversal input rectiers. Areviewof the main single-phase
topologies and techniques used in an HPF rectier is presented
in [2][4]. A discussion about the use of single stage and two
stages structures is presented in [5]. Atwo switches topology for
universal input HPF rectier is presented in [6]. Some single-
stage-isolated HPF rectiers are presented in [7][14].
The use of high static gain and low-switch voltage topologies
can improve the efciency operating with low input voltage, as
presented in [15][18]. The voltage multiplier technique was
presented in [18] for a boost converter in order to increase the
static gain with reduced switch voltage. However, the boost volt-
age doubler cannot be used for a universal input voltage HPF
rectier because the output voltage must be higher than the dou-
ble of the maximuminput voltage (V
o
= 800 V). Amodication
in the multiphase boost voltage doubler was proposed in [1] for
Manuscript received February 19, 2009; revised May 13, 2009. Current
version published February 12, 2010. Recommended for publication by
Associate Editor P.-T. Cheng.
The authors are with the Federal University of Technology Paran a (UTFPR,),
Curitiba PR 80230-901, Brazil (e-mail: rgules@gmail.com).
Digital Object Identier 10.1109/TPEL.2009.2027323
Fig. 1. Classical SEPIC converter.
a universal input HPF rectier, in order to obtain high static gain
at the lower input voltage with the same dc output voltage level
of a classical boost converter (V
o
= 400 V).
The integration of a voltage multiplier cell with a classical
single-ended primary inductance converter (SEPIC) is proposed
in this paper in order to obtain a high step-up static gain oper-
ating with low input voltage and a low step-up static gain for
the high input voltage operation. The operation characteristics
obtained with this modication makes the proposed structure
an interesting alternative for the universal input HPF rectier or
wide input voltage range applications, operating with high ef-
ciency. The proposed converter operates with a switch voltage
lower than the output voltage, and with an input current ripple
lower than the classical boost converter. The power circuit of the
proposed converter can be integrated with a simple regenerative
snubber, obtaining soft-switching commutation and increasing
the efciency.
II. PROPOSED CONVERTER
The power circuit of the classical SEPIC converter is pre-
sented in Fig. 1. The step-up and step-down static gains of the
SEPIC converter is an interesting operation characteristic for a
wide input voltage-range application. However, as the switch
voltage is equal to the sum of the input and output voltages, this
topology is not used for a universal input HPF rectier.
The voltage multiplier technique was presented in [18] in or-
der to increase the static gain of single-phase and multiphase
boost dcdc converters. An adaptation of the voltage multiplier
technique with the SEPIC converter is presented in Fig. 2. The
modication of the SEPIC converter is accomplished with the
inclusion of the diode D
M
and the capacitor C
M
. Many op-
erational characteristics of the classical SEPIC converter are
changed with the proposed modication.
The capacitor C
M
is charged with the output voltage of the
classical boost converter. Therefore, the voltage applied to the
inductor L
2
during the conduction of the power switch (S) is
0885-8993/$26.00 2010 IEEE

DE MELO et al.: MODIFIED SEPIC CONVERTER FOR HIGH-POWER-FACTOR RECTIFIER AND UNIVERSAL INPUT VOLTAGE APPLICATIONS 311
Fig. 2. Modied SEPIC converter.
Fig. 3. First operation stage.
Fig. 4. Second operation stage.
higher than that in the classical SEPIC, thereby increasing the
static gain. The polarity of the voltage stored in the capacitor
C
S
is inverted in the proposed converter, and the expressions of
the capacitors voltages and others operation characteristics are
presented in the theoretical analysis.
The continuous conduction-mode (CCM) operation of the
modied SEPIC converter presents the following two operation
stages.
1) First stage ([t
0
, t
1
] Fig. 3)At the instant t
0
, the switch S
is turned-off and the energy stored in the input inductor L
1
is transferred to the output through the capacitor C
S
and
output diode D
o
, and also to the capacitor C
M
through the
diode D
M
. Therefore, the switch voltage is equal to the
capacitor C
M
voltage. The energy stored in the inductor
L
2
is transferred to the output through the diode D
o
.
2) Second stage ([t
1
, t
2
] Fig. 4)At the instant t
1
, the switch
S is turned-on and the diodes D
M
and D
o
are blocked, and
the inductors L
1
and L
2
store energy. The input voltage
is applied to the input inductor L
1
and the voltage V
CS

V
CM
is applied to the inductor L
2
. The voltage V
CM
is
higher than the voltage V
CS
.
The main theoretical waveforms operating with hard-
switching commutation are presented in Fig. 5.
Fig. 5. Main theoretical waveforms.
The voltage in all diodes and the power switch is equal to the
capacitor C
M
voltage. The output voltage is equal to the sum of
the C
S
and C
M
capacitors voltages. The average L
1
inductor
current is equal to the input current and the average L
2
inductor
current is equal to the output current.
III. THEORETICAL ANALYSIS
The main equations and the theoretical analysis of the pro-
posed converter are presented in this section. The results of the
theoretical analysis are compared with the classical boost con-
verter in order to show the positive and negative aspects of the
proposed converter.
Some comparison with the classical SEPIC converter is also
presented because the proposed topology is obtained from this
converter.
The equations dened by the theoretical analysis are utilized
for the determination of the inductances and capacitances of the
proposed converter. The theoretical analysis is developed con-
sidering the operation as an HPF rectier, and the utilization
of an ac voltage source and a full-bridge diode rectier con-
nected to the input of the proposed converter is considered. All

312 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010
Fig. 6. Static Gain.
analyses are accomplished for an application with an ac input
voltage changing from V
i
= 100 V
rms
to V
i
= 240 V
rms
, an
output voltage equal to V
o
= 425 V
dc
, and a nominal output
power equal to P
o
= 650 W.
A. Static Gain
The static gain of the proposed converter can be obtained
considering that the average inductor voltage is zero at the steady
state. Therefore, the relation presented in (1) must occur at the
steady state for the inductor L
1
V
i
t
ON
= (V
CM
V
i
) t
OFF
(1)
V
i
D = (V
CM
V
i
) (1 D) . (2)
Therefore, the C
M
capacitor voltage is dened by (3), which
is the same equation of the classical boost static gain given by
V
CM
V
i
=
1
1 D
. (3)
During the period where the power switch is turned-off (t
OFF
),
the diodes D
M
and D
0
are in conduction state, and the following
relation can be dened:
V
o
= V
CS
+V
CM
. (4)
The L
2
average voltage is zero at the steady state, and the
following relations can be considered:
(V
CM
V
CS
) t
ON
= (V
o
V
CM
) t
OFF
(5)
(V
CM
V
CS
)D = (V
o
V
CM
)(1 D). (6)
Substituting (3) and (7) in (6), the static gain of the proposed
converter is obtained and presented in (8)
V
CS
= V
o
V
CM
(7)
V
o
V
i
=
1 +D
1 D
. (8)
The static gain variation as a function of the duty cycle of
the modied SEPIC and the static gain of other converters is
presented in Fig. 6. The voltage doubler boost converter [18]
presents the highest static gain and is interesting for the opera-
tion with the lower input voltage. However, the minimal output
TABLE I
DUTY-CYCLE VARIATION AS A FUNCTION OF THE INPUT
AND OUTPUT VOLTAGES
voltage (D = 0) is the double of the input voltage. Therefore,
this structure cannot be used for a universal input application.
The static gain of the classical boost converter is half of the
voltage doubler boost, and can be used in a universal input ap-
plication. The modied SEPIC converter presents a static gain
closed to the classical boost for low values of duty cycle, and
a static gain closed to the voltage doubler for high values of
duty cycle. Therefore, the static gain is higher than the classical
structures in the operation with high values of duty cycle that oc-
curs in the operation with low input voltage. The operation with
a higher static gain results in an improvement in the operation
with the lower input voltage. The step-up and step-down char-
acteristics of the classical SEPIC converter are not maintained
in the modied SEPIC converter. The proposed structure cannot
operate with an output voltage lower than the input voltage.
The voltage of the series capacitor (V
CS
) is dened by sub-
stituting (3) and (8) in (7), resulting the following equation:
V
CS
V
i
=
D
1 D
. (9)
B. Input Current Ripple and L
1
L
2
Inductances
The input inductance value is dened as a function of the
maximum input current ripple. As the classical SEPIC, boost,
and the modied SEPICconverters present the same input stage,
the equation for the determination of the input current ripple is
the same for all converters. The input current ripple (i
L1
)
during the conduction of the power switch is dened by the
following equation:
i
L1
=
V
i
D
L
1
f
(10)
where f is the switching frequency.
Although the same equation can be used to calculate the input
ripple, the input current ripple for each converter is not the same
because the duty-cycle variation is different for each topology,
as presented in Fig. 6. The duty-cycle variation as a function of
the input and output voltages is presented in Table I.
In order to show the duty-cycle variation in a universal input
rectier application, the instantaneous input voltage signal is
considered in a semicycle of the input line voltage. Fig. 7 is
obtained considering an input line voltage equal to 100 V
rms
,
and Fig. 8 is obtained considering an input line voltage equal to
240 V
rms
. The output voltage is equal to V
o
= 425 V
dc
for both
gures.
As can be observed in Figs. 7 and 8, the modied SEPIC
converter presents the lowest duty-cycle value in all range of
the input voltage. Lower duty cycle results in a lower switch
conduction interval (t
ON
).

DE MELO et al.: MODIFIED SEPIC CONVERTER FOR HIGH-POWER-FACTOR RECTIFIER AND UNIVERSAL INPUT VOLTAGE APPLICATIONS 313
Fig. 7. Duty-cycle variation (V
i
= 100 V
rms
and V
o
= 425 V
dc
).
Fig. 8. Duty-cycle variation (V
i
= 240 V
rms
and V
o
= 425 V
dc
).
A lower input current ripple is also obtained because the
input voltage (V
i
) is applied to the input inductor L
1
in a shorter
interval during the t
ON
period.
The parameterized input current ripple (i
L1
) is dened from
(10) and presented in (11).
Replacing in (11) the duty cycle of each converter presented
in Table I, the parameterized input current ripple is obtained and
presented in Fig. 9 for an input voltage equal to 100 V
rms
, and
in Fig. 10, for an input voltage equal to 240 V
rms
, considering
an output voltage equal to V
o
= 425 V
dc
i
L1
= i
L1
L
1
f = V
i
D. (11)
The input inductance can be dened by (13) obtained from
(11). The input inductance is calculated for the power con-
verter operating at the peak of the lowest input voltage. For
this operation point, the instantaneous input voltage is equal
to V
ipk
= 141 V, the converter duty cycle is equal to D = 0.5,
and the input current ripple (i
L1
) considered is 23% of the
peak input current (i
inpk
). Therefore, the input current ripple is
calculated as follows:
i
L1
= i
inpk
0.23 = 6.5 0.23 = 1.5 A. (12)
The input inductance calculated is equal to
L
1
=
V
i
D
i
L1
f
=
141 0.5
1.5 48000
= 97 916 H. (13)
Fig. 9. Parameterized input current ripple (V
i
= 100 V
rms
and V
o
=
425 V
dc
).
Fig. 10. Parameterized input current ripple (V
i
= 240 V
rms
and V
o
=
425 V
dc
).
The input inductance value utilized in the practical imple-
mentation is equal to L
1
= 1 mH.
The input inductance of the proposed converter is 27% lower
than the input inductance of the classical boost converter, and
33% lower than the input inductance of the classical SEPIC
converter for the same specications, as presented in Fig. 9.
The inductor L
2
presents the same equation as the L
1
inductor
current ripple. However, the L
1
inductor average current is equal
to the average input current, and the L
2
average current is equal
to the output current. As the average input current is higher
than the average output current for a step-up converter, the L
2
inductor volume is lower than the L
1
inductor volume. The L
2
peak current is three times lower than the L
1
peak current for the
operation with the lower line input voltage. Also, the L
2
current
ripple can be higher than the L
1
current ripple because the input
current ripple depends only on the L
1
current ripple. Therefore,
the proposed converter uses two inductors, but the L
1
inductor
can be 27% lower than the input inductor of the classical boost,

314 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010
Fig. 11. Parameterized switch voltage (V
i
= 100 V
rms
and V
o
= 425 V
dc
).
Fig. 12. Parameterized switch voltage (V
i
= 240 V
rms
and V
o
= 425 V
dc
).
and the L
2
volume is smaller than the L
1
inductance. The L
2
inductance utilized in the practical implementation is half of the
L
1
inductance (L
2
= 500 H).
C. Power Switch Voltage
The power switch voltage is also an important parameter of
the circuit in a wide input voltage application, and presents in-
uence in the converter efciency and cost. The modication
proposed in this paper signicantly changes the drawback of the
operation with high switch voltage of the classical SEPIC con-
verter. A comparison of the power switch voltage is presented
in Fig. 11, considering a line input voltage equal to 100 V
rms
,
and in Fig. 12, for an input voltage equal to 240 V
rms
. In both
gures, the output voltage is equal to 425 V
dc
, and the switch
voltage is presented parameterized in relation to the output volt-
age. The switch voltage is equal to the output voltage for the
boost converter. Therefore, the parameterized voltage of this
converter is unitary in all voltage ranges. The switch voltage for
the classical SEPIC is equal to the sum of the input and output
voltages. Therefore, the operation voltage is very high, mainly
in the maximuminput voltage condition (240 V
rms
). The switch
voltage of the modied SEPIC converter is equal to the voltage
of the capacitor C
M
. This voltage is determined by (3), but with
the duty cycle of the modied SEPIC converter presented in
Table I.
As can be observed in Figs. 11 and 12, the switch voltage of
the modied SEPIC is lower than the output voltage in all input
voltage ranges. Figs. 11 and 12 also show the capacitor voltages
V
CM
and V
CS
. The output voltage is equal to the sum of the
V
CM
and V
CS
capacitors voltages.
D. Series Capacitor (C
S
) and Multiplier Capacitor (C
M
)
The C
S
series capacitor voltage and the C
M
multiplier ca-
pacitor voltage change with the line input voltage variation, as
shown in Figs. 11 and 12. Therefore, these capacitances can-
not be large as the output lter capacitor (C
o
). However, these
capacitances present a high-frequency voltage ripple due to the
circulating current and the capacitor charge variation (Q). As
the circulating current in both capacitances are equal, the high-
frequency voltage ripple is the same. During the power switch
turn-on period, the current in the C
S
and C
M
capacitances is
equal to the L
2
inductor current. The capacitor charge variation
Q is calculated as
Q = i
L2
DT. (14)
The high-frequency capacitor voltage ripple (V
c
) can be
dened by (15), as a function of the capacitor charge variation
V
c
=
Q
C
. (15)
Therefore, the C
S
and C
M
capacitances can be dened as
follows:
C
S
= C
M
=
i
L2
D
V
c
f
(16)
where f is the switching frequency.
The highest capacitor voltage ripple occurs at the peak of the
lowest line input voltage. The average current of the inductor L
2
is equal to the output current (i
o
), and its peak value must be used
in (16). Considering an input voltage equal to V
i
= 100 V
rms
and a maximum capacitor voltage ripple equal to 12% of the
output voltage (V
c
= 50 V), the capacitors C
S
and C
M
can
be dened as
C
S
= C
M
=
i
L2
D
V
c
f
=
3 0.5
50 48000
= 625 nF. (17)
The capacitances utilized in the practical implementation of
the proposed converter is equal to C
S
= C
M
= 660 nF, com-
posed of two capacitors (330 nF) connected in parallel. A
polypropylene capacitor is used in the practical implementation,
and as the equivalent series resistance (ESR) of the polypropy-
lene capacitor is very low (ESR = 12 m at 100 kHz), the
inuence of this resistance in the calculation of the capacitor
voltage ripple is not considered.

DE MELO et al.: MODIFIED SEPIC CONVERTER FOR HIGH-POWER-FACTOR RECTIFIER AND UNIVERSAL INPUT VOLTAGE APPLICATIONS 315
Fig. 13. Turn-on regenerative snubber with switch voltage equal to V
o
.
E. Output Capacitor
The output lter capacitor (C
o
) is determined as in the clas-
sical boost converter. The capacitance is dened by a function
of the output power (P
o
), the grid frequency (f
G
), and the low-
frequency output voltage ripple (V
o
). Considering an output
voltage ripple equal to 1% of the output voltage, the output
capacitance is calculated as
C
o
=
P
o
2f
G
2V
o
V
o
=
650
260 2 425 4.25
=477 F.
(18)
The output lter capacitor utilized in the practical implemen-
tation is equal to C
o
= 500 F.
F. Regenerative Snubber
A classical problem presented by the hard-switching struc-
tures operating in CCM is the reduction of the efciency due
to the additional losses caused by the reverse recovery current
of the diodes. This problem is an important source of losses
in a universal input HPF rectier. There are some regenerative
snubbers proposed for the classical boost converter that can
reduce the effects of this problem [19]. However, the correct
operation of these snubbers in all input voltage ranges is dif-
cult. Therefore, the use of these snubber integrated with the
classical boost converter cannot be effective for the universal in-
put HPF rectier. There are some soft-switching congurations
with the inclusion of an active switch and other components in
order to reduce the reverse recovery current and eliminate the
commutation losses [4], [20], [21]. This alternative can be used
in high-performance applications, but increases the complexity
and cost of the converter.
The power circuit of the modied SEPICconverter allows the
integration of three regenerative snubbers that reduces the diode
reverse recovery current problem, and is effective in all input
voltage ranges. The simplest regenerative snubber is presented
in Fig. 13. A small inductance L
snb
(typically, 520 H) is con-
nected in series with the power switch. This inductance limits
the di/dt at the switch turn-on instant and zero-current switching
(ZCS) is obtained. When the power switch is turned-off, the en-
ergy stored in the L
snb
inductance is transferred to the capacitor
C
S
through the diode D
snb
. This conguration eliminates the
turn-on commutation loss, which is the most signicant part of
the commutation losses. The turn-off commutation is dissipa-
tive and the power switch voltage is equal to the output voltage
Fig. 14. Turn-on/ turn-off regenerative snubber with switch voltage equal to
V
o
.
Fig. 15. Turn-on/ turn-off regenerative snubbers with switch voltage equal to
V
CM
.
with the inclusion of the diode D
snb
.The soft-switching turn-on
and turn-off commutation snubbers, presented in Fig. 14, can be
obtained including some additional components to the circuit
presented in Fig. 13. The inductor L
snb
limits the di/dt at the
switch turn-on, and when the power switch is turned-off, the
energy stored in this inductance is transferred to the capacitor
C
snb
through the diode D
snb1
. The initial condition of the volt-
age in the capacitor C
snb
is zero, and the reduced capacitance
value (typically, 330 nF) limits the dv/dt of the power switch
voltage. The voltage in this capacitor increases until it reaches
the output voltage value when the diode D
snb2
conducts. Dur-
ing the conduction of the power switch, the energy stored in
the capacitor C
snb
is transferred to the capacitor C
s
through the
diode D
snb2
and inductor L
snb
until the C
snb
voltage becomes
null. The peak current is limited by the L
snb
inductor during this
energy transference. The switch voltage is limited to the output
voltage with the use of this snubber.
Fig. 15 presents the turn-on and turn-off snubbers with the
power switch voltage equal to V
CM
, which is lower than the
output voltage. The operation of this snubber is almost the same
as the circuit presented in Fig. 14. The unique difference is
that during the energy transference from the inductor L
snb
to
the capacitor C
snb
, after the power switch turn-off, the capaci-
tor voltage increases until it reaches the C
M
voltage when the
diode D
snb3
conducts, maintaining the switch voltage equal
to the voltage V
CM
, as in the hard-switching circuit. During
the conduction of the power switch, the snubber capacitor is
discharged through the diode D
snb2
and inductor L
snb
, trans-
ferring energy to the capacitor C
s
. All snubber circuits does
not change the static and dynamic operations of the power

316 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010
Fig. 16. Modied SEPIC converter with magnetic coupling.
circuit, which acts only in the commutation periods, eliminating
the commutation losses and reducing the negative effects of the
reverse recovery current of all diodes.
G. Magnetic Coupling
The inductors L
1
and L
2
of the proposed converter presented
in Fig. 2 cannot be coupled as in the classical SEPIC topology
without changing signicantly the operation characteristics pre-
sented in this paper. Therefore, the magnetic coupling of these
inductors is not analyzed for the proposed modication of the
SEPIC converter. The operation of the proposed converter with
isolation between the input and output with the inductor L
2
op-
erating as a yback transformer is possible, but is not presented
in this paper. The inductor L
2
can also be used as a yback
transformer without isolation, as presented in Fig. 16. The ad-
vantage of this modication is that the transformer turns ratio
(n
Lp2
/n
Ls2
) allows the converter operation with a very high
static gain without increasing the power switch voltage.
Therefore, this modication can be interesting for low input
voltage and high output voltage applications.
H. Control System
The control algorithm of the proposed converter is based
on the classical structure of the average current-mode control
with the digital implementation and the power system operat-
ing in CCM. The design procedure of the control system for
the boost converter is well established and used in this imple-
mentation. The implementation of the control system for the
proposed converter is accomplished by using exactly the same
control designed for the classical boost converter. This approx-
imation is possible because the additional poles inserted by the
inductor L
2
and capacitors C
S
and C
M
occur in a frequency
higher than the poles inserter by the inductor L
1
and the output
lter capacitor C
o
. As presented in Section III-D, the capacitors
C
S
and C
M
are very small comparing with the output lter ca-
pacitor. The inductor L
2
is also a fraction of the input inductor
L
1
. As the crossing frequencies of the voltage and current con-
trol loops are lower than the frequency of the lower frequency
poles, the additional higher frequency poles does not present a
signicant inuence in the phase margin and the gain margin,
thus maintaining approximately the same dynamic response for
both power stage structures. In order to show this characteristic,
the same control algorithm designed for the classical boost con-
Fig. 17. Implemented prototype.
verter is used with the proposed converter and the experimental
results obtained conrm this consideration.
The simplied block diagram of the digital control system
utilized in the implementation of the high-RF rectier is pre-
sented in Fig. 17. The control algorithm is developed using the
MC56F8013 digital signal controller operating with a sampling
rate equal to 24 kHz. The sample of the output voltage is com-
pared with a reference of the output voltage (V
ref
). The error
signal obtained (E
v
) is applied to a digital proportionalintegral
(PI) controller. The result obtained from the voltage controller
(VC
v
) is multiplied by a sample of the rectied input voltage,
and the resultant signal is the reference waveformfor the current
control loop (i
ref
). The sampling of the rectied input current
is compared with the current reference (I
ref
). The result (E
i
) is
applied to a digital PI controller. The output of the current con-
troller (V
Ci
) is applied to the pulse width modulator, generating
the command signal of the power switch.
IV. EXPERIMENTAL RESULTS
The proposed converter presented in Fig. 15 is tested with the
implementation of an experimental prototype, and the perfor-
mance of the modied SEPIC converter is compared with the
classical boost converter.
A prototype of the classical boost is also built with the same
specication of the proposed converter. The power circuit with
the components parameters and a representation of the simpli-
ed block diagram of the digital control system are presented in
Fig. 17. The experimental waveforms are obtained with the ex-
perimental prototype operating with the nominal output power
P
o
= 650 W and with an input voltage changing from V
i
=
100 V
rms
to V
i
= 240 V
rms
. The output voltage is regulated in
V
o
= 425 V
dc
. The input voltage and current waveform are pre-
sented in Fig. 18 for an input voltage equal to V
i
= 127 V
rms
.
The THDi obtained is equal to THDi = 5.49%, and the PF is
equal to PF = 0.99865. The THDi variation as a function of the

DE MELO et al.: MODIFIED SEPIC CONVERTER FOR HIGH-POWER-FACTOR RECTIFIER AND UNIVERSAL INPUT VOLTAGE APPLICATIONS 317
Fig. 18. Input voltage (V
i
) and current (I
i
) waveform for an input voltage
V
i
= 127 V
rms
(100 V/division, 5 A/division, and 5 ms/division).
Fig. 19. Total current harmonic distortion as a function of the input voltage
variation.
Fig. 20. Power-factor variation as a function of the input voltage variation.
input voltage of the proposed converter and the classical boost
converter is shown in Fig. 19.
The PF variation as a function of the input voltage of the
proposed converter and the classical boost converter is shown
in Fig. 20.
The current waveform of the L
1
input inductor and L
2
in-
ductor of the proposed converter operating with V
i
= 127 V
rms
are presented in Fig. 21. The measured current ripple of the
input current is equal to i
L1
= 1.5 A. The current waveform
of the input inductor of the classical boost converter operating
Fig. 21. L
1
and L
2
inductors current of the proposed converter operating with
V
i
= 127 V
rms
(5 A/division and 5 ms/division).
Fig. 22. Input inductor current of the classical boost converter operating with
V
i
= 127 V
rms
(2.5 A/division and 5 ms/division).
with V
i
= 127 V
rms
is presented in Fig. 22. The measured input
current ripple presented by the classical boost converter is equal
to i
L
= 2 A, using the same value of the input inductor of the
modied SEPIC converter (L
1
= L
boost
= 1 mH).
Therefore, the modied SEPIC input current ripple is 25%
lower than the current ripple of the boost converter using the
same inductance value, as presented in Section III.
The voltage waveform of the capacitors C
S
and C
M
are
presented in Fig. 23 for an input voltage equal to V
i
= 127 V
rms
,
and in Fig. 24, for an input voltage equal to V
i
= 220 V
rms
. The
experimental waveforms presented in Figs. 23 and 24 agree well
with the theoretical waveforms presented in Figs. 11 and 12,
considering as null the high-frequency capacitor voltage ripple.
The high-frequency voltage ripple presented in Fig. 23 is close
to 50 V.
A comparison of the switch voltage and current between the
proposed converter and the classical boost converter can be
done with the waveforms presented in Figs. 25 and 26. Fig. 25
shows the switch voltage and current of the proposed converter
operating with the nominal output power and an input voltage
equal to V
in
= 127 V
rms
.

318 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010
Fig. 23. C
S
and C
M
capacitors voltage operating with V
i
= 127 V
rms
(100 V/division and 5 ms/division).
Fig. 24. C
S
and C
M
capacitors voltage operating with V
i
= 220 V
rms
(100 V/division and 5 ms/division).
Fig. 25. Switch current and voltage of the proposed converter operating with
V
i
= 127 V
rms
(100 V/division, 5 A/division, and 5 ms/division).
Fig. 26. Switch current and voltage of the classical boost converter operating
with V
i
= 127 V
rms
(100 V/division, 5 A/division, and 5 ms/division).
Fig. 27. Turn-on and turn-off switch commutations of the proposed con-
verter operating with V
i
= 127 V
rms
(100 V/division, 5 A/division, and
2.5 s/division).
The switch voltage is equal to the C
M
capacitor voltage and
the maximum value is equal to V
Smax
= 320 V. The switch
peak current value is equal to I
S
= 10 A. The switch voltage
and current of the classical boost converter are shown in Fig. 26.
The switch voltage is equal to the output voltage and the
maximum value is equal to V
Smax
= 420 V. The switch peak
current value is equal to I
S
= 9 A.
The commutation improvement obtained with the regenera-
tive snubber presented in Fig. 15 is shown in Fig. 27. Fig. 27
presents the turn-on and turn-off commutations of the power
switch. As can be seen in this gure, the turn-on and turn-off
commutations are soft switching and the commutation losses are
minimized. The maximum switch voltage is equal to the C
M
capacitor voltage with the snubber presented in Fig. 15. The
proposed snubber is effective in all ranges of the input voltage
variation and in all ranges of the output power variation.
Fig. 28 presents the switch commutation operating with light
load. As can be seen in this gure, the snubber circuit maintains
the reduction of the commutation losses.

DE MELO et al.: MODIFIED SEPIC CONVERTER FOR HIGH-POWER-FACTOR RECTIFIER AND UNIVERSAL INPUT VOLTAGE APPLICATIONS 319
Fig. 28. Turn-on and turn-off switch commutations of the proposed con-
verter operating with V
i
= 127 V
rms
(100 V/division, 2.5 A/division, and
2.5 s/division).
Fig. 29. Efciency curve of the proposed converter and the classical boost
converter with and without nondissipative snubber as a function of the input
voltage.
The efciency curves of the proposed converter and the clas-
sical boost converter with hard switching and a nondissipative
snubber, operating with the nominal output power P
o
= 650 W,
are presented in Fig. 29. The highest efciency is obtained with
the highest input voltage V
i
= 240 V
rms
, and is equal to 97.4%
for the proposed converter and 95.5% for the classical boost
converter.
The efciency of the classical boost converter with the nondis-
sipative snubber is equal to 97.2%. The lowest efciency is ob-
tained with the lowest input voltage V
i
= 85 V
rms
, and is equal
to 92.6% for the proposed converter and 89% for the boost
converter with the nondissipative snubber.
Therefore, the efciency improvement with the proposed con-
verter in relation, the classical boost converter in the worst op-
eration condition is equal to 3.6%. The efciency curves of the
proposed converter as a function of the output power and oper-
ating with the input voltage equal to 90, 127, 220, and 240 V
rms
are presented in Fig. 30.
The dynamic response of the high-PF rectier implemented
with the modied SEPIC and the classical boost converters are
presented in Figs. 31 and 32, respectively. Fig. 31 presents the
output voltage (V
o
) and the input inductor current (i
L1
) of the
Fig. 30. Efciency curves of the proposed converter as a function of the output
power.
Fig. 31. Output voltage (V
o
) and input inductor current (i
L1
) of the proposed
converter operating with V
i
= 127 V
rms
and with the output power reduction
from 650 to 300 W (100 V/division, 2.5 A/division, and 50 ms/division).
Fig. 32. Output voltage (V
o
) and input inductor current (i
Lboost
) of the
classical boost converter operating with V
i
= 127 V
rms
and with the out-
put power reduction from 650 to 300 W (100 V/division, 2.5 A/division, and
50 ms/division).
proposed converter operating with an input voltage equal to
V
i
= 127 V. The output power is reduced from the nominal
value P
o
= 650 W to P
o
= 300 W. The output voltage rises
from the nominal value V
o
= 425 V to the maximum value
V
o
= 475 V during the load transient. The transient duration is
equal to 150 ms. Fig. 32 presents the output voltage (V
o
) and the

320 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010
input inductor current (i
Lboost
) of the classical boost converter
operating with the same specications of the proposed converter.
The output power is reduced from the nominal value P
o
=
650 W to P
o
= 300 W, and the output voltage rises from the
nominal value V
o
= 425 V to the maximum value V
o
= 465 V
during the load transient. The transient duration is also 150 ms.
Therefore, the overshoot of the output voltage presented by the
proposed converter is equal to 11.76%, and the overshoot of the
classical boost converter is equal to 9.4%for the same controller
parameters.
V. CONCLUSION
Amodied version of the SEPICconverter is proposed for the
implementation of a high-PF rectier suitable for universal line
application. Although the proposed structure presents a higher
circuit complexity than the classical boost converter, the advan-
tages obtained are the higher static gain for the operation with
the lower input voltage range, lower switch voltage operation,
higher efciency operation with the lowest input voltage, lower
input current ripple, and easy integration with a regenerative
snubber. Three snubber circuits are proposed in order to ob-
tain a reduction of the diode reverse recovery current problem,
and also obtaining turn-on and turn-off soft switching for all
input voltage ranges and output power variation. The average
current-mode control is used for the classical boost converter
and also for the proposed converter, and the dynamic response
obtained with both converters is approximately the same. The
experimental results are obtained with the implementation of
a rectier with an output power equal to P
o
= 650 W, using
the boost and the modied SEPIC converters, and the efciency
improvement with the proposed topology is equal to 3.6% for
the worst operation condition.
REFERENCES
[1] Y. Jang and M. M. Jovanovic, Interleaved boost converter with intrinsic
voltage-doubler characteristic for universal-line PFC front end, IEEE
Trans. Power Electron., vol. 22, no. 4, pp. 13941401, Jul. 2007.
[2] O. Garca, J. A. Cobos, R. Prieto, P. Alou, and J. Uceda, Single phase
power factor correction: Asurvey, IEEE Trans. Power Electron., vol. 18,
no. 3, pp. 749755, May 2003.
[3] B. Singh, B. N. Singh, A. Chandra, K. Al-Haddad, A. Pandey, and
D. P. Kothari, A review of single-phase improved power quality AC
DC converters, IEEE Trans. Ind. Electron., vol. 50, no. 5, pp. 962981,
Oct. 2003.
[4] M. M. Jovanovic and Y. Jang, State-of-the-art, single-phase, active power-
factor correction techniques for high-power applicationsAn overview,
IEEE Trans. Ind. Electron., vol. 52, no. 3, pp. 701708, Jun. 2005.
[5] J. Zhang, M. M. Jovanovic, and F. C. Lee, Comparison between CCM
single-stage and two-stage boost PFC converters, in Proc. Appl. Power
Electron. Conf. Expo. (APEC), Mar. 1999, vol. 1, pp. 335341.
[6] J. Chen, D. Maksimovic, and R. W. Erickson, Analysis and design of
a low-stress buck-boost converter in universal-input PFC applications,
IEEE Trans. Power Electron., vol. 21, no. 2, pp. 320329, Mar. 2006.
[7] C. Qiao and K. M. Smedley, A universal input single-phase single-stage
power supply with power factor correction and automatic voltage clamp-
ing, in Proc. Power Electron. Spec. Conf. (PESC), Jun. 2001, pp. 907
913.
[8] D. D. C. Lu, H. H. C. Iu, and V. Pjevalica, Asingle-stage AC/DCconverter
with high power factor, regulated bus voltage, and output voltage, IEEE
Trans. Power Electron., vol. 23, no. 1, pp. 218228, Jan. 2008.
[9] J. Qian, Q. Zhao, and F. C. Lee, Single-stage single-switch power factor
correction ac/dc converters with dc-bus voltage feedback for universal line
application, IEEE Trans. Power Electron., vol. 13, no. 6, pp. 10791098,
Nov. 1998.
[10] J. Qian and F. C. Lee, A high efcient single stage single switch high
power factor ac/dc converter with universal input, IEEE Trans. Power
Electron., vol. 13, no. 4, pp. 699705, Jul. 1998.
[11] L. Huber and M. M. Jovanovic, Single stage single switch isolated power
supply technique with input current shaping and fast output voltage regu-
lation for universal input voltage range applications, in Proc. IEEE Appl.
Power Electron. Conf. Expo. (APEC), 1997, pp. 272280.
[12] C. Qiao and K. M. Smedley, A topology survey of single-stage power
factor corrector with a boost type input current-shaper, IEEE Trans.
Power Electron., vol. 16, no. 3, pp. 360368, May 2001.
[13] M. H. L. Chow, Y. S. Lee, and C. K. Tse, Single-stage single-switch
isolated PFC regulator with unity power factor, fast transient response,
and low-voltage stress, IEEE Trans. Power Electron., vol. 15, no. 1,
pp. 156163, Jan. 2000.
[14] J. L. Lin, W. K. Yao, and S. P. Yang, Analysis and design for a novel
single-stage high power factor correction diagonal half-bridge forward
ac-dc converter, IEEE Trans. Power Electron., vol. 53, no. 10, pp. 2274
2286, Oct. 2006.
[15] Q. Zhao and F. C. Lee, High-efciency, high step-up DCDCconverters,
IEEE Trans. Power Electron., vol. 18, no. 1, pp. 6573, Jan. 2003.
[16] R.-J. Wai and R.-Y. Duan, High step-up converter with coupled-inductor,
IEEE Trans. Power Electron., vol. 20, no. 5, pp. 10251035, Sep. 2005.
[17] R.-J. Wai and R.-Y. Duan, High-efciency power conversion for low
power fuel cell generation system, IEEE Trans. Power Electron., vol. 20,
no. 4, pp. 847856, Jul. 2005.
[18] M. Prudente, L. L. Ptscher, G. Emmendoerfer, E. F. R. Romaneli, and
R. Gules, Voltage multiplier cells applied to non-isolated DCDC con-
verters, IEEE Trans. Power Electron., vol. 23, no. 2, pp. 871887, Mar.
2008.
[19] K. M. Smith, Jr. and K. M. Smedley, Engineering design of lossless pas-
sive soft switching methods for PWM convertersPart I: With minimum
voltage stress circuit cells, IEEE Trans. Power Electron., vol. 16, no. 3,
pp. 336344, May 2001.
[20] C. M. C. Duarte and I. Barbi, A new ZVS-PWM active-clamping high
power factor rectier: Analysis, design and experimentation, in Proc.
Appl. Power Electron. Conf. Expo. (APEC), Feb. 1998, vol. 1, pp. 230
236.
[21] H. M. Suryawanshi, M. R. Ramteke, K. L. Thakre, and V. B. Borghate,
Unity-power-factor operation of three-phase ACDC soft switched con-
verter based on boost active clamp topology in modular approach, IEEE
Trans. Power Electron., vol. 23, no. 1, pp. 229236, Jan. 2008.
Priscila Facco de Melo was born in Curitiba, Brazil,
in 1984. She received the B.S. degree in electrical en-
gineering from the Federal Technological University
of Paran a, Curitiba, in 2008, where she is currently
working toward the M.S. degree.
Her current research interests include power elec-
tronics, power quality, and digital control.
Roger Gules (M09) was born in Bento Goncalves,
Rio Grande do Sul, Brazil, in 1971. He received the
B.S. degree from the Federal University of Santa
Maria, Rio Grande do Sul, and the M.S. and Ph.D. de-
grees from the Federal University of Santa Catarina,
Florianopolis, Brazil, in 1998 and 2001, respectively.
From 2001 to 2005, he was a Professor at the
Universidade do Vale do Rio dos Sinos, Rio Grande
do Sul. Since 2006, he has been a Professor at the
Federal Technological University of Paran a, Curitiba,
Brazil. His current research interests include power-
switching converters and renewable energy applications.

DE MELO et al.: MODIFIED SEPIC CONVERTER FOR HIGH-POWER-FACTOR RECTIFIER AND UNIVERSAL INPUT VOLTAGE APPLICATIONS 321
Eduardo F elix Ribeiro Romaneli received the B.S.
degree, and the Masters and Doctorate degrees in
electrical engineering from the Federal University of
Santa Catarina, Florianopolis, Brazil, in 1993, 1998,
and 2001, respectively.
Since 2003, he has been a Full-Time Professor
at the Federal Technological University of Paran a,
Curitiba, Brazil. His research has spanned a several
disciplines, emphasizing power electronics. His cur-
rent research interests are focused but not restricted
to uninterruptible power system (UPS), power-factor
correction, and digital control.
Rafael Christiano Annunziato was born in Curitiba,
Brazil, in 1978. He is currently working toward the
degree in technology of automation at the Federal
Technology University of Paran a, Curitiba.
Since 1997, he has been with the National Health
Service (NHS) Sistemas Eletr onicos Ltda, Curitiba,
where he has been engaged in the development of
power electronics and microcontrollers rmware for
uninterruptible power system (UPS). His current re-
search interests include power converters and digital
control applied to UPS and power-correction factor.