cmos inverter design You can refer to layout example in [1] Jan Rabaey, "Digital Integrated Circuits 2nd

Edition" [2] Neil Weste, "CMOS VLSI Design A Circuits and Systems Perspective (3rd Editio n)" [3] Neil Weste, "Principles of CMOS VLSI Design" [4] Baker, "CMOS Circuit Design, Layout, and Simulation" You can use tools like LASI, Microwind, Cadence, or other EDA-CAD layout tools. Even Protel can be used. In practice, the lambda scale is used. For example, if I use a 0.18um CMOS techno logy, then the channel length is 0.18um. Therefore we use two equals to 0.18um. In practice, to design a CMOS inverter, follow the steps below: 1. Draw the diffusion layers of the PMOS and NMOS. Make sure they have the same diffusion length (not the channel length), but the diffusion width of the PMOS m ust be 2.5 times longer than the diffusion width of the NMOS. This is to compens ate the low mobility of holes by decreasing the cross-sectional channel resistan ce, in order to match the mobility of electrons. For example, both diffusion length have 10 each, the diffusion width of NMOS be 6 , then the diffusion width of PMOS be 15 in this case. 2. You can choose to place an N-well to encompass PMOS or a P-well to encompass NMOS. Normally this depends on the choice of your substrate (usually an epitaxy layer). If you use a N-type substrate, then you use a P-well for NMOS. If you us e a P-type substrate, then you use an N-well for PMOS. You need to use a metal l ayer, metal1, to connect either (1) VDD to the N-well or (2) VSS to P-well. Make sure you use multiple vias for this connection so that you can reduce the b ody effect to the minimum. If you are using an N-well for PMOS, then you have to make a contact potential using a via and metal1 that connects this well to VDD. Likewise use a via and metal1 that connects the substrate to VSS for the NMOS. Always connect this contact potential closest and around your transistor (define d by the diffusion layer). This is to reduce body effect. 3. Draw poly-Si (polysilicon) which is 2 (mask channel length, not effective chan nel length) across (1) the middle of the diffusion layer of PMOS. (2) the middle of the diffusion layer of NMOS. Notice the poly-Si you drew for PMOS is longer than the NMOS because the diffusi on layer of PMOS is longer. Make sure you make a 2 poly-Si tail or extension out of the diffusion for both NM OS and PMOS. This tail is in the opposite direction of where you will later conn ect the two poly-Si. The drain and source are on either side of diffusion layer equally divided by th e poly-Si. 4. Connect the two poly-Si you drew for PMOS and NMOS. In the centre of this con nection, make a metal1 connection using a via to your input, Vin. 5. Use metal1 and vias to connect the drain of PMOS and NMOS. This is is extende d out for your output, Vout. 6. Connect the VDD to the Source of PMOS. Connect the VSS to the Source of NMOS. Make sure you use multiple vias for these connections. This is to reduce resist ance, thus minimizes latchup.

7. Usually transistors are aligned in a very organised fashion. In digital circuits using a P-substrate or epitaxy layer, a long N-well is used where many PMOS can be placed in this long well. Therefore the VDD rail and VSS rail are parallel to both side of the well. This is to allow ease of drawing the transistors. To imagine this, try imagine a picture where you are hanging many clothes on a l ong metal bar in your wardrode.