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EE3013
Course Content
Fundamentals of Bipolar Devices MOS Devices Diffusion and thermal oxidation Ion implantation Deposition Techniques Lithography Etching (4 hours) (4 hours) (4 hours) (3 hours) (4 hours) (4 hours) (3 hours)
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TBK
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TEXTBOOK
1. Stephen A Campbell The Science and Engineering of Microelectronic Fabrication, Oxford University Press, 2001 (TK7871.85.C191 2001)
REFERENCE
1. Richard C Jaegar, Introduction to Microelectronic Fabrication: Vol 5 of Modular Series in Solid State Devices, Prentice Hall, 2002. (TK7874.J22 2002 ) 2. Michael Quirk and Julian Serda, Semiconductor Manufacturing Technology, Prentice Hall, 2003 (TK7836.Q93 )
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The Fairchilds 1st commercial planar transistor (2N1613), marketed in April 1960 4
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0.13 m MOSFET
(Courtesy of Chartered Semiconductor Mfg Pte Ltd, Singapore)
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Data transmission
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Semiconductor transistors
What is the commonest human artifact today? Not plastic bag! It is transistor! Not metal screw! Not cigarette butt!
Gordon Moore made an educated guess several years ago: 1018 (one quintillion) transistors are produced annually.
We make more transistors per year than the number of printed characters in all the newspapers, magazines, books, photocopies, and computer printouts,; And we sell these transistors for less than the cost of a character in the Sunday New York Times.
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Conventional manufacturing
Assembly - Primary method of manufacturing for engineered systems 1. Materials are processed, formed into components 2. Components are assembled together to build more complex modules 3. Materials are standardized 4. Interfaces are standardized 5. Manufacturing methods are standardized 6. Design method is mature 7. Test methods are mature
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Originally developed by NASA and the aerospace industry for satellite manufacturing. Cleanrooms now in use for all semiconductor and MEMS manufacturing.
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Semiconductor Processing
The current Si IC fabrication is using planar fabrication process Planar fabrication process: Simultaneous fabrication of many chips on a wafer, each comprising an integrated circuit (e.g. a microprocessor or memory chip) containing millions or billions of transistors
300mm Si wafer Method: Sequentially lay down and pattern thin films of semiconductors, metals and insulators.
In EE3013, starting from the basic semiconductor devices, we are going to learn the fabrication process for semicondctor devices and ICs
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Red LED
Photodetector
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EC
N
Ei EV
_ + _ +
N
p n
Majority carriers diffuse across the junction, leaving ionized dopants - establishing a field. The field causes drift currents and opposes diffusion, so that the net current is zero.
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Carrier Drift
minority
E
e e
p-region
qVbi
EF
majority hole diffusion
h h h
n-region
minority
EV
The built in field will sweep minority carriers across the junction. Electrons drift from p to n, shown below). Drift velocities are ve = e E , vh = h E Drift current densities are of the form
J e = qnve
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Carrier Diffusion
Carriers diffuse from high to low concentrations (so n to p for electrons).
F = D
For holes and electrons
dC dx
dp dn , J e ( diff ) = qD e dx dx
J h ( diff ) = qD h
The positive and negative signs indicate the direction of the current with respect to the carrier gradient - Recall: De = e(kBT/q) (Einstein relation), where me, electron mobility is a measurable parameter.
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where m is the mobility of the carriers, (measured in cm2V-1 s-1), and n and p are carrier densities (cm-3), J is current per unit area. In equilibrium, no net charge accumulation J h = J e = 0 We know the number of electrons in p-type and n-type material. In equilibrium, it is possible to derive the expression to show that Fermi level in the p-n junction is constant at thermal equilibrium. (See notes page 4)
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Similarly, Therefore,
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Transition region: the space charges of impurity ions are partially compensated by the mobile carriers. The transition region is thin can be neglected Rectangular Approximation of Space-charge region or depletion region: mobile carrier densities are zero.
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Depletion Region
Abrupt junction: Formed when there is an abrupt transition of doping between n- and p- regions; Linearly graded junction: Formed when the impurity distribution varies linearly across the junction.
Abrupt junction
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The maximum electric field m that exists at x = 0 is given by This can be derived using Poissons equation.
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q(Vbi VF )
+
minority e
_
VF
e Majority diffusion e EC FN
p-region
FP h Majority diffusion h
n-region
h minority EV
qV =F F F N P
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I V
_
minority e
+
VR
q(Vbi+VR) EC FN EV School of EEE, NTU
p-region
FP h majority h h minority
majority e
n-region
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Depletion capacitance
The depletion capacitance per unit area is defined as
Cj = dQ/dV,
where dQ is the incremental change in depletion layer charge per unit area for an incremental change in the applied voltage dV.
This equation for the depletion capacitance per unit area is the same as the standard expression for a parallel-plate capacitor where the spacing between the two plates represents the depletion layer width. This equation is valid for any arbitrary impurity distribution.
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Capacitance-Voltage characteristics
For one-sided abrupt junction,
Or
A plot of 1/Cj2 versus V produces a straight line for a onesided abrupt junction. The slope links to the impurity concentration NB and the intercept (at 1/Cj2 = 0) gives Vbi.
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