10 1 1 111

UNIVERSITY OF CALIFORNIA
Santa Barbara

Wireless Data Interface for
Cryogenic Imaging Arrays

A Thesis submitted in partial satisfaction of the
requirements for the degree of Master of Science in
Electrical and Computer Engineering

by

Ryan Garrett Conolley

June 2003

Committee in charge:

Professor Stephen I. Long, Chairman
Professor Steven E. Butner
Professor Upamanyu Madhow

The thesis of Ryan Garrett Conolley is approved.

_____________________________________________
Professor Stephen Long, Committee Chair

_____________________________________________
Professor Steven E. Butner

_____________________________________________
Professor Upamanyu Madhow

June 2003

iii
Acknowledgment

I would like to gratefully and emphatically thank my advisor, Dr. Stephen I. Long for his
tremendous assistance on this project. His insightful guidance, patient supervision and
technical expertise were instrumental towards the success of this project. Dr. Longs
consistent support and encouragement were both comforting and greatly appreciated.
Additionally I give many thanks to James Peterson for our productive collaboration and
for countless hours of time spent in the lab on this project.

Raytheon Infrared Operations deserves particular acknowledgment for the initial support
of this work under the Raytheon University Research program and subsequent joint
funding under the UC MICRO program. Dr. Leonard P. Chen has made many significant
technical suggestions that have helped to shape this design effort through our frequent
discussions.

The UCSB Electrical and Computer Engineering Department deserves special
recognition. In the six years I have attended UCSB, the faculty have been more
consistently supportive and helpful than I could ever ask for. My friends on the faculty
and staff in addition to my classmates have made me fell at home above and beyond the
call of duty.

I would like to thank Dr. Steven E. Butner and Dr. Upamanyu Madhow for taking
precious time out of their busy schedules to read this work.

Finally, I would like to dedicate this work to my parents. Without their incredible support
and selfless caring, I could not have made it though this difficult process. This is true on
multiple dimensions and for this I am sincerely and forever grateful.

iv
Table of Contents

1. Introduction................................................................................................................. 8
2. Detailed Statement of the Problem............................................................................. 8
2.1 Feasibility Study on Low Power Wideband Data Link ...................................... 9
2.2 Proposed Transmitter ........................................................................................ 12
3. Transmitter Architecture........................................................................................... 14
3.1 Overview........................................................................................................... 14
3.2 Circuit Implementation..................................................................................... 15
3.2.1 Differential Oscillator ................................................................................... 15
3.2.2 Clock Divider ................................................................................................ 19
3.2.3 Digital Front-End Multiplexing .................................................................... 29
3.2.4 Six-Phase Clock ............................................................................................ 31
3.2.5 Single-Ended to Differential (S2D) Conversion........................................... 36
3.2.6 Polyphase Filter............................................................................................. 37
3.2.7 Mixer ............................................................................................................. 41
3.3 Simulation of the Clock and LO Section.......................................................... 43
3.4 Simulation of the Baseband to RF Output ........................................................ 45
3.4.1 Power Budget ................................................................................................ 48
3.5 Cryogenic Temperature Issues.......................................................................... 48
3.6 Transmit Antenna.............................................................................................. 49
4. System Synchronization............................................................................................ 50
4.1 Synchronization Issues...................................................................................... 50
5. Transmitter Integrated Circuit Layout ...................................................................... 53
5.1 Transmitter Overview....................................................................................... 54
5.2 Section Details .................................................................................................. 56
5.2.1 Differential Oscillator ................................................................................... 56
5.2.2 Clock Divider ................................................................................................ 60
5.2.3 Digital Front-End Multiplexing .................................................................... 63
5.2.4 Single-Ended to Differential Conversion...................................................... 67
5.2.5 Polyphase Filter............................................................................................. 71
5.2.6 Mixer ............................................................................................................. 75
5.2.7 Remaining IC Issues ..................................................................................... 77
5.3 Integrated Circuit Design for Testability.......................................................... 79
5.3.1 Test Plan and Test Structures........................................................................ 80
6. IC Interface Printed Circuit Board............................................................................ 87
7. Testing Results.......................................................................................................... 90
7.1 TLM Resistor Measurements............................................................................ 90
7.2 Differential Oscillator ....................................................................................... 93
8. References ................................................................................................................. 96

v

Table of Figures

Figure 1: Simplified Quadrature modulator block diagram.............................................. 11
Figure 2: General overview of the communication system [1]......................................... 11
Figure 3: Overview diagram of the QPSK transmitter illustrating the input multiplexing
................................................................................................................................... 13
Figure 4: Detailed block diagram of the QPSK transmitter illustrating the specific
functional areas to be designed. ................................................................................ 14
Figure 5: Circuit Schematic of Differential Oscillator ..................................................... 16
Figure 6: Oscillator output waveform taken differentially ............................................... 17
Figure 7: Detail of the oscillator output waveform taken differentially ........................... 18
Figure 8: Spectrum of the oscillator output ...................................................................... 19
Figure 9: Detail of the oscillator output waveform taken single-ended............................ 19
Figure 10: Block diagram of divide-by-twelve implementation....................................... 20
Figure 11: Schematic of SCL divide-by-two .................................................................... 21
Figure 12: Simplified schematic of the SCL divide-by-two ............................................. 22
Figure 13: Schematic of TSPC flip-flop used as a divide-by-two .................................... 23
Figure 14: Schematic of TSPC divide-by-three................................................................ 24
Figure 15: Output signals on different nodes of the TSPC divide-by-three ..................... 25
Figure 16: Clock divider output waveforms ..................................................................... 25
Figure 17: Dynamic latch divider ..................................................................................... 26
Figure 18: Dynamic latch divider ..................................................................................... 27
Figure 19: NOR based divide-by-three............................................................................. 27
Figure 20: And based divide-by-three .............................................................................. 28
Figure 21: Cascaded D- flip-flop divide-by- four ............................................................... 28
Figure 22: Asynchronous cascaded D- flip-flop divide-by- four........................................ 28
Figure 23: Detail of the front-end digital multiplexing .................................................... 29
Figure 24: Multiplexer schematic diagram....................................................................... 30
Figure 25: T-gate schematic in ADS ................................................................................ 30
Figure 26: Six-to-one multiplexer schematic in ADS....................................................... 31
Figure 27: Timing diagram of the six-phase clock used in the front-end multiplexer ..... 32
Figure 28: Shift register to generate the six-phase clocking signals................................. 32
Figure 29: Schematic of the six-phase clock configuration.............................................. 33
Figure 30: Schematic of D-Flip-Flop with Synchronous Set............................................ 34
Figure 31: Schematic of D-Flip-Flop with Synchronous Reset ........................................ 35
Figure 32: Simulation of the six-phase clock illustrating the initial state machine reset
phase.......................................................................................................................... 36
Figure 33: Single-Ended to Differential Converter (S2D) Schematic .............................. 37
Figure 34: Polyphase network and one stage of the final circuit implementation............ 38
Figure 35: Resistor modeling with provided spice data for the polyphase network......... 39
Figure 36: One-stage polyphase filter network................................................................. 39
Figure 37: Polyphase phase relation between the I and Q outputs at 2.4 Ghz for multiple
polyphase stages over variations in the RC time constant ........................................ 40
Figure 38: Three-stage Polyphase structure schematic in ADS........................................ 41
Figure 39: Gilbert Mixer Schematic ................................................................................. 42
vi
Figure 40: Blocks included in the clock and LO simulation............................................ 43
Figure 41: Results of the Clock and LO simulation......................................................... 44
Figure 42: Simulation of the quadrature carriers .............................................................. 45
Figure 43: Blocks included in the baseband to RF output path........................................ 45
Figure 44: Data out of the Q-channel and I-channel multiplexer ..................................... 46
Figure 45: Q channel data output of the multiplexer and S2D......................................... 46
Figure 46: Q channel data output of the multiplexer and S2D......................................... 47
Figure 47: QPSK Output................................................................................................... 47
Figure 48: Printed dual feed microstrip patch antenna [] ................................................. 50
Figure 49: Synchronization issues in a digital communication system............................ 50
Figure 50: Overview diagram of the QPSK receiver illustrating the carrier and symbol
timing recovery blocks.............................................................................................. 51
Figure 51: Effect of phase reference error on the In-phase signal correlator ................... 52
Figure 52: Effects of timing jitter (a) on the oscillator phase (b) on the QPSK signal
constellation.............................................................................................................. 53
Figure 53: Complete transmitter in relative proportion to the overall die size................. 54
Figure 54: Complete IC layout illustrating the room temperature and low temperature
transmitter sections ................................................................................................... 55
Figure 55: Transmitter layout overview and organization................................................ 56
Figure 56: Oscillator circuit schematic ............................................................................. 57
Figure 57: Oscillator cross-coupled feedback pair layout ................................................ 57
Figure 58: AC equivalent of the oscillator resonator network.......................................... 58
Figure 59: Oscillator layout illustrating the output connections to the bond pads ........... 59
Figure 60: Metal 4 routing over Metal 1 for resonator capacitor ..................................... 59
Figure 61: Simple ESD protection circuit......................................................................... 60
Figure 62: Clock divider block diagram........................................................................... 61
Figure 63: SCL Divide-By-Two circuit schematic........................................................... 61
Figure 64: First clock divider stage the SCL Divide-By-Two Layout .......................... 62
Figure 65: TSPC Clock Dividers Divide-by-six chain circuit schematic ...................... 63
Figure 66: TSPC Divide-by-six chain layout .................................................................... 63
Figure 67: Data multiplexing block diagram.................................................................... 64
Figure 68: Six Phase Clock layout .................................................................................... 64
Figure 69: General Star-cluster layout .............................................................................. 65
Figure 70: Organization and signal flow of the six-phase clock and data multiplexers ... 65
Figure 71: TSPC Clock Dividers and Multiplexer Layout ............................................... 67
Figure 72: Differential converter circuit schematic ......................................................... 68
Figure 73: Common-centroid layout used to implement the S2D resistors ...................... 68
Figure 74: Layout of the differential converter................................................................. 69
Figure 75: Circuitry to bias the second half of the differential converter......................... 70
Figure 76: Bypass MOS capacitor .................................................................................... 70
Figure 77: Overall configuration of the differential converters ........................................ 71
Figure 78: Single Polyphase stage circuit schematic........................................................ 71
Figure 79: Single Polyphase Stage illustrating the capacitor layout ................................. 72
Figure 80: Common-centroid layout for matching four structures ................................... 72
Figure 81: Common-centroid four capacitor layout ......................................................... 73
Figure 82: Capacitor used for the polyphase structure ..................................................... 74
vii
Figure 83: Common-centroid layout used for the polyphase filter resistors .................... 74
Figure 84: Polyphase resistor layout ................................................................................. 75
Figure 85: Layout of the three-stage Polyphase network ................................................. 75
Figure 86: Gilbert cell double-balanced mixer circuit schematic..................................... 76
Figure 87: Single Mixer layout ......................................................................................... 76
Figure 88: Final layout of the two mixers illustrating the input/output connections ........ 77
Figure 89: Separation of the digital and analog supplies .................................................. 78
Figure 90: On-chip bypass capacitors ............................................................................... 78
Figure 91: IC design considerations for testability........................................................... 79
Figure 92: Test Section 1 oscillator and polyphase ....................................................... 81
Figure 93: Off-chip inductor configuration on the PCB test fixture................................. 82
Figure 94: Test Section 3 Low Temperature Transmitter.............................................. 83
Figure 95: Test Section 4 section 4 will be tested by rotating the IC 180 degrees ........ 83
Figure 96: Test Section 5 Divide-by-six (missing the first stage divide-by-2) clock
divider and input multiplexer test structure .............................................................. 84
Figure 97: Test Section 6 Divide-by-twelve clock divider and input multiplexer test
structure..................................................................................................................... 85
Figure 98: Test Section 7 Resistor test structures .......................................................... 86
Figure 99: Test Section 8 Transistor test structures ....................................................... 87
Figure 100: PCB for IC mounting and interfacing ........................................................... 87
Figure 101: Detail of the PCB test fixture ........................................................................ 88
Figure 102: PCB layer definitions and construction (dimensions in inches).................... 89
Figure 103: Model and simulation results of loading the RF output with the ESD resistor
................................................................................................................................... 90
Figure 104: General TLM Plot of Measured Resistance .................................................. 91
Figure 105: TLM N-diffusion resistor measurement ........................................................ 92
Figure 106: TLM N-well resistor measurement ............................................................... 92
Figure 107: Transmission line adjustment mechanism to tune the oscillator tank inductor
................................................................................................................................... 93
Figure 108: Measured oscillator output taken from one of the four polyphase filter
outputs....................................................................................................................... 93
Figure 109: Measured oscillator illustrating the presence of second harmonic................ 94
Figure 110: Simulated oscillator spectrum taken from one of the four polyphase filter
outputs....................................................................................................................... 94
Figure 111: Measured phase shift between the 0and 90 outputs of the polyphase filter95
Figure 112: Measured output from the six-phase synchronization signal ........................ 95
8
1. Introduction
Transmission of data from an infrared focal plane sensor array to the external image
processing circuitry has traditionally required a wired or fiber optic connection. Heat
conduction in such a system is a fundamental concern since the sensor array and readout
IC are maintained at a low temperature (80 K). Maintaining this temperature is crucial in
reducing dark current and self-referenced noise pickup. Heat is generated in the form of
interconnect losses through the cryogenic container through resistive loss in the wired
interconnections or the conversion loss to optical fiber. As a result, power dissipation in
the readout interface must be minimized.

In this work, a wireless data transmission interface between the sensor array and the
external image processing circuitry outside the cryogenic container has been studied,
designed, fabricated and tested. The principal challenge was to design a transmitter that
dissipates less power than multiple wired interconnects would demand. Because the
transmission distance is small, very low RF power can provide a reliable bit error rate.
This has facilitated a simple modulator architecture that effectively expends minimal DC
power while maintaining throughput specifications. An RF integrated circuit (IC) and
printed circuit board (PCB) test fixture were designed and fabricated in order to assess
the functionality of the proposed design.

In what follows a wireless transmitter is presented from a system level proposal, through
the analysis and simulation, to the final test and measurement. A detailed statement of the
problem is presented in Section 2. In this section the system specifications and challenges
are examined and the proposed solution is outlined. The design objectives are followed in
Section 3 with a comprehensive look at the transmitter architecture where the
implementation and design of the major circuit blocks is presented. The receiver portion
of the data link has also been investigated in relation to the transmitter, since clock and
symbol timing relationships create a fundamental issue in digital communication systems.
Section 4 illustrates these issues in relation to the role the transmitter plays in overall
system performance. Section 5 describes the layout of the transmitter IC prototype and
how the major components presented in Section 3 translate into the physical realization
on the IC. The PCB test fixture is presented in Section 6. Lastly, the tests and
measurements performed on the IC prototype are presented in Section 7.
2. Detailed Statement of the Problem
Capturing information from an infrared focal plane detector involves raster scanning,
multiplexing and converting the data from an analog to digital format by an
accompanying Readout IC. This data must them be transferred to an external image
processing unit for analysis. Since the sensor array and readout IC must be operated at
cryogenic temperatures, heat conducted through the interconnections to the external
image processing unit creates a heat load on the cryogenic cooling system. The power
efficiency of cryogenic cooling systems is very low, and any additional head load created
by such interconnections increases the power requirements for the overall system.
9
An RF wireless data link would eliminate the thermal conduction problem of the wired
interface. If the wireless link can be implemented on the Readout IC, and if the link can
reduce the overall system power requirements, it may be a good alternative to the wired
data connection. For the large imaging arrays targeted for this application, the additional
heat generated by the wired interconnects is estimated to generate over 10mW of power.
Therefore, to provide a better solution, the design goal for the wireless data link is to
dissipate less than 10mW of power.

In addition to the power constraint on the RF wireless data link, a high bandwidth is
required. Typical infrared focal plane sensor arrays consist of 1024 1024 pixels per
frame. Future generations of such arrays are likely to quadruple in size to 2048 2048
pixels per frame. Data from each pixel has conventionally been quantized to a parallel
output of 12 bits. For a typical infrared focal plane sensor and a frame rate of 30Hz, a
data rate of just below 380 Mbps is required. This data rate requires a broadband solution
and a carrier frequency in the low GHz. The 0.35m CMOS transistors have high
enough f
t
and f
max
that these data bandwidths and carrier frequencies are feasible.
The challenges in designing such a wireless link are in selecting a bandwidth efficient
digital modulation technique and implementing the transmitter within a low power
budget. The power budget limitation is especially difficult for high-speed digital logic,
where dynamic power is directly proportional to the signal frequency.
2.1 Feasibility Study on Low Power Wideband Data Link

A feasibility study was performed [1] to ascertain the specific difficulties in
implementing such a challenging project. In this work the design space was reduced by
defining explicit realization strategies and resolving some of the power budget
restrictions. As a result of this study, several important resolutions were made:
A modulation scheme was chosen
Major circuit block topologies were studied
Based upon the system-level simulations of the major circuit blocks, the power
budget was determined to be tolerable

In choosing the modulation scheme, several important issues were carefully considered:
A reasonably bandwidth efficient modulation scheme is needed due to the high
data rate and low power budget
Highly bandwidth efficient modulation schemes require complex modulator
architectures, which increases power consumption

As a result of the trade-off made between the above issues, Phase-Shift Keyed (PSK)
modulation was chosen. PSK modulators are relatively simple in hardware design and
reasonably power efficient. In addition, multi-bit symbols can be transmitted, allowing
the system designer to achieve higher bandwidth efficiency while retaining modulator
simplicity.

In digital communication systems, the power and spectral efficiency are among the most
important system requirements. This is especially true for systems that require a
10
maximum RF to DC power ratio. Quadrature PSK (QPSK) combines two bits (called the
In-Phase (I) and Quadrature (Q) bits) per symbol and will be the modulation scheme used
in this work. QPSK is frequently used in high- and medium-speed wireless systems
because of its 2-bit/s/Hz theoretical (1.5- to 1.8-bit/s/Hz practical) bandwidth efficiency
[2]. In addition, QPSK boasts low energy per bit over noise spectral density requirements
for good error probability performance, and a relatively simple hardware design. Higher
order M-ary PSK modulation schemes where rejected since the architecture becomes
increasingly complex as higher order symbols are used. While it is true that higher order
PSK modulation are more bandwidth efficient, these schemes require higher signal to
noise ratio. In our power-limited system, the trade-off was made in favor of power
efficient modulation at the expense of bandwidth.

Since this application involves a low power single transmission signal environment, some
of the negative issues with using QPSK are avoided. A certain amount of filtering at the
transmitter is often needed in digital modulation systems. This is required since sidelobe
levels in the power spectra may cause interference with adjacent channels. The filtering
process increases envelope fluctuations which can be problematic in high power
applications where the nonlinear effects of the transmit amplifier cause spectrum
spreading and tend to reintroduce spectral sidelobes. It is possible to filter the
transmission at the output of the transmit amplifier, but in general this is undesired since
this would require impractically high-Q filters at the transmitters output. For these
reasons, QPSK is not a very attractive solution for many power and spectral efficient
applications.

In this work, we avoid the necessity of filtering and the nonlinear effects of high power
amplifiers since the data channel environment is precisely controlled. The channel
distance is very short since the data only needs to be transmitted from the center of the
cryogenic container to its sidewall. Being in a closed container also eliminates the
concern of interference with other channels. Padding the container with RF absorbing
material may mitigate multi-path reflections off the container walls. This will greatly
simplify the design considerations and the transmitter architecture.

A carrier frequency of 2.4Ghz was selected since this frequency is high enough to
encompass the data rate requirements and the 0.35m technology operates adequately in
this regime. Most importantly, the 2.4Ghz carrier facilitates the potential use of
commercially available receiver hardware built for 2.4Ghz WLAN/802.11b/ISM
applications. The availability of commercial hardware should assist in a timely design of
a receiver prototype.

A simplified view of a common QPSK transmitter architecture [3] is illustrated in Figure
1. Two binary data streams are applied to a set of mixers. Also applied to the mixers are
two RF carriers with a relative phase difference of ninety degrees. Finally, the outputs of
the mixers are summed for transmission.

11

Figure 1: Simplified Quadrature modulator block diagram

From Figure 1, it is evident that the following blocks are needed:
Oscillator
Phase Shifter to achieve the sine and cosine carrier inputs
Mixers
A multiplexer to translate the twelve-bit parallel data stream from the Readout IC
into two serial data streams (the I and Q data inputs)

A simplified view of the QPSK demodulation process is the reverse process shown in
Figure 1. The received signal is applied to a set of mixers with the same RF carriers as in
the transmitter. This output is low-pass filtered and sampled to recover the data bits.

A general overview of the complete communication system investigated in this work is
shown below in Figure 2.

NRZ
NRZ
COS
SIN
COS
SIN
Demodulator
Modulator Channel
VtLFSR_DT
SRC8
DT
LPF_Chebyshev
LPF4
VtLFSR_DT
SRC7
DT
LPF_Chebyshev
LPF3
Mixer
MIX1
Mixer
MIX2
VSum
SUM1
P_1Tone
PORT2
P_1Tone
PORT1
P_1Tone
PORT3
P_1Tone
PORT4
R
R1
R=50 Ohm
LPF_Chebyshev
LPF1
Mixer
MIX3
BPF_RaisedCos
BPF3
R
R2
R=50 Ohm
LPF_Chebyshev
LPF2
Mixer
MIX4
BPF_RaisedCos
BPF4
BPF_RaisedCos
BPF2

Figure 2: General overview of the communication system [1]

The power budget is the primary driving force behind the circuit implemenation of the
transmitter section of this communication system. The DC power consumption is directly
related to the RF output power and a tradeoff will need to be made in order to meet the
12
power budget specifications. An output transmission power calculation was performed
with the following parameters:

Parameter Value
Symbol rate, f
b
160 Mb/s
Receiver bandwidth, B 1 GHz
Receiver noise figure, NF 10 dB
Channel attenuation, Ch_atten 5 dB
Bit Error Rate, BER 10E-9
E
b
/N
o
18

The calculation yields a required transmission power of only 0.4 nW to complete the link
with the specified BER (systems often require an E
b
/N
o
up to 3dB above the theoretical
value [2] to compensate for practical non-idealities). It is clear that the system power
budget will be dominated by the modulator, oscillator, and associated clock generation
circuitry. Transmission power is not an obstacle that constrains the system design.
2.2 Proposed Transmitter
As shown in the prevoius section, the proposed wireless signal interface is theorectically
feasable. To complete the study, a comprehensive transmitter architecture needs to be
designed, analyzed and simulated. The simplified block diagram presented in Figure 1
and the design considerations given in the previous section provide most of the
inspiration for completing the proposed transmitter. There are several important
considerations that have not been mentioned. The bit rate and carrier frequency
relationship needs to be established in addition to generating the bit clock and input data
multiplexor.

For simplicity in deriving the theoretical performance of QPSK systems, it is often
assumed that the carrier frequency is an integer multiple of the bit rate, that is
b
c
T
n
f .
The bit source in our application is the output of the Readout IC, the interface between
the imaging array and our wireless data link. If the carrier frequency were to be locked
onto an output bit clock or the output data from the Readout IC, fluctuations of this
source (
b b
f f t ) would be translated into fluctuations of both the unmodulated carrier
frequency (
b c
f n f t ) and of the modulated spectrum. For the complete communication
system, such fluctuations would be overly restrictive.

Fortunetly, we can avoid system complications by observing two central points. First, it is
not entirely esential to have the unmodulated carrier locked to an integer multiple of the
bit rate (f
c
nf
b
). While this does degrade performance from a bit error rate perspective,
the typical degredation is virtually negligable, espcially if
b c
f f 10 > [4]. Secondly, there
13
are currently no provisions on the Readout IC for presenting an output bit clock to the
transmitter for phase locking to the bit period. While the transmitter could employ a
phased-locked-loop to perform the necessary locking sequence, it was feasible to reverse
the problem and provide the Readout IC with a bit clock derived from our transmitter. If
maximum perfromance is necessary, the Readout IC could derive a synchronous bit clock
from this transmitter output. This will ensure that bit rate fluctuations are limited to
fluctuations in the transmitters carrier frequency. This method eliminates the need to
phase-lock any signals at the transmitter, thus reducing the transmitters complexity.

The input data multiplexing is explicitly shown in relation to the local oscillator in Figure
3. The oscillator will be used as a clock reference when performing the twelve-bit-
parallel to two six-bit-serial conversions.

Mux Oscillator
12 Data
Inputs
Page 1
Overview Diagram of the QPSK Transmitter
In - Phase (I)
Quadrature (Q)
0
90
o
o

Figure 3: Overview diagram of the QPSK transmitter illustrating the input multiplexing

From the previous discussion and the bit and carrier frequency relationship, it is evident
that a clock divider is needed for this transmitter. In addition to the circuit blocks listed in
Section 2.1, a clock divider will be needed to translate the 2.4Ghz local oscillator used as
carrier inputs to the mixers, down to the I / Q data rate for the input multiplexer.
Referring to Figure 3, the prescaler would take the oscillator output and provide the
proper clock signal to the multiplexer. The proper prescaler divisor needs to be selected.
Recall that a data rate of at least 380Mbps is required to meet the specified frame rate for
current generation imaging arrays. Since there are two bits per symbol, the I / Q symbol
rate is one half of the bit rate, or 190Mhz. The closest integer yielding a satisfactory data
rate is twelve, offering a symbol rate of 200MHz:

( )
MHz
Ghz f
f
sc o
s
200
12
4 . 2
(1)

At this point in the feasibility study, specific circuit implementations of the necessary
transmitter blocks were investigated. The design originally investigated went through
14
several revisions and modifications before the final version was ready for IC layout. For
coherency, we will only present the final design of the transmitter circuit blocks and
selective design iterations where appropriate.
3. Transmitter Architecture
The feasibility study and subsequent investigations into available circuit topologies led to
the choice of transmitter blocks as listed in Table 1.

Table 1: Chosen circuit block topologies for the main transmitter components
Transmitter Circuit Block Design Topology
Oscillator Differential Negative Resistance Oscillator
Clock Divider SCL and True Single Phase Clock (TSPC) [5,6,7]
Mixer Gilbert Cell Double-Balanced Mixer
3.1 Overview
The choice of circuit implementation for the main transmitter components yields the
detailed block-level transmitter diagram shown in Figure 4.

6-to-1 Mux
6-to-1 Mux
Single
Ended to
Differential
Single
Ended to
Differential
Differential
Oscillator
Prescaler
Clock
Divider
Six Phase
Clock
6 Data
Inputs
6 Data
Inputs
Page 1
Block-Level Detail of the QPSK Transmitter
0
90
o
o

Figure 4: Detailed block diagram of the QPSK transmitter illustrating the specific
functional areas to be designed.

As previously described, data transmission using QPSK requires the incoming parallel
data bits to be multiplexed into serial I and Q data streams. The twelve parallel bits are
split into two six-bit sections where these six bits are multiplexed into one single-ended
serial output. A six-phase clock is used to select one of the six data inputs for each
multiplexer. The symbol clock, derived by dividing oscillators output frequency, is used
to operate the six-phase block. Differential to single-ended conversion of the differential
oscillators output is naturally accomplished through a Source Coupled Logic (SCL)
divider integrated at the front end of the clock divider. Since the Gilbert Cell mixers have
differential inputs, single-ended to differential conversion of the I and Q data streams
needs to be performed. Taking the oscillators output through an RC Polyphase Filter
15
yields the quadrature carrier signals used to drive the mixers. The final output is taken
into a differentially fed antenna for transmission.
3.2 Circuit Implementation
This section describes the specific circuit implementation, design, simulation and analysis
of the QPSK transmitter illustrated in Figure 4. Since the final application targeted for
this work is in cryogenic temperature environments, low temperature device models were
extracted for simulation purposes. BSIM3 device parameters were obtained through
testing performed at Raytheons Vision Systems in Goleta, California. Verification of the
design utilized Agilents ADS Analog/RF circuit simulation software.

The description will be organized as follows. Section 3.2.1 will begin at the center of the
transmitter describing the differential oscillator. This is followed by the clock divider
circuitry in Section 3.2.2. The focus moves towards the front-end of the transmitter with
the six-phase-clock in Section 3.2.2.3 and the input multiplexer in Section 3.2.3. Section
3.2.5 describes the conversion of data out of the multiplexer from single-ended to
differential signaling. This data is then fed to the mixers along with the quadrature carrier
signals. The phase shifting circuitry necessary for generating the two quadrature carrier
signals is described in Section 3.2.6 followed by the mixer in Section 3.2.7. Throughout
this section, device dimensions will be given in integer multiples of the draw dimension
=0.2m, the scalable resolution parameter in CMOS design.
3.2.1 Differential Oscillator
The local oscillator is the heart of the transmitter system. It provides both the desired
carrier signal, and the source from which data synchronization is derived.

The oscillator design solution consists of a simple differential negative resistance
oscillator [8]. The differential oscillator topology provides a differential signal input to
both the clock divider, and the polyphase filter. The differential oscillator was chosen
since this circuit easily provides a negative resistance and is a popular choice for IC
oscillators. This topology is also easily integrated with the polyphase filter and mixer due
to the availability of differential outputs. From a system level, the output spectrum should
be as pure as possible in terms of phase noise. In general there are two ways to achieve
enhanced phase noise in LC oscillators:

Increase the output voltage swing
Increase the quality factor, Q, of the resonator

These two issues will be discussed in specific relation to the differential oscillator while
the system level issues of phase noise and timing jitter are differed to Section 4.

Figure 5 illustrates the final design of the oscillator.
16
osc- osc+
Vdd
PRL
PRL1
L=19 nH
R=2865 Ohm
PRL
PRL2
L=19 nH
R=2865 Ohm
Port
osc+
MOSFET_NMOS
MOSFET12
Width=W_n2
Length=Ln
ItPulse
SRC4
Period=10000 nsec
Width=2 nsec
Fall=1 nsec
Rise=1 nsec
Edge=linear
Delay=0 nsec
I_High=0.1 mA
I_Low=0 mA
MOSFET_NMOS
MOSFET9
Width=W_n
Length=Ln
MOSFET_NMOS
MOSFET13
Width=100e-6
Length=Ln
MOSFET_NMOS
MOSFET8
Width=W_n
Length=Ln
Port
osc-
MOSFET_NMOS
MOSFET11
Width=W_n2
Length=Ln
MOSFET_NMOS
MOSFET14
Width=100e-6
Length=Ln
MOSFET_NMOS
MOSFET10
Width=W_n_cs
Length=Ln
R
R1
R=1 kOhm
Cntrl
C
C1
C=115 fF
Port
p wr
Num=1

Figure 5: Circuit Schematic of Differential Oscillator

The design variables for the oscillator schematic of Figure 5 are listed in Table 2.

Table 2: Differential Oscillator schematic variables
Supply Voltage 3.3 V
Transistor Length, Ln 0.4 m
Bias Current, I
bias
0.5 mA
Transistor Width, W_n 100 m
Current Source Transistor Width, W_n2 1 m
Current Source Transistor Width, W_n_cs 1 m
Level Shift Transistor Width 100m
Resonant Frequency, f
0
2.4Ghz

As shown in Figure 5, the basic oscillator operation is performed by the cross-coupled
transistor pair of MOSFET8 and MOSFET9 where the oscillation frequency is
determined by the resonator tank. The oscillators differential outputs are labeled osc+
and osc-.

17
In order to meet startup conditions, the following condition must be satisfied:

m
p
g
R
1
>
(2)

where R
p
is the parallel resistance of the resonant network and g
m
is the transconductance
of both cross-coupled inverter transistors. The resonant network has an oscillation
frequency given by

L C
f
T
2
1
0

(3)

where L is the resonant network inductance and C
T
is given by

GS T
C C C + 2 (4)

where C is the capacitance shown in Figure 5 and C
GS
is the gate to source parasitic
capacitance on the cross-coupled transistors . For design purposes, it is initially assumed
that
GS
C C >> 2 and the resonant network has Q=20. The transistor width, W_n, was
chosen to easily meet the startup conditions given in Eq. 2 for the assumed value of
inductor Q.

The final resonant network values ultimately depend on what can be physically realized
on the IC prototype. This will be discussed in Section 5.2.1.

The oscillator output is shown in Figure 6 and Figure 7.

Figure 6: Oscillator output waveform taken differentially

18

Figure 7: Detail of the oscillator output waveform taken differentially

The output swing can be approximated by [9]:

( ) / 2
p bias peak
R I V (5)

where R
p
is the parallel resistance of the resonator tank. As previously mentioned, the
phase noise can be improved by increasing the output voltage. There are two ways to do
this, by increasing I
bias
or by increasing R
p
. Increasing the bias current directly increases
the oscillators power consumption and is not a viable option for this application. The
parallel resistance of the resonator tank is therefore the best way to improve the
oscillators phase noise. Unfortunately, on-chip inductors in CMOS suffer from low Q
and hence low R
p
. For this reason we decided to implement the tank inductance off-chip,
hoping to provide a higher Q resonator and lower the phase noise. The phase noise
analysis of the differential oscillator has been differed to Section 4.1.

The output spectrum of the oscillator was evaluated from a transient simulation. As
shown in Figure 8, the spectrum is free from second harmonic energy but is spread
around the 2.4Ghz nominal frequency.
19

Figure 8: Spectrum of the oscillator output

In order for the oscillator to properly interface with the mixer, the oscillator output needs
to be level shifted to the proper DC value. The level shifting is accomplished through the
diode-connected transistors MOSFET13 and MOSFET14. The transistor widths were
chosen to provide adequate channel resistance and resulting voltage drop setting the DC
level at about 1.35V. Figure 9 illustrates the output waveform taken from one of the
differential outputs. The DV level shift and mixer interfacing is further discussed in
Section 3.2.7.

Figure 9: Detail of the oscillator output waveform taken single-ended
3.2.2 Clock Divider
The clock divider is used to derive the 200 MHz symbol clock used to drive the front-end
multiplexers from the local oscillator. Since the oscillator is designed at 2.4 GHz, a
divide-by-twelve needs to be implemented to produce the 200 Mhz clocking frequency.
The divide-by-twelve scheme was implemented in three stages:
20
1. SCL divide-by-two to produce a 1.2 GHz signal,
2. TSPC divide-by-two to produce a 600 MHz signal
3. TSPC divide-by-three to produce the final 200 MHz clocking signal

The clock divider chain and intermediate signal frequencies are illustrated in Figure 10.

Six Phase
Clock
Oscillator
6 Clock
Signals
Page 1
Divide-By-Twelve Clock Divider
SCL Divide
By Two
TSPC
Divide By
Two
TSPC
Divide By
Three
6 Clock
Signals
6-to-1 Mux
6-to-1 Mux
Q Data
I Data
6 Data
Inputs
6 Data
Inputs
2.4 Ghz
1.2 Ghz
600 Mhz 200 Mhz
200 Mhz
200 Mhz
Divide-By-Twelve
33 Mhz
33 Mhz

Figure 10: Block diagram of divide-by-twelve implementation

An attempt was made to design all of the digital circuitry shown in Figure 10 (all except
for the oscillator) at an increased gate length. A gate length of 0.6 m was used where
possible in an attempt to mitigate low temperature reliability issues such as hot carrier
effects. These issues will be further discussed in Section 3.5. Using a gate length above
the minimum value of 0.4 m was not feasible for the SCL divide-by-two or the TSPC
divide-by-two due to the high operating frequencies. In every subsequent stage (TSPC
divide-by-three, six-phase clock and input multiplexers), a gate length of 0.6 m was
feasible and used in the IC layout.
3.2.2.1 SCL Divide-by-Two
The first stage of the clock divider was implemented in an SCL flip-flop [10], shown in
Figure 11, connected as a divide-by-two circuit. This configuration used was since
differential to single-ended conversion is naturally performed by utilizing the
complementary inputs and take one single-ended output. In addition, the SCL logic
family has the ability to operate at very high frequencies and thus provides a divide
solution for the 2.4Ghz oscillator output.

21
Vdd
Vdd Vdd
Vdd
Q Qb Qb Q Qi Qi
Vdd
V_bias
Q
CLK_b
Qb
CLK
V_bias
Qib Qi b
left_leg_top
right_leg_top
Vdd Vdd
MOSFET_NMOS
MOSFET26
Width=W_n_cs2
Length=Ln
R
R1
R=1.25 kOhm
Cntrl
MOSFET_PMOS
MOSFET2
Width=W_p
Length=Lp
MOSFET_NMOS
MOSFET27
Width=W_n_cs2
Length=Ln
MOSFET_NMOS
MOSFET8
Width=W_n
Length=Ln
Qi b
MOSFET_NMOS
MOSFET11
Width=W_n
Length=Ln
Qi
MOSFET_NMOS
MOSFET14
Width=W_n_cs
Length=Ln
CLK
MOSFET_NMOS
MOSFET17
Width=W_n_cs
Length=Ln
CLK_b
MOSFET_NMOS
MOSFET9
Width=W_n_cs
Length=Ln
MOSFET_NMOS
MOSFET12
Width=W_n
Length=Ln
MOSFET_NMOS
MOSFET13
Width=W_n
Length=Ln
MOSFET_PMOS
MOSFET24
Width=W_p
Length=Lp
MOSFET_PMOS
MOSFET25
Width=W_p
Length=Lp
Port
clock_bar
Port
Q
Port
clock
Port
Qb
MOSFET_PMOS
MOSFET23
Width=W_p
Length=Lp
MOSFET_NMOS
MOSFET21
Width=W_n_cs
Length=Ln
MOSFET_NMOS
MOSFET22
Width=W_n
Length=Ln
MOSFET_NMOS
MOSFET16
Width=W_n
Length=Ln
MOSFET_NMOS
MOSFET19
Width=W_n
Length=Ln
MOSFET_NMOS
MOSFET18
Width=W_n
Length=Ln
Port
pwr
Num=3

Figure 11: Schematic of SCL divide-by-two

The design variables for the oscillator schematic of Figure 11 are listed in Table 3:.

Table 3: SCL divide-by-two schematic variables
V_bias 0 V
Bias Current 0.62 mA
Transistor Width, W_n 2.8 m
Transistor Width, W_p 0.8 m
Transistor Width, W_n_cs 12.4 m
Current Source Transistor Width, W_n_cs2 24.8 m

Using the specifications given in Table 3, simulations verified that the SCL divider would
adequately perform a divide-by-two function up to an input clock rate of 5 Ghz.

A simplified schematic of the SCL divider is shown in Figure 12. The SCL divider
consists of two SCL latches in a master-slave flip-flop configuration. The clock input
common-mode voltage was adjusted to properly interface to the differential oscillators
DC level. The integration was performed on a system level such that the DC level was
adequate for both the SCL divider inputs and the mixer inputs. Referring to Figure 11,
both D-latches were biased with a current mirror using MOSFET26 and MOSFET27 to
level shift the clock inputs around the oscillators DC voltage.

22
Q Qb
Qbi Qi
V_bias
VDD
V_bias
VDD
MOSFET_NMOS
M13
MOSFET_NMOS
M15
MOSFET_NMOS
M16
MOSFET_NMOS
M14
MOSFET_NMOS
M12 CLK
MOSFET_NMOS
M11 CLK_b
MOSFET_PMOS
M10
MOSFET_PMOS
M9
MOSFET_PMOS
M7
MOSFET_PMOS
M8
MOSFET_NMOS
M2
CLK_b
MOSFET_NMOS
M4
MOSFET_NMOS
M6
MOSFET_NMOS
M5
MOSFET_NMOS
M3
MOSFET_NMOS
M1
CLK

Figure 12: Simplified schematic of the SCL divide-by-two

An additional benefit in using the SCL divider as the initial clock divider is the high
sensitivity of the circuit. A low amplitude input clock source is tolerable since the SCL
divider exhibits conversion gain and thus allows for a small minimum detectable signal
(MDS) [10].
3.2.2.2 TSPC Divider Chain
The remaining divider circuitry was implemented using the TSPC topology. There are
many methods and topologies for TSPC flip-flops as frequency dividers [11,12,13]. In
deciding the final topology, power dissipation was the main figure of merit. A divide-by-
two block was chosen to follow the SCL divider since higher divide ratios typically
involve higher power dissipation at an input clock rate of 1.2Ghz. Following the TSPC
divide-by-two is a TSPC divide-by-three which divides the 600Mhz input to the final
200Mhz clock needed to drive the six-phase block.
3.2.2.2.1 TSPC Divide-by-Two
The TSPC divide-by-two is illustrated in Figure 13. The divide-by-two circuit was
implemented from a D-flip-flop through inverse data-feedback by connecting the Qbar
output to the D input.
23
D
Clock
Clock
Clock
Clock
Precharge
Qbar
Q
MOSFET_NMOS
MOSFET11
Width=Wn
Length=Ln
MOSFET_PMOS
MOSFET6
Wi dt h=Wp
Length=Lp
MOSFET_NMOS
MOSFET4
Wi dt h=Wn
Length=Ln
MOSFET_PMOS
MOSFET2
Wi dt h=Wp
Length=Lp
MOSFET_PMOS
MOSFET7
Width=Wp
Length=Lp
MOSFET_PMOS
MOSFET10
Width=Wp
Length=Lp
MOSFET_NMOS
MOSFET12
Wi dt h=Wn
Length=Ln
MOSFET_NMOS
MOSFET9
Width=Wn
Length=Ln
MOSFET_NMOS
MOSFET8
Width=Wn
Length=Ln
Port
Pwr
Port
Q_bar
MOSFET_NMOS
MOSFET14
Width=W_n_inv
Length=Ln
Port
D
Port
Clock
Port
Q
MOSFET_PMOS
MOSFET13
Width=W_p_inv
Length=Lp

Figure 13: Schematic of TSPC flip-flop used as a divide-by-two

The design variables for the TSPC divide-by-two schematic of Figure 13 are listed in
Table 4.

Table 4: TSPC divide-by-two schematic variables
Transistor Width, W_p 2.4 m

The TSPC architecture features compact clock distribution and minimal circuit
complexity. This technique minimizes clock loading and only requires a single-phase
clock. These characteristics are crucial to realize high-speed circuits. The maximum
clock frequency of the TSPC divide-by-two was found through circuit simulation to be
approximately 3 Ghz, thus providing an adequate design margin.
3.2.2.2.2 TSPC Divide-by-three
The TSPC divide-by-three stage [14] is shown in Figure 14. The divide-by-three stage
operates on the same principle as the inverse data-feedback (Qbar to D) flip-flop but
incorporates an additional logic function in the feedback path. An input controlled
register in inserted into the feedback path which is transparent on half of the clock cycle,
that is it gives one clock-cycle delay to data 0 and no delay to data 1. This additional
logic function transforms the traditional flip-flop divide-by-two into a divide-by-three.
The half-transparent (HT) register is fast, adding a delay nearly equal to one inverter
propagation delay. Therefore the divide-by-three operates up to input clock rates almost
equal to the TSPC divide-by-two. It was verified through circuit simulation, for the
24
specifications given in Table 4, that the TSPC divide-by-three would operate up to input
clock rates of approximately 2.2 Ghz.

b
c
d
d
a
a
a
clock
clock
MOSFET_NMOS
MOSFET13
Width=Wn2
Length=Ln2 clock
MOSFET_NMOS
MOSFET17
Width=Wn
Length=Ln
MOSFET_PMOS
MOSFET2
Width=Wp1
Length=Lp1
clock
MOSFET_NMOS
MOSFET10
Width=Wn
Length=Ln clock
MOSFET_PMOS
MOSFET15
Width=Wp1
Length=Lp1
MOSFET_PMOS
MOSFET16
Width=Wp2
Length=Lp2
MOSFET_NMOS
MOSFET12
Width=Wn
Length=Ln
MOSFET_PMOS
MOSFET14
Width=Wp2
Length=Lp2
MOSFET_NMOS
MOSFET4
Width=Wn
Length=Ln
MOSFET_PMOS
MOSFET5
Width=Wp2
Length=Lp2
MOSFET_NMOS
MOSFET9
Width=Wn
Length=Ln
MOSFET_NMOS
MOSFET8
Width=Wn2
Length=Ln2
MOSFET_PMOS
MOSFET6
Width=Wp2
Length=Lp2
MOSFET_NMOS
MOSFET11
Width=Wn1
Length=Ln1
MOSFET_PMOS
MOSFET7
Width=Wp2
Length=Lp2
Port
b
Port
c
Port
d
Port
pwr
Port
a
Num=3
Port
clk
Num=1

Figure 14: Schematic of TSPC divide-by-three

The design variables for the TSPC divide-by-three schematic of Figure 14 are listed in
Table 5.

Table 5: TSPC divide-by-three schematic variables
Transistor Width, W_n1 0.8 m
Transistor Width, W_p 2 m
Transistor Width, W_p1 2 m
Transistor Width, W_p2 2.4 m

Variable duty cycle outputs can be taken from different nodes of the divide-by-three
circuit as shown in Figure 15. A symmetric output can be taken from node b of Figure 15
if the input clock has a fifty-percent duty cycle.

25
Figure 15: Output signals on different nodes of the TSPC divide-by-three

In our application, the duty cycle is not critical since the output of the divide chain feeds
additional TSPC circuit blocks. The particular output was chosen with consideration
placed on loading the divider node. Taking the output from node c was determined to
have the least effect on decreasing the transition edge slopes and this output was used in
the final design. It is critical for subsequent TSPC stages in the six-phase block (see
Section 3.2.2.3) that the transition edges be as sharp as possible [15]. Internal timing
problems arise in TSPC building blocks with shallow transition slopes.

0
2
-2
4
d
i
v
_
b
y
_
4
,

V
m1
time=5.391nsec
div_by_12=3.248 V
m2
ind Delta=5.001E-9
dep Delta=-0.001
delta mode ON
2 4 6 8 10 12 14 16 18 0 20
0
2
-2
4
time, nsec
d
i
v
_
b
y
_
1
2
,

V
m1
m2
1.5
2.0
2.5
1.0
3.0
d
i
v
_
b
y
_
2
,

V
0
2
-2
4
d
i
v
_
b
y
_
4
,

V
m1
time=5.391nsec
div_by_12=3.248 V
m2
ind Delta=5.001E-9
dep Delta=-0.001
delta mode ON
2 4 6 8 10 12 14 16 18 0 20
0
2
-2
4
time, nsec
d
i
v
_
b
y
_
1
2
,

V
m1
m2
m1
time=5.391nsec
div_by_12=3.248 V
m2
ind Delta=5.001E-9
dep Delta=-0.001
delta mode ON

Figure 16: Clock divider output waveforms

The output waveforms of each component in the clock divider chain are shown in Figure
16. From this figure it is apparent that the final divide-by-twelve
PMOS
NMOS
NMOS
NMOS
NMOS
PMOS
NMOS
PMOS
PMOS
PMOS
NMOS
NMOS
PMOS
PMOS
NMOS
a
b
c
d
Clk
a
b
c
d
26
( Mhz
f
f
osc
div
200
12
12 _
) output provides a fairly clean waveform with 3/2 duty cycle as
expected from the c output of the divide-by-three. Figure 16 also illustrates that the
SCL dividers output does not fully swing to ground. Because of this reduced voltage
swing, subsequent NMOS devices will have some continual current conduction and
PMOS devices will not be fully active. This is not an issue since the TSPC divide-by-two
stage following the SCL divider has been designed to work with the input voltage swing.
If the Precharge node is charged high enough on a low clock edge and Qbar is not
unintentionally pulled to ground when Precharge is high and Clock is low, the operation
is unaffected. The Precharge node experiences a voltage division between the pull-up
transistor, MOSFET7 and the series combination of MOSFET8 and MOSFET9. The
design must ensure that the voltage at the Precharge node rises above the threshold
voltage of the subsequent devices and Qbar is latched on a negative clock edge. This was
verified through simulation.
3.2.2.3 Additional Clock Divider Topologies
In addition to the clock divider topologies presented in the previous sections, several
alternative high-speed divider topologies were investigated. These circuits were
determined to be either too slow, or consume more power than desired.
Figure 17: Dynamic latch divider

The divider illustrated in Figure 17 [16] was investigated for its use as the first divider
stage interfacing to the oscillator. The first two inverters operate as dynamic latches
controlled by the differential clock input and the final inverter provides the overall
inversion necessary for the feedback loop. With this configuration, a divide-by-two
function can be realized.

Vout
VDD
MOSFET_NMOS
M1
CLK
MOSFET_NMOS
M2
CLK_B
MOSFET_NMOS
M4
CLK
Inv
X2
Inv
X4
Inv
X3
MOSFET_NMOS
M3
CLK_B
27
Figure 18: Dynamic latch divider

A second dynamic frequency divider was evaluated, as shown in Figure 18. Unlike the
divider in Figure 17, this design operates on a single-phase clock source and offers
complementary outputs. It is possible to use only half of this structure if a non-
complementary output is desired. The maximum operation frequency is set by the
propagation delay through the feedback connection, that is

pd tg
n
f
+
1
max

(6)
where
tg
is the delay through the -clocked transmission device,
pd
is the propagation
delay through one inverter in the feedback chain, and n is the number of inverters in the
feedback chain. It was determined that the dividers in Figure 17 and Figure 18 would not
provide the best solution since their power consumptions are greater than the final design
solution.

In addition, flip-flop based divide-by-three circuits were investigated. Two of these
circuits are shown in Figure 19 and Figure 20 [16]. The flip-flops were implemented in
the TSPC method similar to the circuit shown in Figure 13.
Figure 19: NOR based divide-by-three
D
>
Q
Q'
D
>
Q
Q'
Q1 Q2 NOR(Q1,Q2)
0 0 1
1 0 0
0 1 0
0 0 1
1 0 0
0 1 0
0 0 1
Clk
OUT_B
OUT
CLK
MOSFET_PMOS
M2
MOSFET_PMOS
M1
Invr
X1
Invr
X2
Invr
X3
Invr
X6
Invr
X4
Invr
X5
Invr
X8
Invr
X7
28
Figure 20: And based divide-by-three

The internal logic functions used to generate the proper feedback signals greatly decrease
the maximum operation frequency. It was verified through circuit simulation that the
maximum operation frequency for these two circuits was under 1Ghz using the design
variables associated with Figure 13. In addition to this problem, these circuits consume
greater power than the final divide-by-three implementation. This is of course not
surprising since two flip-flops are needed as compared to one flip-flop in the final design.

Several divide-by-four circuits were also considered, such as those in Figure 21 and
Figure 22. Using a divide-by-four in the clock divider chain would require a preceding
divide-by-three circuit, operating at 2.4Ghz, to obtain the final divide-by-twelve.
Figure 21: Cascaded D-flip-flop divide-by-four

Figure 22: Asynchronous cascaded D-flip-flop divide-by-four

The divide-by-four circuits suffer from the same speed and power problems as the divide-
by-three circuits previously described. Incorporating a divide-by-four in the clock divider
D
>
Q1
Q1'
D
>
Q2
Q2'
Clk
Q1 Q1 Q2 Q2
0 1 0 1
1 0 0 1
1 0 1 0
0 1 1 0
0 1 0 1
1 0 0 1
1 0 1 0
D
>
Q1
Q1'
D
>
Q2
Q2'
Cl k
AND
Q1 Q2 Q2 AND(Q1,Q2)
0 0 1 0
1 0 1 1
1 1 0 0
0 0 1 0
1 0 1 1
1 1 0 0
0 0 1 0
D
>
Q1'
Q1
D
>
Q2'
Q2
Clk
Q1 Q1 Q2 Q2
0 1 - -
1 0 0 1
0 1 0 1
1 0 1 0
0 1 1 0
1 0 0 1
0 1 0 1
29
chain is an additionally deficient solution since the preceding divide-by-three stage must
operate at the 2.4Ghz oscillator frequency. This will greatly increase the power
consumption and was therefore not chosen as the final solution.
3.2.3 Digital Front-End Multiplexing
The front-end multiplexing consists of the functional blocks illustrated in Figure 23. Data
from the Readout IC, in 12 parallel bits, is converted into two serial data streams using
two six-to-one multiplexers.

6-to-1 Mux
6-to-1 Mux
Six Phase
Clock
6 Data
Inputs
6 Data
Inputs
Q
I
Clock
Divider
Input
Page 1
Digital Front End Multiplexing

Figure 23: Detail of the front-end digital multiplexing

The six-to-one multiplexers were constructed from six parallel Transmission gates (T-
gates). T-gates were used instead of a single transistor in order to utilize the full input
voltage swing. A voltage drop equal to the devices threshold voltage is observed at the
output of a NMOS or PMOS transistor for a logic high or logic low input respectively.

Figure 24 demonstrates the multiplexers functionality. Each switch is activated from
one phase of a non-overlapping six-phase clock source. The switches are activated
sequentially, from ph1 to ph6 and the cycle is then repeated.
30
Figure 24: Multiplexer schematic diagram

One of the six T-gates is shown in Figure 25. The T-gates were scaled to minimize clock
feed-through and charge injection by keeping the transistor widths near minimum values
[17]. Table 6 lists the T-gate schematic variables.

Port
bias_n
Port
out
Port
in
Port
bias_p
MOSFET_PMOS
MOSFET5
Width=Wp
Length=Lp
pwr
MOSFET_NMOS
MOSFET4
Width=Wn
Length=Ln

Figure 25: T-gate schematic in ADS

Table 6: T-gate schematic variables
Transistor Width, Wn 1.2 m
Transistor Width, Wp 3.6 m

ph1
ph2
ph3
ph4
ph5
ph6
Implemented as T-gates
31
An additional inverter will be needed for each T-gate since this gate requires
complementary inputs. Referring to Figure 25, the bias_n signal, connected to the NMOS
transistor, will be directly connected to one output of the six-phase clock. An inverter is
placed from bias_n to bias_p to drive the PMOS transistor. This will create a delay
between the bias_n and bias_p inputs, equal to the propagation delay of one inverter. This
delay is not a concern since the propagation delay of one inverter is only a small fraction
of the active period of one of the six-phase signals. In fact the frequency of one six-phase
clock output must satisfy:

Mhz
f
f
data
phase six
33
6

% 100
6
1

phase six
cycle duty
(7)

where f
data
is the required I / Q data rate of 200 Mhz. If a minimum sized inverter is used
to produce the active signal on bias_p, the propagation delay is less than 1/30 of the
active period on the bias_n input.

The multiplexer schematic is shown in Figure 26 where the six T-gates and their control
inputs are illustrated.

Figure 26: Six-to-one multiplexer schematic in ADS
3.2.4 Six-Phase Clock
The six-phase clock must meet the timing requirements to properly latch the twelve bit
parallel data into two serial data streams. This is accomplished by providing six non-
overlapping clock signals to drive the two six-to-one multiplexers that were detailed in
the previous section. The timing diagram of Figure 27 illustrates the necessary six-phase
waveforms.

Port
out
Num=7
Port
in6
Num=13
Port
in5
Num=12
Port
in4
Num=11
Port
in3
Num=10
Port
in2
Num=9
Port
in1
Num=8
T-gate
X4
out
bi as_p
bias_n
in
ph4
ph4_b
T-gate
X5
out
bi as_p
bias_n
in
ph5
ph5_b
T-gate
X6
out
bi as_p
bias_n
in
ph6
ph6_b
T-gate
X3
out
bi as_p
bias_n
in
ph3
ph3_b
T-gate
X2
out
bi as_p
bias_n
in
ph2
ph2_b
T-gate
X1
out
bi as_p
bias_n
in
ph1
ph1_b
32

Figure 27: Timing diagram of the six-phase clock used in the front-end multiplexer

A six-segment shift register, shown in Figure 28, provided an excellent solution to meet
the output requirements. Using the set input signal, the register is set to an initial
100000 output pattern on the first rising clock edge. Each flip-flop within the register
will hold the 1 at its output until the next rising clock edge, where it is passed to the
next flip-flop.

D
>
Q
Clk
Set
D
>
Q
Reset
D
>
Q D
>
Q D
>
Q D
>
Q
Set
Reset Reset Reset
Reset

Figure 28: Shift register to generate the six-phase clocking signals

ph1 ph2 ph3 ph4 ph5 ph6
33
wrap
out
set
clock
vdd
Port
ph4
Port
ph5
Port
ph6
dff_reset
X4
Pwr
Q
D
Clock
Reset
set
clock
out
vdd
dff_reset
X5
Pwr
Q
D
Cl ock
Reset
set
clock vdd
dff_reset
X6
Pwr
Q
D
Cl ock
Reset
set
clock vdd
dff_set
X1
Pwr
Q
D
Set
Clock
wrap
Port
pwr
Port
ph3
Port
ph2
Port
ph1
Port
clk
Port
set
dff_reset
X3
Pwr
Q
D
Cl ock
Reset
dff_reset
X2
Pwr
Q
D
Cl ock
Reset

Figure 29: Schematic of the six-phase clock configuration

Low power, positive-edge triggered flip-flops are needed to implement the shift register.
In addition, one flip-flop must incorporate a synchronous set, and the remaining five flip-
flops must incorporate a synchronous reset. The TSPC method was again utilized to
construct these circuits.

Figure 30 illustrates the TSPC flip-flop with synchronous set. This circuit is a modified
version of the TSPC flip-flop shown in Figure 13. A NOR logic function was added to
the input stage controlled by the Set signal (En of Figure 30).
34
Clock
Clock
Clock
Clock
Precharge
Nor
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Qbar
Q
En
D
MOSFET_NMOS
MOSFET9
Width=Wn
Length=Ln
MOSFET_NMOS
MOSFET8
Width=Wn
Length=Ln
Port
Pwr
MOSFET_PMOS
MOSFET7
Width=Wp
Length=Lp
MOSFET_NMOS
MOSFET14
Width=W_p_inv
Length=Ln
MOSFET_PMOS
MOSFET13
Width=W_n_inv
Length=Lp
Port
Q
MOSFET_NMOS
MOSFET12
Width=Wn
Length=Ln
MOSFET_NMOS
MOSFET11
Width=Wn
Length=Ln
MOSFET_PMOS
MOSFET10
Width=Wp
Length=Lp
Port
Clock
Port
Set
Port
D
MOSFET_NMOS
MOSFET15
Width=Wn
Length=Ln
D
MOSFET_NMOS
MOSFET3
Width=Wn
Length=Ln
En
MOSFET_PMOS
MOSFET6
Width=Wp
Length=Lp
MOSFET_PMOS
MOSFET5
Width=Wp
Length=Lp
MOSFET_PMOS
MOSFET2
Width=Wp
Length=Lp

Figure 30: Schematic of D-Flip-Flop with Synchronous Set

Table 7: D-flip-flop with synchronous set schematic variables
Transistor Width, Wp 2 m
Transistor Width, W_n_inv 16 m
Transistor Width, W_p_inv 1.6 m

Table 8 lists the input functions and the corresponding output of the D-flip flop with
synchronous set. The Q output is logic high when the Set input is high, regardless of the
D input.

Table 8: Input functions of the D-Flip-Flop with Synchronous Set
D Input Set Input Output
HIGH LOW HIGH
LOW LOW LOW
HIGH HIGH HIGH
LOW HIGH HIGH

The D-flip-flop with synchronous reset [18] is shown in Figure 31. Referring to Figure
31, with the Reset signal active, the Prechage node is discharged and the Q_bar output is
pulled high on a positive clock edge. These two mechanism ensure that the output is logic
low when the Reset is active, regardless of the D input.
35
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Reset
D
Clock
Clock
Clock
Clock
Precharge Q_bar Q
Vcc
MOSFET_PMOS
MOSFET23
Width=W_p_inv
Length=Lp
MOSFET_NMOS
MOSFET29
Width=W_n_inv
Length=Ln
Port
Q
Port
Reset
MOSFET_PMOS
MOSFET20
Width=Wp
Length=Lp
MOSFET_PMOS
MOSFET33
Wi dt h=Wp
Length=Lp
MOSFET_PMOS
MOSFET22
Width=Wp
Length=Lp
MOSFET_NMOS
MOSFET27
Width=Wn
Length=Ln
MOSFET_NMOS
MOSFET32
Wi dth=Wn
Length=Ln
MOSFET_NMOS
MOSFET28
Width=Wn
Length=Ln
MOSFET_NMOS
MOSFET25
Width=Wn
Length=Ln
Port
D
Port
Cl ock
MOSFET_PMOS
MOSFET2
Width=Wp
Length=Lp
MOSFET_NMOS
MOSFET4
Width=Wn
Length=Ln
MOSFET_PMOS
MOSFET5
Width=Wp
Length=Lp
MOSFET_NMOS
MOSFET31
Width=Wn
Length=Ln
MOSFET_NMOS
MOSFET26
Wi dt h=Wn
Length=Ln
MOSFET_NMOS
MOSFET30
Wi dth=Wn
Length=Ln
MOSFET_PMOS
MOSFET24
Wi dth=Wp
Length=Lp
Port
Pwr
Num=5

Figure 31: Schematic of D-Flip-Flop with Synchronous Reset

Table 9: D-flip-flop with synchronous reset schematic variables
Transistor Width, Wp 2 m
Transistor Width, W_n_inv 16 m
Transistor Width, W_p_inv 1.6 m

Table 10 lists the input functions and corresponding output of the D-flip-flop with
synchronous reset.

Table 10: Input functions of the D-Flip-Flop with Synchronous Reset
D Input Set Input Output
HIGH LOW HIGH
LOW LOW LOW
HIGH HIGH HIGH
LOW HIGH HIGH

Non-overlapping outputs are ensured through inherent timing delays in both the D-flip-
flop with synchronous set and the D-flip-flop with synchronous reset. The flip-flop
output rise time slope was decreased through transistor sizing on the output inverter. The
36
inverters PMOS transistor was designed to have a slow response time while the NMOS
was designed to rapidly pull the output to ground. This functionality was verified by the
ADS simulation shown in Figure 32.
0
2
-2
4
v
a
r
(
"
1
"
)
,

V
0
2
-2
4
v
a
r
(
"
2
"
)
,

V
0
2
-2
4
v
a
r
(
"
3
"
)
,

V
0
2
-2
4
v
a
r
(
"
4
"
)
,

V
0
2
-2
4
v
a
r
(
"
5
"
)
,

V
5 10 15 20 25 30 35 40 45 50 55 0 60
0
2
-2
4
time, nsec
v
a
r
(
"
6
"
)
,

V

Figure 32: Simulation of the six-phase clock illustrating the initial state machine reset
phase

The initial reset phase can be clearly seen from Figure 32 as the first 13ns of the
simulation. During this period, the six-phase set signal is high and the shift register
outputs are held in their 100000 configuration. During operation the set signal will
need to be active for at least several clock periods (each clock period being 5ns) to set the
initial state of the shift register. This signal can simply be actuated from an output on the
infrared arrays Readout IC since there arent strict requirements on the timing of the set
signal. If this signal is not actuated, the initial state of the shift register is indeterminate
and the data will not be correctly multiplexed into the transmitter.
3.2.5 Single-Ended to Differential (S2D) Conversion
The single-ended outputs of the six-to-one multiplexers need to be converted to a
differential signal to interface with the Gilbert mixers. The S2D function is accomplished
using a simple differential amplifier as shown in Figure 33. The single-ended input is
applied to one side of the differential pair, and the other is biased at a constant DC level.
Current is pulled through one side or the other side of the differential pair depending
upon whether the 0 to 3.3 V input bitstream is high or low. The constant bias is set to
have the supply voltage (i.e. 1.65 V) with a resistive voltage divider and capacitive
bypassing. Common drain output stages are used to buffer the output signal and provide
the appropriate DC level shifting to properly interface with the mixers.
37

V_cs
baseband-
baseband+
input
diff_pair_2
diff_pair_1
MOSFET_NMOS
MOSFET17
Width=W_n2
Length=Ln
MOSFET_NMOS
MOSFET15
Width=W_n2
Length=Ln
MOSFET_NMOS
MOSFET19
Width=W_n
Length=Ln
MOSFET_NMOS
MOSFET20
Width=W_n
Length=Ln
MOSFET_NMOS
MOSFET18
Width=W_n_cs2
Length=Ln
V_cs
MOSFET_NMOS
MOSFET16
Width=W_n_cs2
Length=Ln
V_cs
MOSFET_NMOS
MOSFET22
Width=W_n_cs
Length=Ln
MOSFET_NMOS
MOSFET21
Width=W_n_cs
Length=Ln
R
R3
R=3.5 kOhm
Cntrl
V_DC
SRC2
Vdc=v_bias
Port
input
Port
baseband-
Port
baseband+
Port
Pwr
R
R2
Temp=-193
R=3 kOhm
R
R1
Temp=-193
R=3 kOhm

Figure 33: Single-Ended to Differential Converter (S2D) Schematic

Table 11: S2D schematic variables
Bias Current 0.5mA
Transistor Width, W_n_cs 5.2 m
Transistor Width, W_n_cs2 0.6 m
Drain Resistors 3 k

Because this circuit is the input stage to the Gilbert mixer, the interfacing voltages
required careful consideration. The common drain buffers were designed to provide the
correct DC level shift at the baseband+ and baseband- differential outputs through
transistor sizing. Gain compression was analyzed since distortion generated at the mixer
would produce undesired effects in the output QPSK spectrum. In order to properly
interface the mixer with both the S2D converter and the polyphase filter, the Gilbert
mixer was driven in an unconventional fashion. The detailed discussion of this issue has
been deferred until the Gilbert mixer has been presented in Section 3.2.7.
3.2.6 Polyphase Filter
The use of QPSK modulation requires establishing the data channels upon perfectly
orthogonal carrier signals. Orthogonality of the differential carrier signals was created
using a polyphase filter network [19] as shown in Figure 34. A passive network was
chosen to perform the required phase shifting in an effort to conserve power.

38
Figure 34: Polyphase network and one stage of the final circuit implementation

Table 12: Polyphase filter schematic variables
Corner Frequency 2.4 Ghz
R 2.1 k
C 32 fF

The quadrature phases are derived by passing the local oscillators output through the
RC-CR polyphase filter, which shifts the outputs by t45 with respect to one another.
Two differential outputs can be taken from a differential connection to the 0/180 and
the 90/270 outputs shown in Figure 34. The amplitude of the two quadrature outputs
will only be equal at one frequency, corresponding to the corner frequency at:

RC
f
c
2
1
(8)

Any deviation in the values of the resistors and capacitors will cause amplitude and phase
imbalance between the outputs. However, good matching between components is hard to
realize due to process variations and limitations on both the on-chip resistors and
capacitors.

Polysilicon resistors would be the preferred choice for implementing the resistors. The
process for polysilicon deposition is well controlled, having exact thickness for superior
accuracy and well-controlled widths and lengths. Most importantly, polysilicon resistors
do not rely on substrate bias connections and the sheet resistance is therefore independent
of voltage. Unfortunately, polysilicon has low sheet resistance. Using this material would
require very large resistor structures, or large capacitors to achieve the 2.4Ghz corner
frequency. A silicide-block layer was available in the IC fabrication process used to
realize the transmitter prototype. The silicide-block would increase the sheet resistance,
providing a suitable solution, although this was not used since reliable data on the sheet
resistance was not available. Diffusion resistors were chosen for the final
implementation. Further details on this material choice will be given in Section 3.5.
Differential
Oscillator
Polyphase
Filter
0 deg
90 deg
180 deg
270 deg
C
C
C
C
R
R
R
R
39

The depletion region junction between the N+ diffusion resistor and the P- substrate
contributes a parasitic capacitance. This capacitance is distributed along the length of the
resistor. The parasitic capacitance is composed of the bottom-plate capacitance (per unit
area), Cj, and the sidewall capacitance (per unit width), Cjsw. The total capacitance is
given by:

( ) ( )
jsw j
C L W C L W C + + 2 (9)

A first order model of this structure is given by two diodes [20], equivalent to the N+/P-
diodes created by the resistor structure, placed at each end of the resistor. This model is
illustrated in Figure 35. The diode model was created from data provided by the IC
fabrication facility. This model was then used in subsequent design and simulations.

Figure 35: Resistor modeling with provided spice data for the polyphase network

The main disadvantage to using a single-stage polyphase filter, as illustrated in Figure
36, is the limited matching between quadrature outputs for small RC mismatches.

Figure 36: One-stage polyphase filter network

It can be shown that the voltage transfer function of the quadrature to in-phase output of
the single-stage can be expressed as [21]:

Diode
DIODE1
Diode
DIODE2
R
R20
R=Rs*(L/W)
C
C
C
C
R
R
R
R
Iout+
Qout+
Iout-
Qout-
40
( )
( )
RC j
j V
j V
I
Q
(10)

From the above expression it is clear that small mismatches in R or C is highly undesired
as changes in either will cause an imbalance at the design frequency.

By cascading several of the stages illustrated in Figure 36, broadband quadrature outputs
can be produced having reduced sensitivity to R and C variations. If two stages are
cascaded, the outputs are matched at two frequencies, corresponding to the resonant
frequencies of each stage, 1/2R
1
C
1
and 1/2R
2
C
2
. A three-stage network is additionally
robust against component mismatches. In order to account for typical process variations,
the RC time constants for each stage were varied by t15% around the 2.4 Ghz design
frequency [22, 23]. Cascading three stages has been proven to be highly tolerant to
process variations, bounding the gain error to within t2% [21]. Figure 37 shows a phase
error comparison for 1, 2 and 3 stage polyphase networks.

I / Q Phase Offset Vs. Process Variation
82
86
90
94
98
102
106
110
114
0% 5% 10% 15% 20% 25% 30% 35% 40% 45% 50%
Percent Variation on Time Constant
P
h
a
s
e

R
e
l
a
t
i
o
n
Single
Doubtle
Triple

Figure 37: Polyphase phase relation between the I and Q outputs at 2.4 Ghz for multiple
polyphase stages over variations in the RC time constant

The final polyphase filter network is shown in Figure 38. Three stages were cascaded and
the resistors were replaced with the diode model. Although cascading three stages does
reduce the output amplitude compared to a single-stage polyphase filter, simulations
verified that the output swing is adequate to drive the mixer.
41
Di ode
DIODE20
Diode
DIODE18
Diode
DIODE19
Di ode
DIODE17
Di ode
DIODE22
Di ode
DIODE21
Diode
DIODE24
Diode
DIODE23
Di ode
DIODE12
Di ode
DIODE10
Di ode
DIODE11
Di ode
DIODE9
Di ode
DIODE14
Di ode
DIODE13
Diode
DIODE16
Di ode
DIODE15
Di ode
DIODE8
Di ode
DIODE7
Di ode
DIODE5
Di ode
DIODE6
Di ode
DIODE3
Di ode
DIODE4
Di ode
DIODE2
Di ode
DIODE1
R
R20
R=R1 Ohm
C
C30
C=C3 F
C
C29
C=C3 F
R
R26
R=R3 Ohm
R
R28
R=R3 Ohm
R
R27
R=R3 Ohm
R
R29
R=R3 Ohm
C
C28
C=C3 F
C
C31
C=C3 F
C
C24
C=C2 F
C
C25
C=C2 F
C
C26
C=C2 F
C
C27
C=C2 F
R
R22
R=R2 Ohm
R
R24
R=R2 Ohm
R
R23
R=R2 Ohm
R
R25
R=R2 Ohm
Port
Iout-
Num=4
Port
Qout-
Num=6
Port
Qout+
Num=5
Port
Iout+
Num=3
Port
Vi n-
Num=2
R
R18
R=R1 Ohm
R
R19
R=R1 Ohm
R
R21
R=R1 Ohm
Port
Vi n+
Num=1
C
C20
C=C1 F
C
C21
C=C1 F
C
C22
C=C1 F
C
C23
C=C1 F

Figure 38: Three-stage Polyphase structure schematic in ADS
3.2.7 Mixer
Mixing of the baseband data with the sinusoidal carriers was implemented using a Gilbert
Cell topology as shown in Figure 39. A full analysis of this circuit is given in [20]. The
Gilbert mixer was designed for adequate bandwidth and minimal power dissipation. The
maximum operating frequency of the mixer is inversely proportional to the parasitic
capacitances, C
gd
and C
gs
, and input and output resistances. However, the bandwidth is
directly proportional to the transistors transconductance [1]. A direct method of extending
the bandwidth is increasing the drain current, since the transconductance is proportional
to the square root of I
D
. Thus large bandwidth is achieved at the expense of power
dissipation. Since power is a fundamental design constraint in this work, device widths
were chosen to be as small as possible to minimize parasitic capacitances while
maintaining sufficient bandwidth.

42
LO+ LO-
RF-
RF+
Vout+
Vout-
R
R4
R=2.5 kOhm
Cntrl
RF+
R
R6
R=RD Ohm
R
R5
R=RD Ohm
Port
LO-
Port
LO+
Port
Vout-
Port
Pwr
Port
Vout+
Port
RF-
Port
RF+

Figure 39: Gilbert Mixer Schematic

Table 13: Gilbert Mixer schematic variables
Bias Current 0.27 mA
Upper Tier Transistor Width, W_n 10.2 m
Lower Tier Transistor Width, W_n2 20 m
Drain Resistors 1 k

Customarily, the Gilbert mixer employs a large amplitude LO input on the upper
transistor tier to switch the devices, while feeding the baseband data through the lower
tier to maintain linearity. Since the NRZ baseband data exhibits a switching
characteristic, that is a square waveform, it does not require linear amplification [3]. In
order to DC bias the mixer directly from the S2D and oscillator stages, the LO and RF
inputs to the mixer were exchanged. As previously described in Section 3.2.1, the DC
level of the oscillator output through the polyphase filter was positioned around an
adequate DC level to drive the mixers lower tier transistors. Thus the NRZ baseband
43
data served to switch the upper tier of inputs, while the smaller signal carrier from the
polyphase network was fed through the lower tier of inputs to the Gilbert mixer.

3.3 Simulation of the Clock and LO Section
A transient simulation was performed to verify the design work on the input data-
multiplexing path, including the differential oscillator, clock divider chain, six-phase
block, and polyphase filter network. The polyphase filter was loading by the two Gilbert
mixers, although the mixer performance was not a verification goal of this simulation.
The simulation setup is shown in Figure 40.

Figure 40: Blocks included in the clock and LO simulation

In order to adequately drive the six-phase block, a three stage exponential horn buffer
was added to the output of the TSPC divide-by-three as shown in Figure 40. The
multiplication factor between the three inverters in the horn buffer was 2.5, starting with
a minimum sized inverter. This buffer will also provide adequate drive when layout
parasitics are included since the 200 Mhz clock into the six-phase block will need to be
distributed to the six flip-flops while minimizing clock skew and maximizing the clock
slope edges.

The challenge in designing the circuits in the clock and LO signal path was to provide
enough voltage swing at the proper DC level for each circuit in the clock division chain
while minimizing power consumption. Fortunately the design was simplified since the
mixer was modified such that the oscillator provides the small signal input on the lower
tier. Thus the oscillator was more simultaneously interfaced with both the mixers and the
SCL divider. In addition, power was conserved since the oscillator only needed to
provide a small voltage swing thereby minimizing the oscillators bias current.

Figure 41 illustrates the simulation results. The topmost signal is the final 200 Mhz clock
source, driving the six-phase block. The reset signal was active until 12ns, at which time
the six-phase state machine had been properly set to the 100000 configuration. On the
subsequent positive clock edges, the 1 is cycled through the shift resister as can be seen
from the simulation results. It is also clear that the six-phase signals do not overlap, a
requirement set by the six-to-one multiplexer.
44

Figure 41: Results of the Clock and LO simulation

The two quadrature carrier signals from the polyphase filter network are shown in Figure
42. The 90 phase shift is clearly observed. Recall that small signal amplitude is
sufficient for the carrier signals, since the baseband data signals provide the large signal
switching inputs to the lower tier of the mixers.
45

Figure 42: Simulation of the quadrature carriers
3.4 Simulation of the Baseband to RF Output
The six-to-one multiplexers, S2D blocks and Gilbert mixers compose the baseband to RF
signal path. The quadrature carriers are applied to the two mixers in addition to the I and
Q data inputs. A differential RF output is taken from the two mixers and these two
signals will be applied to a balanced output antenna.

Figure 43: Blocks included in the baseband to RF output path

An alternating data sequence of 101010 was applied to the I-channel multiplexer while
the complementary set of data, 010101, was applied to the Q-channel multiplexer. This
data sequence exercises the transversal around the QPSK constellation in 180
transitions. The data outputs from the I-channel and the Q-channel multiplexers are
46
shown in Figure 44. The initial six-phase reset period can be observed until the second
data bit is clocked to the multiplexers output at 16ns.

Figure 44: Data out of the Q-channel and I-channel multiplexer

The multiplexers output fully swings to the supply rail and to ground, since T-gates were
used to pass the data. Clock feedthrough can be seen on the multiplexers output when
the six-phase clock signals switch the T-gates. In general, this may cause the normally
reverse-biased junction diodes in the MOS device to become forward biased, causing
faulty operation or latchup. In an effort to mitigate this issue, the parasitic gate-to-drain
capacitances were minimized by using near minimum sized devices on the T-gates. As
such, it was concluded that the V was not a concern.

The I-channel and Q-channel outputs of the S2D stages are shown in Figure 45 and
Figure 46 respectively.

Figure 45: Q channel data output of the multiplexer and S2D

47

Figure 46: Q channel data output of the multiplexer and S2D

From Figure 45 and Figure 46, it is evident that the output transition time of the S2D is
not completely equal. That is, the S2D output transitions to a low output faster than a
high output. The time to discharge the output node is thus small than charging the output.
An effort was made to equalize the transition times by decreasing the output rise-
transitions time constant through device sizing and drain resistance on the S2D stage. A
difference is transition time is not critical as long as it is a small fraction of the bit period.
Ultimately the difference in rise/fall transition times will affect the proper transmission of
the data symbol. For a brief period of time, the difference between the rise/fall transition
of the I bit and the fall/rise transition of the Q bit, the transmitted symbol will be
incorrect. This is not an issue as long as the receiver samples the recovered signal at the
appropriate time. If the receiver samples at the center of the data eye pattern, typically at
the center of the bit period, the correct symbol will be received if the transmitter has
switched to the correct symbol before the center of this period.

The final QPSK output waveform is shown in Figure 47.

Figure 47: QPSK Output

48
The small difference in transition time between the I and Q data channels can be seen, for
example, at the data transition at 16ns. It is clear that this difference is a very small
fraction of the bit period and is not expected to largely degrade system performance.

This simulation has verified that the circuit blocks perform as expected from the design
work. The data multiplexing was properly performed and final RF output has adequate
power to complete the data link.
3.4.1 Power Budget
The following table demonstrates the overall power consumption for the entire QPSK
transmitter. The total power consumption is estimated 9.5 mW, which is within the
desired 10mW power budget.

Table 14: Simulated power consumption for the transmitter circuit blocks
Differential
Conversion
Differential
Oscillator
Misc
Buffering
Mixers SCL
Divider
TSPC
Div-by-
three
TSPC
Div-by-
two
6-Phase
clock
Mux
1.66 mW 1.66 mW 0.76 mW 0.89
mW
2.03
mW
0.24 mW 0.78 mW 1.4 mW 0.05
mW
TOTAL 9.5 mW
3.5 Cryogenic Temperature Issues
Cryogenic operation results in several important changes to MOS devices as well as
changes to the properties of the metal and semiconductor interconnect materials. For
MOS devices, both the saturation velocity and carrier mobility increase. In addition, the
junction capacitance is reduced due to carrier freeze-out. The freeze-out effect causes
dopant atoms to hold on to their extra carriers, resulting in wider depletion regions and
thereby reducing capacitances. Carrier freeze-out also increases the threshold voltage
since fewer dopants in the channel are being ionized [24]. The current gain of bipolar
devices degrades at low temperatures, reducing the risk of CMOS latchup. Leakage
currents are reduced since the reversed bias junction current is directly related to the
temperature ( ( ) 1
/
0

kT qV
r
e I I ). The leakage current is further reduced since the
subthreshold slope is also reduced. Circuit speed is increased due to a reduction in the
resistivity of metal interconnections. The resistivity of aluminum drops to about one-fifth
of its room temperature value (depending on the thickness) at 77K [25, 26].

Despite the above benefits to low temperature operation, the reliability degradation
associated with hot-carriers in the channel yields a fundamental concern for our
application. Because of the increased saturation velocity and carrier mobility, carriers in
the channel experience high energy and can tunnel through the Si-SiO
2
interface. This
causes time-dependant degradation of device performance. The origin of hot-carrier
effects can be traced to the longitudinal electric field from the drain to source through the
channel. In order to reduce the electric field in the channel several solutions have been
studied. Lightly doped drain (LDD) structure devices have been widely used [25,27]
where some of the drain voltage is dropped in the LDD region to reduce the maximum
potential. This technique increases channel resistance and thereby reduces the drive
49
current. Another technique is to grade channel doping by increasing the potential more
rapidly near the source end, which reduces the maximum electric field [28].

Hot-carrier degradation typically shifts the threshold voltages such that the digital input
low voltage, V
IL
, and the digital input high voltage, V
IH
, are increased at low
temperatures [29]. The threshold voltage is more critical in the digital circuitry of the
clock divider, six-phase block, and the input multiplexer. To mitigate threshold shifts and
device degradation, the gate length of devices in these circuits was increased as
previously described in Section 3.2.2. Increasing the gate length decreases the maximum
field in the channel and is expected to reduce hot-carrier effects.

Changes in the resistivity of the semiconductor materials have also been investigated.
Several of the circuits used in the transmitter use resistors and variations in resistance
would change the circuits performance. The polyphase filter network particularly relies
on specific resistor values for optimal amplitude and phase relations between the outputs.
Resistance data for various semiconductor materials at 294K and 77K for two CMOS
processes was provided by Raytheon Vision Systems. The percent variation for the
various materials is listed in Table 15.

Table 15: Resistance change from 294K to 77K for various semiconductor materials
Semiconductor Material Percent Change in Resistance
Polysilicon (gate poly) (-) 11-13%
N+ Diffusion (-) 66%
P+ Diffusion (-) 22-34%
P-Well (+) 136-262%

From Table 15, the (-) indicates a decrease in resistance while the (+) indicates an
increase. This data indicates that the sheet resistance of N+ diffusion is most likely to be
accurately predicted for the process used to fabricate the IC prototype. For this reason,
and the intermediate value of sheet resistance (~87/ ), N+ diffusion was selected to
implement the resistors for the polyphase filter network as previously described in
Section 3.2.6. In fact, N+ diffusion resistors were used to implement all resistors on the
IC prototype that influence circuit performance.
3.6 Transmit Antenna
Since the transmitter chip features a differential output, a differential antenna stage is
required for the wireless interface.
50

Figure 48: Printed dual feed microstrip patch antenna [30]

While research into the transmitter and receiver antenna structures is still ongoing, the
current design solution currently being pursued is a dual feed microstrip patch antenna
[30].
4. System Synchronization
4.1 Synchronization Issues
In all coherent digital communication systems, clock and data recovery (CDR) is a
critical receiver function used to maintain coherence between the transmitter and the
receiver. As stated in Section 2.1, the receiver essentially performs the inverse operation
as the transmitter, as outlined in Figure 49. The local oscillator at the receiver must have
the same frequency and phase as the transmitters local oscillator. In addition, the data
transition edge must also be recovered in order to correctly sampling the received I and Q
data lines.

Oscillator
90 Deg.
Phase
Shift
Page 1
Communication System Synchronization
I
Q
I
Q
Oscillator
90 Deg.
Phase
Shift

Figure 49: Synchronization issues in a digital communication system

The two important clock recovery blocks, the carrier recovery block and the symbol-
timing block, are essential for receiving the transmitted data correctly. The overall issues
in this process are illustrated in the block diagram of Figure 50. The received signal is
51
used in a carrier recovery circuit block to generate a frequency and phase coherent local
oscillator signal. This is used to down-convert the received signal into the baseband I and
Q data lines. A symbol timing recovery block is used to acquire a clock signal aligned
with the data transition edge. This clock is used to sample the I and Q channels yielding
the recovered data. This sampler is often called a decision circuit.

Carrier
Recovery
90 Deg.
Phase
Shift
RF Input
.
LPF
LPF
Symbol
Timing
Recovery
Parallel to
Serial
Conversion
Page 1
Overview Diagram of the QPSK Receiver

Figure 50: Overview diagram of the QPSK receiver illustrating the carrier and symbol
timing recovery blocks

Recovery of the carrier and bit clock form the received transmission signal is not a trivial
process and the details will not be covered in this work. While it is up to the receiver to
capture and maintain coherence, the transmitter does play a major role in reducing the
amount of work this requires. Therefore issues relating to the transmitter have been
considered and the effects of phase incoherence have been investigated.

Phase incoherence results when the receivers local oscillator signal becomes misaligned
in time with the transmitters local oscillator. This can result from timing jitter at the
transmitters oscillator output, which skews the phase of the QPSK signal. The receiver
must accurately track these changes in phase to prevent bit spreading from the I bit into
the Q bit or visa versa. This issue is presented in Figure 51 [31]. With some phase error,

e
, between the transmitters local oscillator and the receivers local oscillator,
it can be shown that a fraction of the Q bit will be present on the I channel output. This
will result in an increased bit error rate and loss of performance on a system level.

52
Page 1
Effect of Phase Error
Ts
0
( )
( )

+ t
+ t
t A
t A
c
c
sin
cos
( ) ( )
s e s e
T A T A sin
2
1
cos
2
1
t t
( ) + t
c
cos
[ ]
2
sin cos
e e b
E t Decoded bit energy=
I-bit
Q-bit

Figure 51: Effect of phase reference error on the In-phase signal correlator

In a more visual representation, phase changes on the transmitters local oscillator,
typically referred to as timing jitter, produces the effects shown in Figure 52 [16]. The
output of an ideal oscillator has a constant period, and thus constant frequency over time.
In this situation there is no fluctuation in the transmission signals phase and the receiver
can easily track and recover the carrier signal. In practical circuits, the oscillation
frequency varies over time such that the zero-crossings have some distribution around the
ideal period. These fluctuations in phase result in symbol shifts on the QPSK
constellation diagram as shown in Figure 52 (b). It is clear that the bit error rate (BER)
increases as the phase fluctuations at the transmitter increase for a constant phase
reference at the receiver.

An important point is that system level performance only degrades when the transmitter
and receiver are phase incoherent. For large phase error,
e
, the BER tends to
asymptotically approach larger values as the signal-to-noise level increases. This
indicates that there is a minimum BER for a given phase error regardless of the signal-to-
noise level. If the receiver can track the transmitters phase fluctuations, the phase error
will be negligible, even for a large phase variance around the mean value.
53
Figure 52: Effects of timing jitter (a) on the oscillator phase (b) on the QPSK signal
constellation

The design of the transmitters local oscillator directly impacts the timing jitter and
ultimately the BER of the system. Timing jitter values are given by many communication
standards, such as SONET, in order to quantify allowable phase fluctuations. Jitter is a
time-domain measure of the phase accuracy, while phase noise is an equivalent frequency
domain representation of this process. The phase noise represents the noise spectrum
around the oscillators ideal frequency. Phase errors are characterized by a probability
density function of Gaussian distribution with constant mean and diverging variance
[32,33]. This distribution can be modeled by a Wiener process. It can be shown that the
timing jitter is related to phase noise by [34]:

( ) ( )
( )
1
1
]
1

3
10 / / _
2 2 2 2
10
_ sec
c
Hz dBc noise Phase
f
Hz offset Freq Jitter (11)

This relation has been used to evaluate the timing jitter of the transmitters oscillator from
a harmonic balance simulation in ADS.
5. Transmitter Integrated Circuit Layout
With the transmitter design phase completed, a prototype IC was fabricated for test and
verification. The IC was realized on a 2.5mm square die fabricated in a 4-metal 0.35 m
CMOS process by Taiwan Semiconductor Manufacturing Corporation (TSMC). Each
circuit block was carefully designed for optimum IC performance. Additional
considerations were made in regard to layout non-idealities as layout parasitics can
drastically change the circuit operation as compared to ideal simulations.

Circuit performance and power dissipation were of primary importance in the layout of
the IC prototype. Although design-automation tools are widely available, we returned to
handcrafting the physical design and circuit layout by using custom design since cost and
non-recursive engineering were not among the prime design criteria.

(a) (b)
54
MAGIC [26,35,36] was used as the IC layout editing tool. The MAGIC editor features
hierarchical designs, interactive design rule checks (DRC), circuit extraction, and a
technology-independent foundry interface. The TSMC 0.35m technology file was
obtained from Tanner Research, Inc. in addition to an electro-static discharge (ESD)
protected pad frame.

The main limitation of the MAGIC editor is the lack of a schematic capture tool,
requiring that layout-vs.-schematic (LVS) must be performed by extracting a netlist of
the layout and running SPICE simulations. Comprehensive LVS verification was
performed for each circuit block where possible. The extraction processes included RC
parasitics and layout non-idealities. The details of the LVS will not be covered in this
work.

In this section, the layout of each circuit block will be presented following the same
organization as Section 3.2. The overall transmitter organization will first be illustrated.
This section will then continue with the issues relating to the individual circuit blocks.
The potential problems with the IC version of the circuit block and their solutions will be
charted.
5.1 Transmitter Overview
The complete transmitter layout is shown in Figure 53. This figure shows the transmitter
in full scale with relation to the size of the IC.

Figure 53: Complete transmitter in relative proportion to the overall die size

As Figure 53 illustrates, the complete transmitter occupies approximately forty percent of
the available bond pads. Due to the availability of additional bond pads, a second version
of the transmitter was put on-chip. This second version incorporates changes to the
resistor structures for low temperature operation as outlined in Section 3.5. It is expected
that this second version will have superior performance under cryogenic conditions due
55
to the modification to the on-chip resistors. With these two versions, a complete set of
room temperature measurements as well as cryogenic temperature measurements can be
made. The final layout of both the room temperature transmitter and the low temperature
transmitter is shown in Figure 54.

Figure 54: Complete IC layout illustrating the room temperature and low temperature
transmitter sections

There were fifteen bond pads remaining unused after the room temperature and low
temperature transmitter sections had been placed on-chip. These remaining bond pads
were used for test structures that require bondwired output connections, such as the high
frequency RF outputs or off-chip connections to the oscillator tank inductors.

The transmitter layout was organized such that a natural flow of data from the
multiplexers to the output mixers was given careful consideration. This was most easily
accomplished by following the block diagram in Figure 4. Since the oscillator is the heart
of the transmitter, driving both the clock divider for the input multiplexers and the output
mixers, it was placed in the center of the transmitter. Outputs from the oscillator were
routed in opposite directions, one towards the input multiplexers and the other towards
the output mixers. Data into the multiplexers was directed from two orthogonal sides of
the IC where six input lines were used on each side. The transmitter arrangement is
shown in Figure 55.
Room Temp.
Transmitter
Cryo. Temp.
Transmitter
56
Figure 55: Transmitter layout overview and organization

As shown in Figure 55, six data inputs are fed into the multiplexers from each side. The
six-phase clock drives the multiplexers. The six-phase clocking signals are derived from
the oscillator through the divide-by-twelve prescaler. The oscillator output is also taken
through the polyphase network and into the mixers at the top of Figure 55. The data input
to the mixers is taken from the S2D, the single-ended to differential converted output
from the multiplexers.
5.2 Section Details
In this section, the layout of each circuit block will be presented. The flow of this section
will start at the data input front-end and travel through the transmitters components to
the output mixers.
5.2.1 Differential Oscillator
The oscillator circuit schematic is shown in Figure 56 in relation to the SCL divide-by-
two and the Polyphase network. As previously mentioned, the oscillator tank inductors
will be located off-chip so an improved quality factor can be achieved. This will reduce
phase noise and improve system performance.
6 Bits of
Input Data
Osc. L/C
Tank
RF Output
6 Bits of
Input Data
57
Figure 56: Oscillator circuit schematic

The layout of the cross-coupled transistor pair and diode-connected transistors for level
shifting is shown in Figure 57. These transistors are very large (100um) to increase the
transconductance of the cross-coupled transistors so oscillation is guaranteed. To
accommodate such large devices a folded structure was used for the layout.
Figure 57: Oscillator cross-coupled feedback pair layout

The oscillator current mirror reference voltage was brought out to an ESD bondpad for
external connection. This provided a manual adjustment to the reference current,
subsequently providing provisions for adjusting the voltage swing of the oscillator.

The capacitor for the resonant network was implemented on-chip. The on-chip capacitor
originated as a metal-insulator-metal (MIM) capacitor using Metal 3 and Metal 2 for the
top and bottom plates. The Metal 3 to Metal 2 parallel plate capacitor was first chosen
since the TSMC 0.35m process has only one polysilicon layer and a poly-poly capacitor
bias
bi as
Vdd
osc- osc+
MOSFET_NMOS
MOSFET10
Temp=Temperature
Width=W_n_cs
Length=Ln
Eqn
Var
V_DC
SRC5
Vdc=2 V
Cntrl
R
R1
R=1 kOhm
Cntrl
C
C2
C=57 f F
C
C3
C=46 fF
PRL
PRL1
L=9.8 nH
R=900 Ohm
PRL
PRL2
L=9.8 nH
R=900 Ohm C
C1
C=115 fF
MOSFET_NMOS
MOSFET13
Temp=Temperature
Width=100e-6
Length=Ln
MOSFET_NMOS
MOSFET14
Temp=Temperature
Width=100e-6
Length=Ln
I t Pul se
SRC4
Period=10000 nsec
Width=2 nsec
Fall=1 nsec
Rise=1 nsec
Edge=linear
Del ay=0 nsec
I_High=0.1 mA
I_Low=0 mA
MOSFET_NMOS
MOSFET12
Temp=Temperature
Width=W_n2
Length=Ln
MOSFET_NMOS
MOSFET9
Temp=Temperature
Wi dt h=W_n
Length=Ln
Port
osc+
Num=2
Port
osc-
Num=3
MOSFET_NMOS
MOSFET11
Temp=Temperature
Width=W_n2
Length=Ln
Port
pwr
Num=1
MOSFET_NMOS
MOSFET8
Temp=Temperature
Width=W_n
Length=Ln
Differential
Oscillator
Polyphase
Filter
Prescaler
Clock
Divider
(a)
bias
bias
Vdd
osc- osc+
MOSFET_NMOS
MOSFET10
Temp=Temperature
Width=W_n_cs
Length=Ln
Eqn
Var
V_DC
SRC5
Vdc=2 V
Cntrl
R
R1
R=1 kOhm
Cntrl
C
C2
C=57 f F
C
C3
C=46 fF
PRL
PRL1
L=9.8 nH
R=900 Ohm
PRL
PRL2
L=9.8 nH
R=900 Ohm
C
C1
C=115 fF
MOSFET_NMOS
MOSFET13
Temp=Temperature
Width=100e-6
Length=Ln
MOSFET_NMOS
MOSFET14
Temp=Temperature
Width=100e-6
Length=Ln
ItPulse
SRC4
Period=10000 nsec
Width=2 nsec
Fall=1 nsec
Ri se=1 nsec
Edge=linear
Delay=0 nsec
I_High=0.1 mA
I_Low=0 mA
MOSFET_NMOS
MOSFET12
Temp=Temperature
Wi dth=W_n2
Length=Ln
MOSFET_NMOS
MOSFET9
Temp=Temperature
Width=W_n
Length=Ln
Port
osc+
Num=2
Port
osc-
Num=3
MOSFET_NMOS
MOSFET11
Temp=Temperature
Width=W_n2
Length=Ln
Port
pwr
Num=1
MOSFET_NMOS
MOSFET8
Temp=Temperature
Width=W_n
Length=Ln
(b)
Out1 Out2
58
was not available. With this design, significant consideration went into minimizing and
modeling the parasitic capacitances. The resulting structure was suffered from a high
ratio of parasitic capacitance to desired capacitance, and was not advantageous to the
oscillators performance.

We used the lessons learned from designing the MIM capacitor, and decided to use the
parasitic capacitances to our advantage. Referring to Section 3.2.1, when analyzed as a
negative resistance oscillator, the resonator capacitor, C
res
, can be split in two with a
common connection to ground. The two capacitors, C
1
and C
2
, will have twice the
capacitance as C
res
, that is:

) ( 2
2 1 res
C C C
(12)

The equivalent network is shown in Figure 58.
PRL
RL1
PRL
RL2
C
C2
C
C1

Figure 58: AC equivalent of the oscillator resonator network

Referring to Figure 57 (a), capacitors C
1
and C
2
would connect between Out1 and Out2 to
ground, respectively.

Using the above result, a ground plane using Metal 1 was placed from the oscillator
cross-coupled transistor structure out to the IC edge. Metal 4 was used to connect the
oscillator to the bond pads, also constructed with Metal 4, where the Metal 4 to Metal 1
fridge and plate capacitances were exploited to obtain the desired capacitance value.
Figure 59 illustrates the resting structure.

Bondpads Connections used as tank capacitors
200
1510
389
389
59
Figure 59: Oscillator layout illustrating the output connections to the bond pads
Each capacitors value was estimated as follows:

Table 16: Oscillator resonator capacitance
Bondpad = 77.8 m x 77.8 m Rectangular Interconnect = 40 m x 302 m
Area = ( ) ( )
2 2
18133 302 40 8 . 77 m m m m +
Perimeter = ( ) ( ) ( ) m m m m 995 302 2 40 2 4 8 . 77 + +
Area Capacitance = ( ) fF m m aF 8 . 18 995 / 9 . 18
Fringe Capacitance = ( ) fF m m aF 163 18133 / 9
2

Total Capacitance = Area + Fringe = fF 182

The above calculation is an underestimate since the tapered section of the interconnect
was not included. The Metal 1 ground plane was extended as far as possible beyond the
Metal 4 interconnection but was constrained by the adjacent ESD bondpad as can be seen
in Figure 54. To minimize capacitive coupling between the oscillators resonant network
and the adjacent bondpad, the ground plane was extended a distance d equal to about ten
times the separation height, h, between the two parallel plates so that field lines terminate
on the ground plane. This is illustrated in Figure 60.

Figure 60: Metal 4 routing over Metal 1 for resonator capacitor
5.2.1.1 Non-ESD Protected Bondpads
The gate connections of MOS devices are well known to be ESD sensitive. Testing has
proven that the source/drain output connections are also susceptible to ESD damage, but
to a lesser degree than the gate input. As a circuit is scaled down, the vulnerability to
ESD damage increases. This is due to thinner gate oxide layers, narrower conductors and
more shallow doping wells. The basic principle of ESD protection circuits is to protect
the component through current limiting resistors and voltage reducing diodes as shown in
Figure 61 [37].
60
Vss
Vdd
Connection to
Main Circuit
(Gate,Source,Drain)
R
R2
R
R1
In
Diode
D1
Diode
D2

Figure 61: Simple ESD protection circuit

Resistor R2 is often implemented in an N+ diffusion resistor, creating a distributed p-n
diode junction along its length. Diode D1 can be fabricated in a diode-connected NMOS
device.

The inclusion of nonlinear elements such as the N+ diffusion resistor and diode-
connected devices in the ESD structure complicate the RF modeling of these structures.
Additional delays and loading on the connection to the main circuit additionally degrade
the RF performance.

The simplistic Metal 4 bondpads shown in Figure 59 were used in place of the ESD
protected bondpads due to the high frequency of operation and the lack of RF models for
the ESD bondpads. With these connections to the PCB there is an increased risk of ESD
damage. The connections off-chip bond to the oscillators resonator inductors and will
need some degree of ESD protection. These lines connect to the drains of the on-chip
transistors, not the gate, which does mitigate the ESD hazard. The solution was current
shunting resistors, placed from the off-chip inductor connection to ground. It is expected
that these resistors will transfer any static charge away from the IC during the bonding
process. This ESD protection strategy will be explained further in Section 6.
5.2.2 Clock Divider
Recall from Section 3.2.2 that the 200 MHz clock signal used to drive the six-phase clock
is derived from the transmitters 2.4 GHz local oscillator. The 2.4 GHz oscillator output
is scaled via a divide-by-twelve prescaler. The clock divider block diagram from Section
3.2.2 illustrating the divide-by-twelve blocks is repeated for convenience in Figure 62.

61
Six Phase
Clock
Oscillator
6 Clock
Signals
Page 1
Divide-By-Twelve Clock Divider
SCL Divide
By Two
TSPC
Divide By
Two
TSPC
Divide By
Three
6 Clock
Signals
2.4 Ghz
1.2 Ghz
600 Mhz 200 Mhz
Divide-By-Twelve
33 Mhz
33 Mhz

Figure 62: Clock divider block diagram

The description of the complete divide-by-twelve chain will be split into two sections, the
first stage SCL divide-by-two in the first section, followed by the TSPC divide-by-six.
5.2.2.1 SCL Divide-By-Two
The SCL divide-by-two takes the 2.4GHz differential output of the local oscillator and
provides a single-ended output at 1.2GHz. The SCL divider circuit schematic is shown in
Figure 63.

Figure 63: SCL Divide-By-Two circuit schematic

Since the SCL divide-by-two is the first divider stage, it must operate at the highest
frequency in the divide-by-twelve chain. Higher operating frequencies directly affect the
importance of loading created by parasitic layout capacitances. A tight and compact
layout strategy was therefore prefered over considerations placed on transistor matching.
Such preference is acceptable as the SCL divider acts in a digital mode. Current is either
directed in one path or the complementary path, so small deviations between devices will
Oscillator
SCL Divide
By Two
Qi
Vdd
Vdd
Q Qb
Vdd
V_bias
Qi
Vdd
Vdd
Q
right_leg_bot
Qb
right_leg_top
Qib Qib
V_bias Vdd Vdd
left_leg_bot
CLK_b
left_leg_top
CLK
Qb Q
Eqn
Var
Eqn Var
R
R1
R=1.25 kOhm
Cntrl
MOSFET_NMOS
MOSFET26
Temp=Temperature
Width=W_n_cs2
Length=Ln
MOSFET_NMOS
MOSFET27
Temp=Temperature
Width=W_n_cs2
Length=Ln
MOSFET_PMOS
MOSFET23
Temp=Temperature
Width=W_p
Length=Lp
MOSFET_PMOS
MOSFET24
Temp=Temperature
Width=W_p
Length=Lp
MOSFET_NMOS
MOSFET17
Temp=Temperature
Width=W_n_cs
Length=Ln
CLK_b
I_Probe
I_Probe1
MOSFET_NMOS
MOSFET21
Temp=Temperature
Width=W_n_cs
Length=Ln
MOSFET_NMOS
MOSFET9
Temp=Temperature
Width=W_n_cs
Length=Ln
MOSFET_NMOS
MOSFET13
Temp=Temperature
Width=W_n
Length=Ln
MOSFET_NMOS
MOSFET12
Temp=Temperature
Width=W_n
Length=Ln
MOSFET_NMOS
MOSFET18
Temp=Temperature
Width=W_n
Length=Ln
MOSFET_NMOS
MOSFET19
Temp=Temperature
Width=W_n
Length=Ln
MOSFET_NMOS
MOSFET11
Temp=Temperature
Width=W_n
Length=Ln
Qi
MOSFET_PMOS
MOSFET25
Temp=Temperature
Width=W_p
Length=Lp
MOSFET_NMOS
MOSFET14
Temp=Temperature
Width=W_n_cs
Length=Ln
CLK
MOSFET_NMOS
MOSFET8
Temp=Temperature
Width=W_n
Length=Ln Qib
Port
clock_bar
Num=2
MOSFET_NMOS
MOSFET16
Temp=Temperature
Width=W_n
Length=Ln
MOSFET_PMOS
MOSFET2
Temp=Temperature
Width=W_p
Length=Lp
MOSFET_NMOS
MOSFET22
Temp=Temperature
Width=W_n
Length=Ln
I_Probe
I_Probe2
Port
clock
Num=1
Port
Qb
Num=5
Port
Q
Num=4
Port
pwr
Num=3
62
not greatly affect the dividers performance as the output drives another digital circuit.
Some degree of device matching was achieved through uniform gate orientation, multi-
fingered transistors, and placing dummy transistor devices to improve edge matching.
The layout shown in Figure 64 was the result of these tradeoffs and layout strategies.

Figure 64: First clock divider stage the SCL Divide-By-Two Layout

In contrast to the six-phase clock and input multiplexers where the transistors gate
lengths were increased to mitigate hot carrier effects at low temperature, a minimum gate
length was maintained for the SCL divider stage.

The SCL current mirror reference voltage used to supply the bias current shown in Figure
64 was brought to an ESD bondpad for external connection.
5.2.2.2 TSPC Divide-By-Six Chain
The output of the SCL divide-by-two, at 1.2 GHz, is then input to the TSPC divide-by-six
chain. The divide-by-six chain with its connection to the first stage SCL divide-by-two is
demonstrated in Figure 65.
Oscillator
Input
Divider
Output
Bias Current
63
Figure 65: TSPC Clock Dividers Divide-by-six chain circuit schematic

The layout of the two circuit blocks comprising the divide-by-six chain followed the
same compact layout strategy as the SCL divider.
Figure 66: TSPC Divide-by-six chain layout

In a similar fashion to the SCL divide by two, the TSPC divide-by-two, operating at 1.2
GHz, would not perform correctly when its transistors gate lengths were increased to
0.6um. The TSPC divide-by-three, on the other hand, would operate correctly with a gate
length of 0.6um. The different device lengths can be seen in Figure 66.
5.2.3 Digital Front-End Multiplexing
The digital front-end starts with the six-phase clock used to drive the six transmission
gates for the six-to-one multiplexers. A 200Mhz clock source is used to drive the six-
phase clock and two sets of six clocking signals are output to the multiplexers. The
overall front-end section of the transmitter is shown in Figure 67.

precharge
Qbar
Qbar
Positive Edge Triggered TSPC D Flip-Flop
Eqn Var
MOSFET_NMOS
MOSFET11
Temp=Temperature
Wi dt h=Wn
Length=Ln
Por t
D
Num=1
MOSFET_NMOS
MOSFET8
Temp=Temperature
Width=Wn
Length=Ln
MOSFET_PMOS
MOSFET7
Temp=Temperature
Width=Wp
Length=Lp
MOSFET_PMOS
MOSFET2
Temp=Temperature
Width=Wp
Length=Lp
MOSFET_PMOS
MOSFET6
Temp=Temperature
Width=Wp
Length=Lp
Por t
Clock
Num=2
Port
Q
Num=3
Por t
Q_ b a r
Num=4
Por t
Pwr
Num=5
MOSFET_PMOS
MOSFET10
Temp=Temperature
Wi dt h=Wp
Length=Lp
MOSFET_NMOS
MOSFET12
Temp=Temperature
Width=Wn
Length=Ln
MOSFET_NMOS
MOSFET9
Temp=Temperature
Width=Wn
Length=Ln MOSFET_NMOS
MOSFET4
Temp=Temperature
Wi dt h=Wn
Length=Ln
MOSFET_PMOS
MOSFET13
Temp=Temperature
Width=Wp+0.4e-6
Length=Lp
MOSFET_NMOS
MOSFET14
Temp=Temperature
Width=Wn+0.4e-6
Length=Ln
a
a
a
a
clock
b
b b c
c c
d
d
d
clock
Eqn
Var
Port
a
Num=3
MOSFET_PMOS
MOSFET7
Temp=Temperature
Width=Wp2
Length=Lp2
MOSFET_PMOS
MOSFET6
Temp=Temperature
Width=Wp2
Length=Lp2
MOSFET_PMOS
MOSFET5
Temp=Temperature
Width=Wp2
Length=Lp2
MOSFET_PMOS
MOSFET16
Temp=Temperature
Width=Wp2
Length=Lp2
MOSFET_PMOS
MOSFET14
Temp=Temperature
Width=Wp2
Length=Lp2
Port
pwr
Num=2
Port
d
Num=6
Port
c
Num=5
Port
b
Num=4
Port
clk
Num=1
MOSFET_PMOS
MOSFET15
Temp=Temperature
Width=Wp1
Length=Lp1
MOSFET_NMOS
MOSFET13
Temp=Temperature
Width=Wn2
Length=Ln2 clock
MOSFET_NMOS
MOSFET17
Temp=Temperature
Width=Wn
Length=Ln
MOSFET_NMOS
MOSFET12
Temp=Temperature
Width=Wn
Length=Ln
MOSFET_NMOS
MOSFET9
Temp=Temperature
Width=Wn
Length=Ln
MOSFET_NMOS
MOSFET11
Temp=Temperature
Width=Wn1
Length=Ln1
MOSFET_NMOS
MOSFET8
Temp=Temperature
Width=Wn2
Length=Ln2
MOSFET_PMOS
MOSFET2
Temp=Temperature
Width=Wp1
Length=Lp1 clock
MOSFET_NMOS
MOSFET4
Temp=Temperature
Width=Wn
Length=Ln
MOSFET_NMOS
MOSFET10
Temp=Temperature
Width=Wn
Length=Ln clock
SCL Divide
By Two
TSPC
Divide By
Two
TSPC
Divide By
Three
Out
In
Divide-By-Three
Divide-By-Two
64
6-to-1 Mux
6-to-1 Mux
Six Phase
Clock
6 Data
Inputs
6 Data
Inputs
Q
I
200Mhz
Clock Input
Page 1
Data Multiplexing
33 Mhz
33 Mhz

Figure 67: Data multiplexing block diagram
5.2.3.1 Six-Phase-Clock
As previously mentioned in Section 3.2.4, the six-phase clock consists of six flip-flops
arranged in as a shift register. The shift register state machine is reset at the activation of
the transmitter by an external reset signal. In Figure 68 the six flip-flops are highlighted
as well as the 200 MHz clock input.
Figure 68: Six Phase Clock layout

The flip-flop layout was implemented to minimize interconnect wiring while allowing a
natural circulation of data through the shift registers. Referring to Figure 28, the Q output
of the last flip-flop is fed back to the D input of the first flip-flop. This circular pattern
was translated into a circular layout.

Issues relating to the 200 MHz input clock were taken under special consideration. The
input clock feeds all six flip-flops and phase skew between the flip-flops needs to be
minimized. To accomplish the necessary clocking phase coherence on all six flip-flops, a
Clock
Input
65
star-cluster[38] type of arrangement was used for the 200 MHz clock input. In a star-
cluster configuration, each flip-flop is connected to the centralized input by equal length
interconnect lines. The key design criteria for the six-phase layout are maintaining equal
length and loading to each flip-flop. This concept is illustrated in Figure 69.
Figure 69: General Star-cluster layout
5.2.3.2 Six-Phase-Clock and Input Multiplexer
To complete the back-end section of the transmitter, the two six-to-one multiplexers were
connected to the six-phase clock. The six clocking signals were routed out the top and
bottom of the six-phase block. The six clock outputs are illustrated in Figure 70. The
numbers one through six at the top and bottom of the six-phase clock circuit all
correspond to the signals ph1 through ph6 of Figure 28, respectively.

Figure 70: Organization and signal flow of the six-phase clock and data multiplexers

RESET
RESET RESET
RESET
RESET
SET
3
3
4
4
2
2
5
5
1
1
6
6
Q Data Out
I Data Out
Clock
Input
6-to-1 Multiplexer
6-to-1 Multiplexer
66
Since the six flip-flops were arranged in a circular pattern, the six output clocking signals
were forced to follow the same structure. Due to this configuration the order of the six
phases does not follow a simple pattern across the length of the multiplexer. The data
lines into the multiplexer will follow this pattern so that the I / Q data outputs will
correctly match the sequence of twelve parallel inputs.

The multiplexers were constructed with transmission gates as previously discussed and
illustrated in Section 3.2.3.
5.2.3.3 TSPC Dividers and Input Multiplexer
Figure 71 illustrates the front-end data multiplexing section integrated with the TSPC
divide-by six chain and the six-phase block. To compensate for the loading of the six-
phase clock star-cluster distribution (roughly 25fF) on the output of the TSPC divide-by-
six chain, an exponential horn of inverters was added to the divide-by-three output. In
addition, inverter buffers were placed on the output of the multiplexer since this output
must drive a long interconnect to the S2D inputs at 200 MHz. The addition of these
inverters can be seen in Figure 71 (a). An expanded view of the layout is given in Figure
71 (b).

The complete digital front-end section was used in a complete set of LVS simulations.
The LVS simulations verified key functionality of the complete digital front-end section.

67
Figure 71: TSPC Clock Dividers and Multiplexer Layout
5.2.4 Single-Ended to Differential Conversion
The S2D circuit of Figure 33 is repeated below in Figure 72 for convenience.
6 Data Inputs
6 Data Inputs
SCL Divider
Input
Q Data
I Data
(a)
(b)
68
Figure 72: Differential converter circuit schematic

A linear common-centroid layout was used to implement the drain resistors as shown in
Figure 73. The two 3 k resistors were split into three sections of 1 k and interdigitated
in a common-centroid layout. The common-centroid layout increases the match between
the two resistor values [39] assuming that there is a one or two-dimensional change in
sheet resistance over distance due to processing variation. This layout strategy only
accounts for process variation along orthogonal axes aligned with the resistor dimensions.
For example, a process variation along the diagonal of the resistor structure of Figure 73
will not be accounted for under this configuration.

Figure 73: Common-centroid layout used to implement the S2D resistors

V_cs
diff_pair_2
di ff_pai r_1
baseband-
baseband+
input
Eqn
Var
R
R2
Temp=-193
R=3 kOhm
V_DC
SRC3
Vdc=1.8 V
Cnt rl
R
R3
R=3.5 kOhm
Cnt rl
MOSFET_NMOS
MOSFET19
Temp=Temperature
Width=W_n2
Length=Ln
R
R1
Temp=-193
R=3 kOhm
C
C3
C=10.0 pF
V_DC
SRC2
Vdc=v_bias
MOSFET_NMOS
MOSFET20
Temp=Temperature
Width=W_n2
Length=Ln
MOSFET_NMOS
MOSFET17
Temp=Temperature
Width=W_n3
Length=Ln
MOSFET_NMOS
MOSFET15
Temp=Temperature
Width=W_n3
Length=Ln
Port
baseband+
Num=4
Port
baseband-
Num=3
Port
Pwr
Num=2
Port
input
Num=1
MOSFET_NMOS
MOSFET18
Temp=Temperature
Wi dth=W_n
Length=Ln
V_cs
MOSFET_NMOS
MOSFET16
Temp=Temperature
Width=W_n
Length=Ln
V_cs
MOSFET_NMOS
MOSFET22
Temp=Temperature
Width=W_n2
Length=Ln
MOSFET_NMOS
MOSFET21
Temp=Temperature
Width=W_n2
Length=Ln
6-to-1 Mux
Single
Ended to
Differential
6 Data
Inputs
A B A B A B
Ohms/Sq.
Distance
69
Figure 74: Layout of the differential converter

The flow of data into and out of the S2D stage can be seen from Figure 74. Data out of
the multiplexer enters the S2D circuit from the bottom and the S2D output to the mixer is
taken from the adjacent side.

One side of the differential pair is biased at half the data voltage swing to obtain equal
differential swing at the output. A simple voltage divider was used for this purpose and is
illustrated in Figure 75. A large resistance was used to minimize the current drain and the
resulting power consumption. The large resistance was best accomplished by using N-
Well for the resistor. This material has a high sheet resistance, although this comes at the
price of precise resistance values. Since the resistors are used as a voltage divider and the
structure is symmetric, a fairly accurate match between the two resistors is expected, and
a precise resistor value is not necessary.

An on-chip bypass capacitor was included to shunt noise on the bias voltage. Noise on
this line would modulate the differential pair and may create inaccuracies on the output.
The bypass capacitor was created using a MOS capacitor, connected as shown in Figure
76. The MOS capacitor is operated with V
GS
=Vdd/2=V
ref
and V
DS
=0V to maximize the
gate-to-channel capacitance. With V
DS
=0V, the gate-to-channel capacitance is equal to its
maximum value at WLC
ox
.

Output to
Mixer
Data from
multiplexer
70

Figure 75: Circuitry to bias the second half of the differential converter

Vdd
MOSFET_NMOS
M1

Figure 76: Bypass MOS capacitor

Only one instance of the bias circuitry shown in Figure 75 was implemented on-chip. The
output reference voltage is then distributed between the two S2D blocks. Figure 77
illustrates the overall configuration of the two S2D blocks and the reference voltage
distribution.

Reference
Voltage
+V
C
R
R
Vdd
= 1.65V
Gnd
Vdd
71

Figure 77: Overall configuration of the differential converters

The supply connection of the bias circuitry of Figure 75, labeled Vdd in this figure, was
routed to a bondpad for more flexibility. This voltage might be adjusted to set the
reference voltage at the midpoint of the voltage swing if the voltage divider
characteristics are not as expected.
5.2.5 Polyphase Filter
The layout of the polyphase network necessitated careful consideration. Optimal
performance is only achieved when the resistors and capacitors are matched to each
other. Device matching was thoroughly investigated and the design went through several
fundamental revisions. The polyphase filter network of Figure 34 is repeated below in
Figure 78 for convenience.

Figure 78: Single Polyphase stage circuit schematic

The polyphase network is comprised of three stages, each stage resembling the circuit
schematic shown in Figure 78. The RC time-constants were staggered by t15% around
the nominal value between the three stages to accommodate process variations. The
layout of a single stage is shown in Figure 79.

Differential
Oscillator
Polyphase
Filter
0 deg
90 deg
180 deg
270 deg
C
C
C
C
R
R
R
R
I Data
Input
Q Data
Input
Bias
72
Figure 79: Single Polyphase Stage illustrating the capacitor layout

As previously discussed, Metal 3 Metal 2 MIM structures provide the best capacitor
realization for this process. Several capacitor layout configurations were explored before
the final layout of Figure 79 was selected.
Figure 80: Common-centroid layout for matching four structures

The capacitor design problem involves matching four capacitors. There are several ways
to match four components in a common-centroid configuration. Two of these methods,
utilizing a common-centroid topology, are shown in Figure 80. Each component is split
into four parts and distributed to cancel one and two-dimensional process variations. A
modified version of this layout configuration was attempted and shown in Figure 81
where each 32fF capacitor was split into two pieces.

0 deg
90 deg
180 deg
270 deg
C
C
C
C
R
R
R
R
N-Diffusion
Resistors
D B
B C
A D
C A
A C
D A
C B
B D
B D
A C
A C
B D
D B
C A
C A
D B
73

Figure 81: Common-centroid four capacitor layout

There is a problem with using the layout shown in Figure 81. Although variations over
distance are canceled out, the connections between the components become so
complicated that degradation due to cross talk between interconnect signals drastically
overshadows any added benefits. The interconnections are shown in Figure 81 (b). In
addition, the only process variation that would affect the capacitor layout is differences in
oxide thickness between Metal 3 and Metal 2. Oxide thickness is expected to be uniform
since modern chemical-mechanical polishing (CMP) steps, especially over empty areas
IC floorspace below the capacitor structure, have tightly controlled characteristics.

The common-centroid capacitor configuration was abandoned and a simple layout was
chosen. Each of the four capacitors were constructed in a 27.4m square structure as
shown in Figure 82.

A B
C D
B A
D C
Dummy
Capacitors
(a) (b)
74

Figure 82: Capacitor used for the polyphase structure

Several resistor-matching guidelines were used in order to obtain resistors as closely
matched as possible. First, minimum widths were avoided such that process variations on
line widths would not contribute a significant deviation on the resistance value. The
length is also important and as a general guideline at least 10 s in length should be used
[39]. The resistors in this design were 12 s in length. A linear common-centroid
configuration was used, slightly different from the layout of the S2D resistors, as shown
in Figure 84.

Figure 83: Common-centroid layout used for the polyphase filter resistors

Process variations in sheet resistance are again canceled by using this layout
configuration, but it is more easily used to match four components that the configuration
shown in Figure 73. The final resistor layout is shown in Figure 84.

A B C D D C B A
75

Figure 84: Polyphase resistor layout

The complete polyphase network uses three of the stages illustrated in Figure 79. These
three stages were staggered to allow a natural flow through the network. The final
polyphase network layout is illustrated in Figure 85.

Figure 85: Layout of the three-stage Polyphase network
5.2.6 Mixer
The mixer circuit schematic is shown in Figure 86. The issues with this block were the
resistor structures and placement of the sets of differential pairs for efficient layout.

76
Figure 86: Gilbert cell double-balanced mixer circuit schematic

The mixer layout is shown in
Figure 87. The oscillator inputs enter connect to the mixers lower tier input from the
bottom and the data inputs from the S2D block enter from the side.
Figure 87: Single Mixer layout

Single
Ended to
Differential
Single
Ended to
Differential
Polyphase
Filter
V_LOm
V_LOm
Vout1
Vout1
Vout1
Vout2
Vout2
Vout2 Vout2
V_RF_p V_RF_m
V_LOp
Eqn
Var
R
R4
R=2. 5 kOhm
Cnt r l
V_DC
SRC1
Vdc=2.0 V
Cntrl
V_LOp
Port
Vout-
Num=6
Port
V_LO-
Num=3
Port
V_RF+
Num=1
Port
V_LO+
Num=4
Port
V_RF-
Num=2
Port
Pwr
Num=7
Por t
Vout+
Num=5
Oscillator Input
Data Input
RF Output
77
The mixers RF output lines were routed to simple Metal 4 bondpads without ESD
protection (see Section 5.2.1.1). Bondpads without ESD protection were used at the
mixers RF output for the same reasons presented for the oscillator design. Recall that the
ESD bondpads were not used due to the high frequency and inadequate bondpad models.
ESD resistors will be placed on the off-chip connections before bonding to dissipate any
static charge.

The two mixers in their final configuration are shown in Figure 88. From this figure the
output resistors can be seen. The off-chip ESD resistors will effectively be connected in
parallel to these on-chip resistors and this was taken into consideration when designing
the mixers layout.
Figure 88: Final layout of the two mixers illustrating the input/output connections

The current mirror reference voltage for the two mixer stages was brought to a bondpad
for external sourcing. This will allow flexibility on the mixers performance to be
evaluated during testing.
5.2.7 Remaining IC Issues
5.2.7.1 Power connections
The power and ground connections were separated for the digital and analog sections of
the transmitter. The digital section included the divide-by-twelve prescaler, six-phase
clock, and data multiplexers. The analog section included the oscillator, S2D blocks, and
mixers. The power and ground connections for the two sections are shown in Figure 89.

I Q
I /Q Data
Inputs
RF Output
78

Figure 89: Separation of the digital and analog supplies

Multiple supply and ground pads have been provided. Employing several connections to
the supply and ground reduce the inductive parasitics which cause L(dI/dt) voltage
transients. Both the digital and analog sections have on-chip bypass capacitors (~22pF)
for noise-suppression using MOS capacitors. This will be augmented with bypass
capacitance on the IC PCB test fixture.
Figure 90: On-chip bypass capacitors

67 um
67 um
79
5.2.7.2 Data Connections
On-chip data connections were hard-wired to the input multiplexer. This will allow
functional testing of the transmitter without the need to provide data inputs off-chip. The
multiplexer inputs were connected to either Vdd or ground through N-Well resistors and
also routed to bondpads. The dta values can be toggled through the bondpad connections
off-chip if desired.
5.3 Integrated Circuit Design for Testability
Testing considerations were made during the layout process to ensure that the widest
range of testing capabilities could be achieved. The goal of these considerations was to
ensure that each circuit block was represented in a test structure so that its individual
characteristics could be measured and analyzed. A tradeoff needed to be made between
the breadth of the test structures, the number of available bond pads, and the unused IC
floor-space. Figure 91 highlights the testability features of the IC. The boxed areas
highlight each test structure
Figure 91: IC design considerations for testability

In addition to the test structures, each circuit block biased with a current mirror has the
reference source taken out to a bondpad. This will allow fine adjustments on the bias
current for each individual circuit block. Such flexibility will permit proper functionality
while minimizing excessive current draw, and accordingly minimize the power
dissipation.

Six-Phase
Clock
Output
Current
Mirror
Reference
Sources
(darkened)
80
Consideration was also given to tests performed on a system level. Specifically, clock
synchronization issues are a fundamental concern and therefore a clock reference output
was created. One 33.34 Mhz clock signal out of the six-phase clock was taken out to a
bondpad. This output performs two functions. First, the data output of the infrared arrays
Readout IC must be synchronized to the input multiplexer of the transmitter. By using
one of the six-phase clocking signals, the Readout IC can maintain phase coherence with
the multiplexer. Secondly, the receiver will need to lock onto the transmitter oscillators
frequency and phase in order for proper demodulation to take place. A simple
communication system without clock recovery capabilities can use this output as a
synchronization indicator, most likely in a phase-locked-loop.

The transmitters RF output and oscillator resonator connections from the IC require
accurately controlled connections to the off-chip environment, since inappropriate
loading will affect ideal functionality. The RF characteristics of most common IC
packages are not suitable for this application, and a complete characterization at the
required operating frequency is not conventionally performed. Due to these limitations,
and the necessity for controlled connections to the IC, an interface PCB was fabricated.
The PCB details will be presented in Section 6.
5.3.1 Test Plan and Test Structures
In this section, an overview of the testing procedure will be presented and each test
structure will be described in detail. The test structure label given in Figure 91 will be
used as a reference throughout the remainder of this work. Table 17 lists the test
structures and their description.

Table 17: Functional sections and description for IC testing
IC Section Description
Section 1 Local 2.4Ghz Oscillator and Quadrature Polyphase Filter
Section 2 Room Temperature QPSK Transmitter
Section 3 Cryogenic Temperature QPSK Transmitter
Section 4 Analog Front-End (Quadrature Polyphase Filter, Differential
Conversion and Mixer)
Section 5 Divide-by-six TSPC clock divider Input Multiplexer
Section 6 Divide-by-twelve clock divider with first stage SCL Divide-
by-two and Input Multiplexer
Section 7 Resistor Test Structures
Section 8 Transistor Test Structures
81
5.3.1.1 Section 1: 2.4GHz Oscillator

Figure 92: Test Section 1 oscillator and polyphase

As shown at label A on Figure 92, the four outputs of the polyphase filter network are
probed with RF ground-signal-ground (GSG) 150m pitch probes. The polyphase output
will be probed so that the following tests can be performed:
a. Since the exact value of the on-chip capacitance was not known, the value of the
off-chip inductor needed to achieve the desired oscillation frequency needed to be
determined through the use of this test structure
b. Evaluate the phase relation between the quadrature outputs of the polyphase filter
network
c. Oscillator power consumption will be assessed as a function of the current mirror
bias and oscillator output amplitude

Tunable, high Q, off-chip inductors were needed to tune the oscillators resonant
frequency. A novel solution was implemented from short lengths of transmission line
constructed on the test PCB, illustrated in Figure 93. The transmission line lengths were
determined by the position of two capacitors, providing AC connections to analog
ground. Series pull-up resistors were connected from the transmission line to the 3.3 V
supply. These resistors provide some ESD protection by draining static charge on the
transmission lines before bondwire connections are made to the IC. In addition, the
resistors provide the DC feed connections to the oscillator.

A
82

Figure 93: Off-chip inductor configuration on the PCB test fixture

The shorted sections of transmission line have input impedances given by:

( ) ( ) l jZ l Z
sc in
tan
0 ,

(13)

where the propagation constant, =2/,

and the characteristic impedance, Z
0
, depend on
the PCBs material properties and dimensions of the transmission line, respectively. The
final design of this structure will be presented in Section 6.
5.3.1.2 Section 2: Room Temperature Transmitter
Once the length of the transmission line has been determined for the oscillators
operating frequency, this length can be used for setting up the operation of the room-
temperature transmitter. The following tests will be performed:
a. Verification of the 33 Mhz six-phase clock synchronization output shown in
Figure 91.
b. Nominal testing of the output on a spectrum analyzer to verify the function of the
mixing process at the carrier and data rates. Since the output power is of minimal
concern, only a correct spectrum will be used to ascertain functionality of the
transmitter on a first-order.
c. Using the available data inputs, the BER can be tested.
d. Power consumption on all functional circuit blocks
83
5.3.1.3 Section 3: Low-Temperature Transmitter

Figure 94: Test Section 3 Low Temperature Transmitter

By rotating the IC 180 degrees, the low temperature transmitter will fit the same PCB
pads and interconnections as the room temperature transmitter. Since the functionality is
identical, the same testing procedure applies.
5.3.1.4 Section 4: Analog Section of the Room Temperature Transmitter
Figure 95: Test Section 4 section 4 will be tested by rotating the IC 180 degrees

This section includes the S2D stages, mixers, and polyphase filter network, driven by an
off-chip oscillator source. In the same configuration as Section 3, Section 4 will be
accessed by rotating the IC 180. This will put the low-temperature transmitter in the
PCB test structure used for the room temperature transmitter and will also put the test
circuitry in Test Section 4 into the PCB test structure used for Test Section 1. The length
84
of transmission line used for the oscillator tank resonator of Test Section 1 will be used as
the RF outputs for Test Section 4. Using this structure, the following can be tested:
a. Since the local oscillator inputs to the mixer can be driven off-chip, there is the
opportunity to test the mixer conversion gain vs. oscillator drive power and the
3dB bandwidth of the mixer at the oscillator port.
b. In addition to the availability of the oscillator input, the data input lines to the
mixer are available. The 3dB bandwidth of the data port can be measured.
c. Isolation on the three mixer ports can be measured: the LO-Data, LO-RF, and the
Data-RF
d. Power consumption vs. data rate and oscillator frequency can be determined.
5.3.1.5 Section 5: Divide-by-six clock divider and Input Multiplexer
Figure 96: Test Section 5 Divide-by-six (missing the first stage divide-by-2) clock
divider and input multiplexer test structure

As shown above in Figure 96, Test Section 5 allows testing of the TSPC divide-by-six
chain and the input multiplexer. A 1.2 GHz clock input drives the clock divider and
several data inputs are accessible for testing the input multiplexing capabilities at various
clock frequencies. Two data inputs are available for testing the functionality of the
multiplexer and a 33 MHz six-phase clocking signal is made accessible for data
synchronization to the clock input. Only one data output is available, corresponding to
the channel with the accessible data inputs. This test structure was designed for simple
functionality testing and therefore a comprehensive evaluation of both the I and Q
channels is not offered with this structure. Specifically, the following can be tested:
a. Data multiplexing with synchronization to the clock input. The maximum input
clock frequency can be derived and, since the data rate needs to be an integer
divisor of the clock frequency, the maximum data rate can be determined.
b. Power dissipation of the clock divider chain as a function of input clock
frequency.
Clock
Input
I Channel
Data Output
GND
Data Input 1
Data Input 2
33 Mhz 6-
Phase sync
6-Phase Reset
Vdd
85
5.3.1.6 Section 6: Divide-by-twelve clock divider and Input Multiplexer
Since the first stage SCL divide-by-two clock divider is a critical link between the
oscillator and the following lower frequency clock dividers, Test Section 6 was designed
to test this circuit.
Figure 97: Test Section 6 Divide-by-twelve clock divider and input multiplexer test
structure

An output is provided immediately following the SCL divider stage to provide some
monitoring capabilities on the functionality of this block. In addition, data inputs and a
differential clock input are available to run similar testing as described above for Test
Section 5.
5.3.1.7 Section 7: Resistor Test Structures
There are several resistors in the transmitter design that need to be fairly precise in value
for proper functionality of the QPSK modulation. Most notably, the resistors in the
polyphase filter network are vital in providing the correct phase relation between the four
oscillator outputs. It is therefore important to measure the materials resistivity used in
the resistor structures for comparison with the values used during the design phase. To
accomplish this, three resistor structures were made using Transmission Line Model
(TLM) patterns. These are summarized in Table 18 and Figure 98.

Table 18: Resistor Test Structures
Material Type TLM contact spacing TLM structure width
N+ Diffusion 50um, 100um, 200um, 250um, 300um 30um
N-Well 50um, 100um, 200um, 250um, 300um 30um
Polysilicon 50um, 100um, 200um 30um

Clock Input 0deg
Clock Input
180deg
SCL Current
Mirror Source
Data Input 1
Data Input 2
33Mhz 6-Phase
sync Output
Gnd
I Data Out SCL Divider Out
6-Phase Reset
86
Figure 98: Test Section 7 Resistor test structures
5.3.1.8 Section 8: Transistor Test Structures
These test structures were created so that MOSFET I-V data could be collected. This data
will be used for comparison with the spice data provided by the fabrication facility,
TSMC, and the cryogenic transistor model provided by Raytheon. Various transistor
widths were used for two transistor lengths, the minimal length, 0.4m and the longer
transistor length of 0.6m. The transistor test structures are summarized in Table 19 and
Figure 99. The transistors were oriented as shown in the upper right corner of Figure 99.

Table 19: Transistor Test Structures

Length
0.4um 0.6um
0.6um
10um
20um
0.6um
N-Type
20um
0.6um
20um
0.6um
Width
P-Type
20um
Polysilicon
Resistor
N+ Diffusion
Resistor
N-Well Resistor
Gnd
Gnd
87

Figure 99: Test Section 8 Transistor test structures
6. IC Interface Printed Circuit Board
The IC die was mounted on the PCB and electrical connections were made by wirebonds
to the off-chip connections. Figure 100 illustrates the fabricated PCB. The PCB was a
two-inch square, three-layer board, composed of two dielectric materials.
Figure 100: PCB for IC mounting and interfacing

Transmission
Line Inductor
RF Output
Die Location
Source Gate
Well Drain
P-Type
0.6 / 0.6
P-Type
0.6 / 0.4
N-Type
10 / 0.4
N-Type
0.6 / 0.4
N-Type
20 / 0.6
N-Type
20 / 0.4
N-Type
0.6 / 0.6
P-Type
20 / 0.6
P-Type
20 / 0.4
88
Figure 101: Detail of the PCB test fixture

Tight control of the physical parameters of the PCB material was necessary for the
transmission line inductor and RF output lines. The characteristic impedance and physical
dimensions of the PCB traces used for these connections are directly related. Of
additional interest for our application, a low dielectric constant, loss tangent, and thermal
coefficient of expansion (CTE) were also important parameters. With these issues in
mind, the 4003C material produced by the Rogers Corporation was chosen for the
dielectric material between the top signal layer and the ground plane. This material boasts
a very temperature coefficient of dielectric constant and stability over microwave
frequencies. This results in a more constant electrical properties from room temperature
to cryogenic temperature environments in a broadband application. The low CTE helps to
ensure continuity of plated vias through the material over our wide temperature range.

The dielectric material separating the power and ground planes is not constrained by the
issues presented above, and FR-4 was chosen. The final PCB layering diagram is shown
in Figure 102.

Analog
Power
Digital
Power
Data / Sync.
/Reset Signal
I/O Header
ESD/Supply
Resistors
Ruler for
Capacitor
Position
Current
Mirror
Potentiometer
ESD/Supply
Resistors
SMA
Connector
Data
Input
Header
89

Figure 102: PCB layer definitions and construction (dimensions in inches)

Thermal considerations were taken to ensure that the two dielectric materials would not
fracture under cryogenic temperatures. Table 20 lists the CTE values for the two
dielectric materials.

Table 20: CTE values
Axis Rogers 4003C FR-4
x-axis 11 13
y-axis 14 13
z-axis 46 75

The x-axis and y-axis CTE values for the Rogers 4003C and the FR-4 are close enough
such that planar expansion will not rupture the PCB.

Once the die is attached to the board, resistors used for ESD protection will be soldered
to the traces that connect to unprotected IC bondpads. The value of this resistor is not
critical to the oscillators connection, since the resistor only supplies a connection to the
supply. The single constraint is that the resistor should be as small as possible to
minimize thermal noise. On the RF output connection, the value is more crucial since
amplitude variations due to mismatch will occur. The RF output connection was modeled
and a parameter sweep was performed on this connection, as shown in Figure 103.
90

Figure 103: Model and simulation results of loading the RF output with the ESD resistor

Since the amplitude variation was very minimal across a broadband spectrum, a 150
value was chosen for the ESD resistor.

The AC shorting capacitor used to shunt the length of the transmission line inductor was
selected to provide a near perfect short, looking slightly capacitive, at the 2.4 Ghz
oscillation frequency. This capacitor was chosen for low equivalent series resistance
(ESR) such that it would not limit the Q of the resonator network. Fortunately these
criteria were easily met since a small package was necessary to fit in the allocated space
on the PCB, minimizing package non-idealities.
7. Testing Results
7.1 TLM Resistor Measurements
Transmission Line

m1
freq=2.40GHz
mix_freq=2.400000, R=50.000000
mag(spect)=0.04
m2
freq=2.200GHz
mix_freq=2.200000, R=150.000000
mag(spect)=0.074
1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 1.0 3.8
0.02
0.04
0.06
0.08
0.00
0.10
freq, GHz
m
a
g
(
s
p
e
c
t
)
m1
m2
T-line_2 T-line_1
Bondpad
Bondwire
output
ESD Resistor
C
C1
C=60.0 fF
Z1P_Eqn
Z1P1
Z[1,1]=R
MLIN
TL2
L=710.0 mil
W=30.0 mil
Subst="MSub1"
MLIN
TL1
L=100.0 mil
W=30.0 mil
Subst="MSub1"
R
R2
R=500 Ohm
L
L1
R=
L=1.0 nH
VtSine
SRC1
Phase=0
Damping=0
Delay=0 nsec
Freq=mix_freq GHz
Amplitude=1 V
Vdc=0 V
R
R3
R=50 Ohm
91
Figure 104: General TLM Plot of Measured Resistance

The total measured resistance using the TLM method as shown in Figure 104 is given by:

s c
R R r + 2
(3)

where R
c
is the contact resistance and R
s
is the semiconductor material resistance. The
semiconductor material resistance, R
s
is given by:

dw
L
R
s

(4)

where is the resistivity of the material, d is the thickness. The sheet resistance, R
sh
, is
given by /d, and Equation 3 can be expressed as:

,
_
+
w
L
R R r
sh c
2
(5)

Equation 5 has a slope, with respect to L, of R
sh
/w, with x and y coordinates at Lx and
2Rc, as shown in Figure 104. Furthermore, R
c
can be expressed as [40]:

w
L
R R
t
sk c

(5)

where R
sk
is a modified sheet resistance of the semiconductor material directly under the
contact pad. L
t
, called the transfer length, is additional length added to the resistor to
account for current flow in and out of the contact.

TLM measurements were made on the N+ diffusion resistor and the N-Well resistor as
shown in Figure 105 and Figure 106.
Pad Spacing, L
Slope = Rsh/w
Measured Resistance
Lx
2Rc
92
TLM Measurement on N-Diffusion Resistor
174.6
438.0
951.7
1602.1
2372.6 y = 12.926x + 47.869
0
250
500
750
1000
1250
1500
1750
2000
2250
2500
-50 0 50 100 150 200
Distance Along Resistor (um)
R
e
s
i
s
t
a
n
c
e

(
O
h
m
s
)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
N-Diffusion Resisance
Std Dev
Linear (N-Diffusion Resisance)
Lx
Gradient = Rsh/w

Figure 105: TLM N-diffusion resistor measurement

TLM Measurement on N-Well Resistor
2704.7
6721.2
15432.8
25785.6
34988.6
y = 192.84x + 1314.1
0
5000
10000
15000
20000
25000
30000
35000
40000
-50 0 50 100 150 200
Distance Along Resistor (um)
R
e
s
i
s
t
a
n
c
e

(
O
h
m
s
)
0
20
40
60
80
100
120
140
160
180
N-Well Resistance
Std Dev
Linear (N-Well Resistance)
Lx
Gradient = Rsh/w

Figure 106: TLM N-well resistor measurement

93
From these data the
7.2 Differential Oscillator

Figure 107: Transmission line adjustment mechanism to tune the oscillator tank inductor

T-Line distance = 480mil = 1.2192cm

Distance between the bondwire and the first tick mark (oscillator test structure) = 29mil
Distance between the bondwire and the first tick mark (transmitter) = 43mil

m1
freq=2.344GHz
oscillator..spec.TraceA=-44.470
1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 1.7 3.0
-65
-60
-55
-50
-45
-70
-40
freq, GHz
oscillator..spec.TraceA
m1

Figure 108: Measured oscillator output taken from one of the four polyphase filter
outputs

94

Figure 109: Measured oscillator illustrating the presence of second harmonic

Simulation Results with the measured Info:

Eqn spect=dbm(fs(var("Qout-"),0,8Ghz,81,10ns,14.17ns))
m3
freq=2.400GHz
spect=-38.200
m4
freq=4.700GHz
spect=-50.883
m3
freq=2.400GHz
spect=-38.200
m4
freq=4.700GHz
spect=-50.883
1 2 3 4 5 6 7 0 8
-60
-40
-20
-80
-10
freq, GHz
s
p
e
c
t
m3
m4

Figure 110: Simulated oscillator spectrum taken from one of the four polyphase filter
outputs

95

Figure 111: Measured phase shift between the 0and 90 outputs of the polyphase filter

Figure 112: Measured output from the six-phase synchronization signal
96

8. References

[1] Freeman, T., A Short Range Wireless Interface for Cryogenic Imaging Arrays, M.S.
Thesis, University of California, Santa Barbara, June 2001.

[2] Feher, K., ed., Advanced Digital Communications, Nobel Publishing, Atlanta, 1997,
pp. 316-334.

[3] Larson, L. E., ed., RF and Microwave Circuit Design For Wireless Communications,
Artech House, Inc., Boston, 1996.

[4] Feher, K., ed., Digital Communications, Nobel Publishing, Atlanta, 1997, pp. 128-
165.

[5] Svensson, C., Yuan, J., High-Speed CMOS Circuit Technique, IEEE J. Solid State
Circ., Vol. 24, No. 1, Feb. 1989, pp. 62-70.

[6] Huang, Q., Rogenmoser, R., Speed Optimization of Edge-Triggered CMOS Circuits
for Gigahertz Single-Phase Clocks, IEEE J. Solid State Circ., Vol. 31, No. 3, March
1996, pp. 456-465.

[7] Svensson, C., Yuan, J., New Single-Clock CMOS Latches and Flipflops with
Improved Speed and Power Savings, IEEE J. Solid State Circ., Vol 32., No. 1, Jan.
1997, pp. 62-69.

[8] Lee, T., The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge
University Press, 1998, pg. 512.

[9] Aparicio, R., A CMOS Differential Noise-Shifting Colpitts VCO, ISSCC, 2002.

[10] Floyd B., Hung C.M., K.O. K., Intra-Chip Wireless Interconnect for Clock
Distribution, IEEE J. Solid State Circ. Vol. 37 No. 5 pp. 543-552, May 2002

[11] Yang, S.H., Lee, C.H., Cho, K.R., A CMOS Dual-Modulus Prescaler Based on a
New Charge Sharing Free D-Flip-Flop, ASIC/SOC Conference, 2001 Proceedings, 14
th

Annual IEEE International, 2001, pp. 276-280.

[12] Chae, K.Y., Ki, H.J., Hwang, I.C., Kim, S.W., Double Precharge TSPC for High-
Speed Dual-Modulus Prescaler, ICVC 6
th
International Conference on VLSI and CAD,
1999, pp. 609-612.

[13] Chang, B., Park, J., Kim, W., A 1.2Ghz CMOS Dual-Modulus Prescaler Using
New Dynamic D-Type Flip-Flops, IEEE J. Solid State Circ., Vol. 31, No. 5, May 1996,
pp. 749-752.
97

[14] Yuan, J., Svensson, C., Fast CMOS Nonbinary Divider and Counter, Elec. Letters,
Vol. 29, Issue 13, June 24, 1993 pp. 1222 1223.

[15] Larsson, P., Svensson, C., Impact of Clock Slope on True Single Phase Clocked
(TSPC) CMOS Circuits, IEEE J. of Solid State Circ., Vol. 29, No. 6, 1994, pp. 723-726.

[16] Razavi, B., RF Microelectronics, Prentice Hall, New Jersey, 1998.

[17] Razavi B., Design of Analog CMOS Integrated Circuits, pg. 442, Mc-Graw Hill,
New York, 2001, pp. 401-406.

[18] Yoshizawa, H., Taniguchi, K., Nakashi, K., An Implementation Technique of
Dynamic CMOS Circuit Applicable to Asynchronous/Synchronous Logic, Proc. of
IEEE Int. Symp. on Circ. and Sys., May 31 Jun 3, Vol. 2, 1998, pp. 145-148.

[19] Gingeli, M.J., Single Sideband Modulation Using Sequence Asymmetric Polyphase
Networks, Electrical Communication, Vol. 48, No. 1, 1973, pp. 21-25.

[20] Gray, P., Meyer, G., Analysis and Design of Analog Integrated Circuits, 3
rd
ed., John
Wiley and Sons, New York,1993.

[21] Galal S.H., Tawfik M.S., Ragaie H.F., On the Design and Sensitivity of RC
Sequence Aysmmetric Polyphase Networks in RF Integrated Transceivers, IEEE Trans.
on Cir. and Sys. II: Analog and Digital Signal Processing, Vol. 47, Issue 1, 2000, pp. 18-
27.

[22] Borremans, M., Muer, B., Steyaert, M.,The Optimization of Ghz Integrated CMOS
Quadrature VCOs Based on a Poly-phase Filter Loaded Differential Oscillator, IEEE
Symp. on Circ. and Sys., May 28-31, Session II, 2000, pp. 729-732.

[23] Bahbahni, F., Kishigami, Y., Leete, J., Abidi, A., CMOS Mixers and Polyphase
Filters for Large Image Rejection, IEEE J. of Solid State Circ., Vol. 36, No. 6, June
2001, pp. 873-887.

[24] Rabaey, J., Digital Integrated Circuits: A Design Perspective, Prentice Hall, New
Jersey, 1996.

[25] Wang-Ratkovic, J., Lacoe, R.C., MacWillilams, K.P., Song, M., Brown, S., Yabiku,
G., New Understanding of LDD CMOS Hot-Carrier Degradation and Device Lifetime at
Cryogenic Temperatures, IEEE Proc. 35
th
Annual Reliability Phys. Symp., April 8-10,
1997, pp. 312 319.

[26] Long, S., Butner, S., Gallium Arsenide Digital Integrated Circuit Design, McGraw
Hill, New York, 1990.
98

[27] Murakami, E., Yoshimura, T., Goto, Y., Kimura, S.,Gate length scalability of n-
MOSFETs down to 30 nm: Comparison between LDD and non-LDD structures, IEEE
Trans. on Elect. Dev., Vol. 47, Issue 4, Apr. 2000, pp. 835 840.

[28] X. Chen, Q. C. Ouyang, G. Wang, S. Banerjee, Improved Hot-Carrier and Short-
Channel Performance in Vertical nMOSFETs With Graded Channel Doping, IEEE
Trans. Electron Devices Vol. 49, pp. 1962-1967, Nov. 2002.

[29] Deen, M.J., Digital Characteristics of CMOS Devices at Cryogenic Temperatures,
IEEE J. of Solid State Circ., Vol. 24, No. 1, Feb. 1989, pp. 158-164.

[30] Deal, William, Radisic, Vesna, Qian, Yongxi, Itoh, Tatsuo. Integrated-Antenna
Push-Pull Power Amplifiers, IEEE Trans. Microwave Theory and Techniques, Vol. 47,
No. 8, Aug. 1999.

[31] Gagliardi, R.M., Satellite Communications, 2
nd
ed., Van Nostrand Reinhold, New
York, 1991.

[32] McNeil, J., Jitter in Ring Oscillators, PhD. Dissertation, Boston University, 1994.

[33] Demir, A., Phase Noise in Oscillators: A Unifying Theory and Numerical Mathods
for Characterization, IEEE Trans. on Circ. and Sys.-I, Vol. 47, No. 5, May 2000.

[34] T. Weigandt, Low-Phase-Noise, Low-Timing-Jitter Design Techniques for Delay
Cell Based VCOs and Frequency Synthesizers, PhD Dissertation, UC Berkeley, Jan.
1998.

[35] Ousterhout, J., Hamachi, G., Mayo, R., Scott, W., Taylor, G., Magic: A VLSI
Layout System, Proc. 21
st
Design Automation Conf., 1984, pp. 152-159,

[36] Magic Tutorials in Berkeley VLSI Tools, Technical Report UCB/CSD/85-225,
University of California, Berkeley, Calif, Feb. 1985.

[37] Hellstrom, S., ESD The Scourge of Electronics, Springer-Verlag, Berlin, 1998, pp.
136-143.

[38] Young, Brian. Digital Signal Integrity. Prentice Hall, New Jersey, 2001.

[39] Hastings, A., The Art of Analog Layout, Prentice Hall, New Jersey, 2000.

[40] Reeves, G. K., Harrison, H. B., "Obtaining the Specific Contact Resistance from
Transmission Line Model Measurements", IEEE Transactions on Electron Devices, EDL-
3(5), 1982, pp. 111 113.

10 1 1 111

Caricato da

Informazioni sul documento

Descrizione originale:

Titolo originale

Copyright

Formati disponibili

Condividi questo documento

Condividi o incorpora il documento

Opzioni di condivisione

Hai trovato utile questo documento?

Questo contenuto è inappropriato?

Copyright:

Formati disponibili

10 1 1 111

Caricato da

Copyright:

Formati disponibili

UNIVERSITY OF CALIFORNIA

Potrebbero piacerti anche