Datasheet

54HSC/T Series
54HSC/T Series
Radiation Hard High Speed CMOS/SOS Logic
Replaces May 1995 version, DS3594-3.3 DS3594-4.0 November 2002
The CMOS/SOS HSC/T Series offer the combined benefits of low power, high speed CMOS with the inherent latch up immunity, Single Event Upset (SEU) immunity and the high level of radiation hardness of Silicon on Sapphire technology. The 54HSC/T Series of circuits are pin for pin compatible with the 54LS series range. HSC and HST devices have CMOS and TTL compatible inputs/outputs respectively.
Adders 54HSC/T283 4-bit binary full adders with fast carry Counters 54HSC/T161 4-bit synchronous binary counter 54HSC/T163 Synchronous 4-bit counter 54HSC/T191 Synchronous 4-bit counter Decoders/Demultiplexers 54HSC/T138 3-line to 8-line decoder/multiplexer 54HSC/T139 Dual 2 to 4 decoders/multiplexers 54HSC/T148 8-line to 3-line octal priority encoders 54HSC/T151 1 of 8 data selectors/multiplexers 54HSC/T154 4 to 16-line decoders/demultiplexers 54HSC/T157 Quad 2-line to 1-line data selectors/multiplexers 54HSC/T238 3 to 8 decoder/demultiplexer 54HSC/T253 Dual 4 to 1 data selectors/multiplexers Registers 54HSC/T164 8-bit parallel output serial shift register 54HSC/T165 Parallel load 8-bit shift register 54H5C/T166 8-bit shift register Comparators 54HSC/T521 8-bit magnitude comparator Line Drivers 54HSC/T240 54HSC/T241 54HSC/T244 54HSC/T540 54HSC/T541
FEATURES
s Radiation Hard to 1MRad (Si) s High SEU Immunity, Latch Up Free s Low Power CMOS/SOS Technology s Plug In Replacement for 54/74LS, HC and HCT s Dual In Line or Flatpack Packages Gates and Buffers 54HSC/T00 Quadruple 2-input positive NAND gates 54HSC/T02 Quadruple 2-input positive NOR gates 54HSC/TO3 Quadruple 2-input positive NAND gates with open collector outputs 54HSC/T04 Hex Inverters 54HSC/T08 Quadruple 2-input positive AND gates 54HSC/T10 Triple 3-input positive NAND gates 54HSC14 Hex schmitt-trigger inverters 54HSC/T21 Dual 4-input positive AND gates 54HSC/T27 Triple 3-input positive NOR gates 54HSC/T32 Quadruple 2-input positive OR gates 54HSC/T86 Quadruple 2-input Exclusive OR gates 54HSC/T125 Quadruple bus buffer gates with tri-state outputs (Active low enable) 54HSC/T126 Quadruple bus buffer gates wlth tri-state outputs (Active high enable) Flip-Flops 54HSC/T74 54HSC/T109 54HSC/T273 54HSC/T374 54HSC/T574
Octal 3-state driver inverting Octal 3-state driver complementary enable Octal 3-state driver Octal 3-state driver/buffer inverting Octal 3-state driver/buffer
Transceivers 54HSC/T245 OctaI bus transceiver Latches 54HSC/T373 Octal transparent latch, 3-state outputs 54HSC/T573 Octal transparent latch, 3-state outputs Miscellaneous 54HSC/T670 4 x 4 register files with tri-state outputs
Dual D-type flip-flops wlth preset and clear Dual J-KB flip-flop with preset and clear Octal D-type flip-flops Octal D-type edge triggered flip-flops Octal D-type edge triggered flip-flops
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54HSC/T Series
DC CHARACTERISTICS AND RATINGS

Parameter Supply Voltage Input Voltage Current Through Any Pin Operating Temperature Storage Temperature Min. -0.5 -0.3 -25 -55 -65 Max. 10 VDD+0.3 +25 125 150 Units V V mA C C Note: Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions, or at any other condition above those indicated in the operations section of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 1: Absolute Maximum Ratings
Total dose radiation not exceeding 3x105 Rad(SI) Symbol VDD VIH1 VIL1 VIH2 VIL2 VOH Parameter Supply Voltage HST Input High Voltage HST Input Low Voltage HSC Input High Voltage HSC Input Low Voltage Output High Voltage Conditions VIN = VIH or VIL IOH = -20A* IOH = 6mA* IOH = -11mA VIN = VIH or VIL IOL = -20A* IOL = 6mA* IOL = 9mA VIN = VDD or VSS All inputs VOUT = VDD or VSS Outputs disabled VIN = VDD Outputs unloaded Min. 4.5 2.0 3.5 VDD-0.1 3.7 2.5 Typ. 5.0 1 20 Max. 5.5 0.8 1.5 0.1 0.2 0.4 5 50 Units V V V V V V V V V V V A A A
VOL
Output Low Voltage
IIL IOL IDD
Input Leakage Current Output Leakage Current Quiescent Current
VDD = 5V10%, over full operating temperature range. * Guaranteed but not tested. Refer to individual device types (-55C / +125C). Figure 2: Electrical Characteristics
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54HSC/T Series
54HSC/T00 : Quadruple 2-Input Positive NAND Gates

The 54HSC/T00 is a Quadruple 2-Input Positive NAND gate.
Inputs A L L H H B L H L H
Outputs Y H H H L
1A 1B 1Y 2A 2B 2Y VSS 1 2 3 4 5 6 7 Top View 14 VDD 13 4B 12 4A 11 4Y 10 3B 9 3A 8 3Y
Figure 2: Logic Diagram
H = high level, L = low level
Figure 1: Function Table
Figure 3: Pin Out
+25C Symbol tPLH tPHL Parameter Propagation delay time, low to high level output Propagation delay time, high to low level output Typ. 11 10 Max. 20 18
-55C / +125C Typ. 17 18 Max. 22 20 Units ns ns
Figure 4: Switching Characteristics
Limits +25C Symbol IDD VOL VOH VIL1 VIH1 VIL2 VIH2 IIN Parameter Quiescent Current Output Voltage Low Level Output Voltage High Level Voltage Input Low (CMOS) Voltage Input High (CMOS) Voltage Input Low (TTL) Voltage Input High (TTL) Input Leakage Current Test Conditions VIN = 0V or VDD IOL = 9mA IOH = -11mA VIN = VDD or VSS Figure 5: DC Characteristics Min. 2.5 3.5 2.0 Max. 10 0.4 1.5 0.8 0.5 -55C / +125C Min. 2.5 3.5 2.0 Max. 300 0.4 1.5 0.8 5.0 Units A V V V V V V A
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54HSC/T Series
54HSC/T02 : Quadruple 2-Input Positive NOR Gates

The 54HSC/T02 is a Quadruple 2-Input Positive NOR gate.
Outputs Y H L L L
1Y 1A 1B 2Y 2A 2B VSS 1 2 3 4 5 6 7 Top View 14 VDD 13 4Y 12 4B 11 4A 10 3Y 9 3B 8 3A
Figure 3: Pin Out
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54HSC/T Series
54HSC/T03 : Quadruple 2-Input Positive NAND Gates With Open Collector Outputs
The 54HSC/T03 is a Quadruple 2-Input Positive NAND gate with open collector output. Inputs A L L H H B L H L H Outputs Y H H H L
Figure 3: Pin Out +25C Symbol tPLH tPHL Parameter Propagation delay time, low to high level output Propagation delay time, high to low level output Typ. 11 10 Max. 20 18 -55C / +125C Typ. 17 18 Max. 22 20 Units ns ns
Figure 4: Switching Characteristics Limits +25C Symbol IDD VOL VOH VIL1 VIH1 VIL2 VIH2 IIN Parameter Quiescent Current Output Voltage Low Level Output Voltage High Level Voltage Input Low (CMOS) Voltage Input High (CMOS) Voltage Input Low (TTL) Voltage Input High (TTL) Input Leakage Current Test Conditions VIN = 0V or VDD IOL = 9mA IOH = -11mA VIN = VDD or VSS Figure 5: DC Characteristics 5/101 Min. 2.5 3.5 2.0 Max. 10 0.4 1.5 0.8 0.5 -55C / +125C Min. 2.5 3.5 2.0 Max. 300 0.4 1.5 0.8 0.5 Units A V V V V V V A
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54HSC/T Series
54HSC/T04 : Hex Inverters

The 54HSC/T04 consists of six Hex Inverters.
Inputs A H L
Outputs Y L H Figure 2: Logic Diagram
1A 1Y 2A 2Y 3A 3Y VSS
1 2 3 4 5 6 7 Top View
14 VDD 13 6A 12 6Y 11 5A 10 5Y 9 4A 8 4Y
Figure 3: Pin Out
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54HSC/T Series
54HSC/T08 : Quadruple 2-Input Positive AND Gates

The 54HSC/T08 is a Quadruple 2-Input Positive AND gate.
Outputs Y L L L H
Figure 3: Pin Out
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54HSC/T Series
54HSC/T10 : Triple 3-Input Positive NAND Gates

The 54HSC/T10 is a Triple 3-Input Positive NAND gate.
Inputs A L X X H B X L X H C X X L H
Outputs Y H H H L
1A 1B 2A 2B 2C 2Y VSS 1 2 3 4 5 6 7 Top View 14 VDD 13 1C 12 1Y 11 3C 10 3B 9 3A 8 3Y
H = high level, L = low level, X = irrelevant
Figure 3: Pin Out
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54HSC/T Series
54HSC14 : Hex Schmitt-Trigger Inverters

The 54HSC/T14 consists of six Hex Schmitt-Trigger Inverters.
Inputs A L H
Outputs Y H L Figure 2: Logic Diagram
1A 1Y 2A 2Y 3A 3Y VSS
1 2 3 4 5 6 7 Top View
14 VDD 13 6A 12 6Y 11 5A 10 5Y 9 4A 8 4Y
Figure 3: Pin Out
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54HSC/T Series
54HSC/T21 : Dual 4-Input Positive AND Gates

The 54HSC/T21 is a Dual 4-Input Positive AND gate. Inputs A L L L L L L L L H H H H H H H H B L L L L H H H H L L L L H H H H C L L H H L L H H L L H H L L H H D L H L H L H L H L H L H L H L H Outputs Y L L L L L L L L L L L L L L L H
1A 1B NC 1C 1D 1Y VSS
1 2 3 4 5 6 7 Top View
14 VDD 13 2D 12 2C 11 NC 10 2B 9 2A 8 2Y
Figure 3: Pin Out
Figure 1: Function Table +25C Symbol tPLH tPHL Parameter Propagation delay time, low to high level output Propagation delay time, high to low level output Typ. 11 10 Max. 20 18 -55C / +125C Typ. 17 18 Max. 22 20 Units ns ns
Figure 4: Switching Characteristics Limits +25C Symbol IDD VOL VOH VIL1 VIH1 VIL2 VIH2 IIN Parameter Quiescent Current Output Voltage Low Level Output Voltage High Level Voltage Input Low (CMOS) Voltage Input High (CMOS) Voltage Input Low (TTL) Voltage Input High (TTL) Input Leakage Current Test Conditions VIN = 0V or VDD IOL = 9mA IOH = -11mA VIN = VDD or VSS Figure 5: DC Characteristics 10/101 Min. 2.5 3.5 2.0 Max. 10 0.4 1.5 0.8 0.5 -55C / +125C Min. 2.5 3.5 2.0 Max. 300 0.4 1.5 0.8 5.0 Units A V V V V V V A
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54HSC/T Series
54HSC/T27 : Triple 3-Input Positive NOR Gates

The 54HSC/T27 is a Triple 3-Input Positive NOR gate.
Inputs A L L L L H H H H B L L H H L L H H C L H L H L H L H
Outputs Y H L L L L L L L
1A 1B 2A 2B 2C 2Y 1 2 3 4 5 6 7 Top View 14 VDD 13 1C 12 1Y 11 3C 10 3B 9 3A 8 3Y
VSS
Figure 1: Function Table Figure 3: Pin Out
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54HSC/T Series
54HSC/T32 : Quadruple 2-Input Positive OR Gates

The 54HSC/T32 is a Quadruple 2-Input Positive OR gate.
Outputs Y L H H H
Figure 3: Pin Out
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54HSC/T Series
54HSC/T86 : Quadruple 2-Input Exclusive OR Gates

The 54HSC/T86 is a Quadruple 2-Input Exclusive OR gate.
Outputs Y L H H L
Figure 3: Pin Out
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54HSC/T Series
54HSC/T125 : Quadruple Bus Buffer Gates with Tri-State Outputs (Active Low Enable)
The 54HSC/T125 is a Quadruple Bus Buffer Gate. When G is low the A input is transferred to the Y output. When G is high the output is in a high impedance state.
Inputs G L L H H A L H L H
Outputs Y L H Z Z
1G 1A 1Y 2G 2A 2Y VSS 1 2 3 4 5 6 7 Top View 14 VDD 13 4G 12 4A 11 4Y 10 3G 9 3A 8 3Y
H = high level, L = low level, Z = high impedance
Figure 3: Pin Out
+25C Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation delay A to Y Propagation delay A to Y Propagation delay G to Y Propagation delay G to Y Propagation delay Y to Tri-State Propagation delay Y to Tri-State Typ. 15 15 12 12 12 12 Figure 4: Switching Characteristics Max. 18 20 25 25 25 25
-55C / +125C Typ. 18 18 15 15 15 15 Max. 28 28 28 28 28 28 Units ns ns ns ns ns ns
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54HSC/T Series
54HSC/T125 : Quadruple Bus Buffer Gates with Tri-State Outputs (Active Low Enable)
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54HSC/T Series
54HSC/T126 : Quadruple Bus Buffer Gates with Tri-State Outputs (Active High Enable)
The 54HSC/T126 is a Quadruple Bus Buffer Gate. When G is high the A input is transferred tp the Y output. When G is low the output is in a high impedance state.
Inputs G H H L L A L H L H
Outputs Y L H Z Z
1G 1A 1Y 2G 2A 2Y VSS 1 2 3 4 5 6 7 Top View 14 VDD 13 4G 12 4A 11 4Y 10 3G 9 3A 8 3Y
H = high level, L = low level, Z = high impedance
Figure 3: Pin Out
+25C Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation delay A to Y Propagation delay A to Y Propagation delay G to Y Propagation delay G to Y Propagation delay Y to Tri-State Propagation delay Y to Tri-State Typ. 14 15 15 17 17 15 Figure 4: Switching Characteristics Max. 25 25 25 25 25 25
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54HSC/T Series
54HSC/T126 : Quadruple Bus Buffer Gates with Tri-State Outputs (Active High Enable)
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54HSC/T Series
54HSC/T74 : Dual D-Type Flip-Flops with Preset and Clear

The 54HSC/T74 is a Dual D-Type Flip-Flop. The D inputs are transferred to the Q outputs on the positive going edge of the clock pulse. The clear is active low.
Inputs PRESET L H L H H H CLEAR H L L H H H CLOCK X X X L-H L-H L D X X X H L X
Output Q H L H* H L Q0 Q L H H* L H Q0
H = high level, L = low level, X = irrelevant, * = unknown return state

1CLEAR 1D 1CLK 1PR 1Q 1Q VSS 1 2 3 4 5 6 7 Top View 14 VDD 13 2CLEAR 12 2D 11 2CLK 10 2PR 9 2Q 8 2Q
Figure 3: Pin Out
+25C Symbol tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation delay. Preset to Q or Q. Propagation delay. Preset to Q or Q. Propagation delay. Clear to Q or Q. Propagation delay. Clear to Q or Q. Propagation delay. Clock to Q or Q. Propagation delay. Clock to Q or Q. Typ. 15 16 18 15 17 18 Max. 20 20 20 20 25 25
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54HSC/T Series
54HSC/T74 : Dual D-Type Flip-Flops with Preset and Clear

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54HSC/T Series
54HSC/T109 : Dual J-KB Flip-Flops with Preset and Clear

The 54HSC/T109 is a Dual Positive-Edge-Triggered J-KB Flip-Flop with preset and clear. PRESET L
1CLR 1J 1K 1CK 1PR 1Q 1Q VSS 1 2 3 4 5 6 7 8 Top View 16 VDD 15 2CLR 14 2J 13 2K 12 2CK 11 2PR 10 2Q 9 2Q
Inputs CLEAR H L L H H H H H CLOCK X X X L J X X X L H L H X KB X X X L L H H X
Output Q H L H* L Q L H H* H
H L H H H H H
Toggle Toggle Q0 H Q0 Q0 L Q0
H = high level, L = low level, X = irrelevant, * = unknown return state
Figure 1: Pin Out
+25C Symbol tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation delay. Preset to Q or Q. Propagation delay. Preset to Q or Q. Propagation delay. Clear to Q or Q. Propagation delay. Clear to Q or Q. Propagation delay. Clock to Q or Q. Propagation delay. Clock to Q or Q. Typ. 15 16 17 15 18 15 Max. 19 25 25 25 25 25
Figure 4: Switching Characteristics 20/101
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54HSC/T Series
54HSC/T109 : Dual J-KB Flip-Flops with Preset and Clear

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54HSC/T Series
54HSC/T273 : Octal D-Type Flip-Flops

The 54HSC/T273 is an Octal D-Type Flip-Flop with a direct active low clear. The D-Inputs are transferred to the Q-Outputs on the positive going edge of the clock pulse.
CLEAR 1Q 1D 1 2 3 4 5 6 7 8 9 Top View 20 VDD 19 8Q 18 8D 17 7D 16 7Q 15 6Q 14 6D 13 5D 12 5Q 11 CLOCK
Inputs CLEAR L H H H CLOCK X L-H L-H L D X H L X
Outputs Q L H L Q0
2D 2Q 3Q 3D 4D 4Q
VSS 10
Q0 = level of Q before inputs were established H = high level, L = low level, X = irrelevant
Figure 2: Pin Out
+25C Symbol tPLH tPHL tPLH tPHL Parameter Propagation delay. Clear to Q or Q. Propagation delay. Clear to Q or Q. Propagation delay. Clock to Q or Q. Propagation delay. Clock to Q or Q. Typ. 14 16 15 17 Max. 25 25 25 25
-55C / +125C Typ. 17 19 18 20 Max. 28 28 28 28 Units ns ns ns ns
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54HSC/T Series
54HSC/T273 : Octal D-Type Flip-Flops

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54HSC/T Series
54HSC/T374 : Octal D-Type Edge-Triggered Flip-Flops

The 54HSC/T374 consists of 8 Positive-Edge Triggered DType Flip-Flops with tri-state output.
OC 1Q 1 2 3 4 5 6 7 8 9 Top View 20 VDD 19 8Q 18 8D 17 7D 16 7Q 15 6Q 14 6D 13 5D 12 5Q 11 CLK
Inputs OC L L L H CLOCK L X D H L X X
Outputs Q H L Q0 Z
1D 2D 2Q 3Q 3D 4D 4Q
H = high level, L = low level, X = irrelevant, Z = high impedance
GND 10
Figure 1: Function Table Figure 2: Pin Out +25C Symbol tPLH tPHL tPZL tPZH tPLZ tPHZ Parameter Propagation delay. Low to high output. Propagation delay. High to low output. Propagation delay. Enable to low. Propagation delay. Enable to high. Propagation delay. Disable from low. Propagation delay. Disable from high. Min. Typ. 14 15 13 16 14 13 Max. 22 22 20 20 20 18 Min. -55C / +125C Typ. 17 16 16 18 16 15 Max. 25 25 25 23 22 20 Units ns ns ns ns ns ns
Limits +25C Symbol IDD VOL VOH VIL1 VIH1 VIL2 VIH2 IOZ IIN Parameter Quiescent Current Output Voltage Low Level Output Voltage High Level Voltage Input Low (CMOS) Voltage Input High (CMOS) Voltage Input Low (TTL) Voltage Input High (TTL) Tri-State Leakage Input Leakage Current Test Conditions VIN = 0V or VDD IOL = 9mA IOH = -11mA VO = 0V or VDD VIN = VDD or VSS Figure 4: DC Characteristics 24/101 Min. 2.5 3.5 2.0 Max. 20 0.4 1.5 0.8 1 0.5 -55C / +125C Min. 2.5 3.5 2.0 Max. 600 0.4 1.5 0.8 50 5.0 Units A V V V V V V A A
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54HSC/T Series
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54HSC/T Series

The 54HSC/T574 consists of 8 Positive-Edge Triggered DType Flip-Flops with tri-state output.
OC 1D 1 2 3 4 5 6 7 8 9 Top View 20 VDD 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q 11 CLK
Inputs OC L L L H CLOCK L X D H L X X
Outputs Q H L Q0 Z
2D 3D 4D 5D 6D 7D 8D
GND 10
Figure 1: Function Table Figure 2: Pin Out +25C Symbol tPLH tPHL tPZL tPZH tPLZ tPHZ Parameter Propagation delay. Low to high output. Propagation delay. High to low output. Propagation delay. Enable to low. Propagation delay. Enable to high. Propagation delay. Disable from low. Propagation delay. Disable from high. Min. Typ. 16 19 13 16 14 13 Max. 25 27 21 24 22 21 Min. -55C / +125C Typ. 19 22 16 19 17 16 Max. 28 30 24 27 25 24 Units ns ns ns ns ns ns
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54HSC/T Series
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54HSC/T Series
54HSC/T283 : 4-Bit Binary Full Adders with Fast Carry

The 54HSC/T283 are 4-Bit Binary Full Adders with fast carry.
Input
Output When CO=L / When C2=L When CO=H / When C2=H

2 B2 A2 1 A1 B1 CO GND 1 2 3 4 5 6 7 8 Top View 16 VCC 15 B3 14 A3 13 3 12 A4 11 B4 10 4 9 C4
A1/A3 L H L H L H L H L H L H L H L H
B1/B3 L L H H L L H H L L H H L L H H
A2/A4 L L L L H H H H L L L L H H H H
B2/B4 L L L L L L L L H H H H H H H H
1/3
L H H L L H H L L H H L L H H L
2/4 C2/C4
L L L H H H H L H H H L L L L H L L L L L L L H L L L H H H H H
1/3
H L L H H L L H H L L H H L L H
2/4
L H H H H L L L H L L L L H H H
C2/C4 L L L L L H H H L H H H H H H H
Figure 2: Pin Out
+25C Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation delay. C0 to any . Propagation delay. C0 to any . Propagation delay. Ai or Bi to i. Propagation delay. Ai or Bi to i. Propagation delay. C0 to C4. Propagation delay. C0 to C4. Propagation delay. Ai or Bi to C4. Propagation delay. Ai or Bi to C4. Typ. 13 12 14 12 11 16 15 14 Max. 25 25 25 25 25 25 25 25
-55C / +125C Typ. 16 15 17 15 14 19 19 17 Max. 28 28 28 28 28 28 28 28 Units ns ns ns ns ns ns ns ns
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54HSC/T Series
54HSC/T161 : 4-Bit Synchronous Binary Counter

The 54HSC/T161 is a Synchronous 4-Bit Binary Counter which features direct clear and an internal carry look-ahead. Inputs Clear L H H H H H H Enable P X L X X X X H Enable T X X L X X X H AD X X X Qn X X X Load X H H L X X H Clock X X X L H Output QAQD 0 Inhibit Inhibit Qn Q0 Q0 Count
CARRY = H when QAQD = H, Q0 = previous level of Q H = high level, L = low level, X = irrelevant
CLEAR CLOCK A B C D ENABLE P VSS
1 2 3 4 5 6 7 8 Top View
16 VDD 15 RCO 14 QA 13 QB 12 QC 11 QD 10 ENABLE T 9 LOAD
Figure 2: Pin Out +25C Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL From (Input) CLOCK CLOCK CLOCK (Load Input HIGH) CLOCK (Load Input HIGH) CLOCK (Load Input LOW) CLOCK (Load Input LOW) ENABLE ENABLE CLEAR To (Output) RIPPLE CARRY RIPPLE CARRY Any Q Output Any Q Output Any Q Output Any Q Output RIPPLE CARRY RIPPLE CARRY Any Q Output Typ. 20 19 16 15 15 15 14 14 18 Max. 25 25 25 25 25 25 25 25 25 -55C / +125C Typ. 23 22 19 18 18 18 17 17 21 Max. 28 28 28 28 28 28 28 28 28 Units ns ns ns ns ns ns ns ns ns
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54HSC/T Series
54HSC/T163 : Synchronous 4-Bit Counter

The 54HSC/T163 is a 4-Bit Counter with synchronous clear.
Inputs Clear L H H H H H H Enable P X L X X X X H Enable T X X L X X X H AD X X X Qn X X X Load X H H L X X H Clock X X X L H
Output QAQD 0 Inhibit Inhibit Qn Q0 Q0 Count
CARRY = H when QAQD = H, Q0 = previous level of Q H = high level, L = low level, X = irrelevant
CLEAR CLK A B C D ENP GND
1 2 3 4 5 6 7 8 Top View
16 VDD 15 RCO 14 QA 13 QB 12 QC 11 QD 10 ENT 9 LOAD
Figure 2: Pin Out
+25C Symbol tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation delay Clock to RCO Propagation delay Clock to RCO Propagation delay Clock to any Q Propagation delay Clock to any Q Propagation delay ENT to RCO Propagation delay ENT to RCO Typ. 12 14 15 13 9 10 Figure 3: Switching Characteristics Max. 20 20 20 20 15 15
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54HSC/T Series

The 54HSC/T191 is a 4-Bit Synchronous Counter with presettable up/down and asynchronous reset.
Inputs PL H H L H CE L L X H U/D L H X X CP X X Function Count Up Count Down Asyn. Preset No Change

P1 Q1 Q0 CE U/D Q2 Q3 GND 1 2 3 4 5 6 7 8 Top View 16 VCC 15 P0 14 CP 13 RC 12 TC 11 PL 10 P2 9 P3
H = high level, L = low level, X = irrelevant, = low-to-high clock (CP) transition. Note: U/D or CE should be changed only when clock (CP) is high.
Figure 1: Function Table Figure 2: Pin Out
+25C Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation delay PL to Qn Propagation delay PL to Qn Propagation delay Pn to Qn Propagation delay Pn to Qn Propagation delay CP to Qn Propagation delay CP to Qn Propagation delay CP to RC Propagation delay CP to RC Propagation delay CP to TC Propagation delay CP to TC Propagation delay U/D to RC Propagation delay U/D to RC Propagation delay U/D to TC Propagation delay U/D to TC Propagation delay CE to RC Propagation delay CE to RC Typ. Figure 3: Switching Characteristics Max. 29 32 27 30 26 29 20 32 29 32 27 30 26 29 22 35
-55C / +125C Typ. Max. 33 36 31 34 30 33 23 34 33 36 31 34 30 33 25 38 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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54HSC/T Series

P0 15 14 CP 5 U/D 11 PL
P1 1
P2 10
P3 9
13 RC
12 TC
PL P T CP FF0 Q Q P T CP
PL P Q Q T CP
PL P Q Q FF2 T CP
PL Q Q
FF1
FF3
4 CE
3 Q0
2 Q1
6 Q2
7 Q3
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54HSC/T Series
54HSC/T138 : 3-Line to 8-Line Decoder/Multiplexer

The 54HSC/T138 is a 3-Line to 8-Line Decoder/Multiplexer, with inverted outputs. Enable Inputs G1 X X L H H H H H H H H G2A H X X L L L L L L L L G2B X H X L L L L L L L L C X X X L L L L H H H H Select Inputs B X X X L L H H L L H H A X X X L H L H L H L H Y0 H H H L H H H H H H H Y1 H H H H L H H H H H H Y2 H H H H H L H H H H H Outputs Y3 H H H H H H L H H H H Y4 H H H H H H H L H H H Y5 H H H H H H H H L H H Y6 H H H H H H H H H L H Y7 H H H H H H H H H H L
A B C G2A G2B G1 YZ VSS
1 2 3 4 5 6 7 8 Top View
16 VDD 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6
Figure 2: Pin Out
+25C Symbol tPLH tPHL tPLH tPHL Parameter Propagation delay. Address to Output. Propagation delay. Address to Output. Propagation delay. G to Output. Propagation delay. G to Output. Typ. 17 19 21 21 Figure 3: Switching Characteristics Max. 25 25 25 25
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54HSC/T Series
54HSC/T138 : 3-Line to 8-Line Decoder/Multiplexer

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54HSC/T Series
54HSC/T139 : Dual 2 to 4 Decoders/Multiplexers

The 54HSC/T139 consists of Two Independent 2 to 4 Line Decoder/Multiplexers. Inputs Enable G H L L L L B X L L H H Select A X L H L H Y0 H L H H H Y1 H H L H H Y2 H H H L H Y3 H H H H L Output
1G 1A 1B 1Y0 1Y1 1Y2 1Y3 VSS
1 2 3 4 5 6 7 8 Top View
16 VDD 15 2G 14 2A 13 2B 12 2Y0 11 2Y1 10 2Y2 9 2Y3
Figure 2: Pin Out
+25C Symbol tPLH tPHL tPLH tPHL Parameter Propagation delay. Address to Output. Propagation delay. Address to Output. Propagation delay. G to Output. Propagation delay. G to Output. Typ. 16 17 16 17 Figure 3: Switching Characteristics Max. 28 28 22 22
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54HSC/T Series
54HSC/T139 : Dual 2 to 4 Decoders/Multiplexers

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54HSC/T Series
54HSC/T148 : 8-Line to 3-Line Octal Priority Encoders

The 54HSC/T148 is an 8 to 3 Line Priority Encoder. Data inputs and outputs are active at the low logic level. Data is accepted on the eight priority inputs (I0-I7). The binary code, corresponding to the highest priority input which is low, is generated on the address outputs (A0-A2) if the enable input is high. The group select (GS) is low when one or more priority inputs and the enable input (EI) are low. The enable output (EO) is low when all priority inputs are high and the enable is low. When the enable input is high all outputs are high.
I4 I5 I6 I7 EI A2 A1 VSS
1 2 3 4 5 6 7 8 Top View
16 VDD 15 EO 14 GS 13 I3 12 I2 11 I1 10 I0 9 A0
Figure 1: Pin Out Inputs EI H L L L L L L L L L I0 X H X X X X X X X L I1 X H X X X X X X L H I2 X H X X X X X L H H I3 X H X X X X L H H H I4 X H X X X L H H H H I5 X H X X L H H H H H I6 X H X L H H H H H H I7 X H L H H H H H H H A2 H H L L L L H H H H A1 H H L L H H L L H H Outputs A0 H H L H L H L H L H GS H H L L L L L L L L EO H L H H H H H H H H
Figure 2: Function Table +25C Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation delay EI to A Propagation delay EI to A Propagation delay EI to GS Propagation delay EI to GS Propagation delay EI to EO Propagation delay EI to EO Propagation delay I to A Propagation delay I to A Typ. 14 15 15 15 14 15 12 14 Figure 3: Switching Characteristics 43/101 Max. 22 22 22 22 22 22 22 22 -55C / +125C Typ. 17 18 18 18 17 18 15 17 Max. 28 28 28 28 28 28 28 28 Units ns ns ns ns ns ns ns ns
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54HSC/T Series

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54HSC/T Series
54HSC/T151 : 1 of 8 Data Selectors/Multiplexers

The 54HSC/T151 is a 1 of 8 Data Selector. When the strobe input is low the device is enabled. When high this forces the W-output high and the Youtput low.
Inputs Select C X L L L L H H H H B X L L H H L L H H A X L H L H L H L H Strobe STR H L L L L L L L L Y L D0 D1 D2 D3 D4 D5 D6 D7
Output
D3 D2 1 2 3 4 5 6 7 8 Top View 16 VDD 15 D4 14 D5 13 D6 12 D7 11 A 10 B 9 C
W H D0 D1 D2 D3 D4 D5 D6 D7
D1 D0 Y W STR VSS
Figure 2: Pin Out
+25C Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation delay A B or C to Y Propagation delay A B or C to Y Propagation delay A B or C to W Propagation delay A B or C to W Propagation delay Strobe to Y Propagation delay Strobe to Y Propagation delay Strobe to W Propagation delay Strobe to W Propagation delay D0-D7 to Y Propagation delay D0-D7 to Y Propagation delay D0-D7 to W Propagation delay D0-D7 to W Typ. 15 16 14 15 14 16 14 15 12 14 12 14 Figure 3: Switching Characteristics Max. 22 22 22 22 22 22 22 22 22 22 22 22
-55C / +125C Typ. 18 19 17 18 17 19 17 18 15 17 15 17 Max. 25 25 25 25 25 25 25 25 25 25 25 25 Units ns ns ns ns ns ns ns ns ns ns ns ns
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54HSC/T Series

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54HSC/T Series
54HSC/T154 : 4 to 16 Line Decoders/Demultiplexers

The 54HSC/T154 consists of a 4 to 16 Line Decoder/Demultiplexer. Inputs G1 L L L L L L L L L L L L L L L L L H H G2 L L L L L L L L L L L L L L L L H L H D L L L L L L L L H H H H H H H H X X X C L L L L H H H H L L L L H H H H X X X B L L H H L L H H L L H H L L H H X X X A L H L H L H L H L H L H L H L H X X X 0 L H H H H H H H H H H H H H H H H H H 1 H L H H H H H H H H H H H H H H H H H 2 H H L H H H H H H H H H H H H H H H H 3 H H H L H H H H H H H H H H H H H H H 4 H H H H L H H H H H H H H H H H H H H 5 H H H H H L H H H H H H H H H H H H H 6 H H H H H H L H H H H H H H H H H H H Outputs 7 H H H H H H H L H H H H H H H H H H H 8 H H H H H H H H L H H H H H H H H H H 9 H H H H H H H H H L H H H H H H H H H 10 H H H H H H H H H H L H H H H H H H H 11 H H H H H H H H H H H L H H H H H H H 12 H H H H H H H H H H H H L H H H H H H 13 H H H H H H H H H H H H H L H H H H H 14 H H H H H H H H H H H H H H L H H H H 15 H H H H H H H H H H H H H H H L H H H
0 1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8 9 Top View
24 VDD 23 A 22 B 21 C 20 D 19 G2 18 G1 17 15 16 14 15 13 14 12 13 11
9 10 10 11 VSS 12
Figure 2: Pin Out 49/101
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54HSC/T Series

+25C Sym tPLH tPHL tPLH tPHL Parameter Propagation delay low to high level output for change in A B C or D input Propagation delay high to low level output for change in A B C or D input Propagation delay low to high level output for change in G1 or G2 Propagation delay high to low level output for change in G1 or G2 Typ. 18 21 21 18 Max. 30 30 30 30 -55C / +125C Typ. 21 24 24 21 Max. 33 33 33 33 Units ns ns ns ns
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54HSC/T Series
54HSC/T157 : Quad 2-Line to 1-Line Data Selectors/Multiplexers

The 54HSC/T157 is a Quadruple 2-Line to 1-Line Data Selector with non-inverted output. The strobe must be low to enable the device. When select is low, A is selected. When select is high, B is selected. Inputs STR H L L L L Select X L L H H A X L H X X B X X X L H Outputs Y L L H L H Figure 2: Pin Out
SEL 1A 1B 1Y 2A 2B 2Y VSS
1 2 3 4 5 6 7 8 Top View
16 VDD 15 STR 14 4A 13 4B 12 4Y 11 3A 10 3B 9 3Y
+25C Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation delay A or B to Y Propagation delay A or B to Y Propagation delay Strobe to Y Propagation delay Strobe to Y Propagation delay Select to Y Propagation delay Select to Y Typ. 14 15 14 15 14 15 Figure 3: Switching Characteristics Max. 25 20 22 22 25 25
Limits +25C Symbol IDD VOL VOH VIL1 VIH1 VIL2 VIH2 IIN Parameter Quiescent Current Output Voltage Low Level Output Voltage High Level Voltage Input Low (CMOS) Voltage Input High (CMOS) Voltage Input Low (TTL) Voltage Input High (TTL) Input Leakage Current Test Conditions VIN = 0V or VDD IOL = 9mA IOH = -11mA VIN = VDD or VSS Figure 4: DC Characteristics 52/101 Min. 2.5 3.5 2.0 Max. 20 0.4 1.5 0.8 0.5 -55C / +125C Min. 2.5 3.5 2.0 Max. 600 0.4 1.5 0.8 5.0 Units A V V V V V V A
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54HSC/T Series
54HSC/T157 : Quad 2-Line to 1-Line Data Selectors/Multiplexers
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54HSC/T Series
54HSC/T238 : 3-Line to 8-Line Decoder/Demultiplexer

The 54HSC/T238 is a 3-Line to 8-Line Decoder/Demultiplexer, with unlatched inputs and non-inverted outputs.
Enable Inputs E3 X L H H H H H H H H E2/E1 H X L L L L L L L L A2 X X L L L L H H H H
Select Inputs A1 X X L L H H L L H H A0 X X L H L H L H L H O0 L L H L L L L L L L O1 L L L H L L L L L L O2 L L L L H L L L L L
Outputs O3 L L L L L H L L L L O4 L L L L L L H L L L O5 L L L L L L L H L L O6 L L L L L L L L H L O7 L L L L L L L L L H
A0 A1 A2 E1 E2 E3 O7 VSS
1 2 3 4 5 6 7 8 Top View
16 VDD 15 O0 14 O1 13 O2 12 O3 11 O4 10 O5 9 O6
Figure 2: Pin Out
+25C Symbol tPLH tPHL tPLH tPHL Parameter Propagation delay, address to output, low to high level output Propagation delay, address to output, high to low level output Propagation delay, enable to output, low to high level output Propagation delay, enable to output, high to low level output Typ. 16 17 19 19 Max. 24 25 27 27
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54HSC/T Series
54HSC/T238 : 3-Line to 8-Line Decoder/Demultiplexer

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54HSC/T Series
54HSC/T253 : Dual 4 to 1 Data Selectors/Multiplexers

The 54HSC/T253 is a Dual 4-Line to 1-Line Data Selector/Multiplexer with tri-state outputs. Output Control C3 X X X X X X X L H G H L L L L L L L L
Select Inputs B X L L L L H H H H A X L L H H L L H H C0 X L H X X X X X X
Data Inputs C1 X X X L H X X X X C2 X X X X X L H X X
Output Y Z L H L H L H L H
1G B 1C3 1C2 1C1 1C0 1Y VSS
1 2 3 4 5 6 7 8 Top View
16 VDD 15 2G 14 A 13 2C3 12 2C2 11 2C1 10 2C0 9 2Y
Figure 2: Pin Out
+25C Symbol tPLH tPHL tPLH tPHL tPZL tPZH tPLZ tPHZ Parameter Propagation delay Data to Output Propagation delay Data to Output Propagation delay Select to Output Propagation delay Select to Output Propagation delay Tri-state to Output Low Propagation delay Tri-state to Output High Propagation delay Low to Tri-state Propagation delay High to Tri-state Typ. 14 15 14 15 12 13 12 13 Max. 25 25 25 25 25 25 25 25
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54HSC/T Series
54HSC/T253 : Dual 4 to 1 Data Selectors/Multiplexers

Limits +25C Symbol IDD VOL VOH VIL1 VIH1 VIL2 VIH2 IOZ IIN Parameter Quiescent Current Output Voltage Low Level Output Voltage High Level Voltage Input Low (CMOS) Voltage Input High (CMOS) Voltage Input Low (TTL) Voltage Input High (TTL) Tri-State Leakage Input Leakage Current Test Conditions VIN = 0V or VDD IOL = 9mA IOH = -11mA VO = 0V or VDD VIN = VDD or VSS Figure 4: DC Characteristics Min. 2.5 3.5 2.0 Max. 20 0.4 1.5 0.8 1 0.5 -55C / +125C Min. 2.5 3.5 2.0 Max. 600 0.4 1.5 0.8 50 5.0 Units A V V V V V V A A
Figure 5: Logic Diagram 57/101
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54HSC/T Series
54HSC/T164 : 8-Bit Parallel Output Serial Shift Register

The 54HSC/T164 is an 8-Bit Parallel Output Serial Shift Register with asynchronous clear.
Inputs CLEAR CLOCK L H H H H X L A X X H L X B X X H X L QA L QAO H L L
Outputs QB L QBO QAN QAN QAN QH L QHO QGN QGN QGN

A B QA QB QC QD VSS 1 2 3 4 5 6 7 Top View 14 VDD 13 QH 12 QG 11 QF 10 QE 9 CLEAR 8 CLOCK
H = high level, L = low level, X = irrelevant, = transition from low to high level. QAO, QBO, QHO = the level of QA, QB or QH, respectively, before the indicated steady-state input conditions were set up. QAN, QBN, QHN = the level of QA or QG before the latest transition of the clock. Indicates a one bit shift.
Figure 2: Pin Out
+25C Symbol tPLH tPHL tPHL Parameter Propagation delay. Q output from clock input, low to high level output. Propagation delay. Q output from clock input, high to low level output. Propagation delay. Q output from clear input, high to low level output. Typ. 15 15 15 Max. 25 25 25
-55C / +125C Typ. 18 18 18 Max. 28 28 28 Units ns ns ns
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54HSC/T Series
54HSC/T164 : 8-Bit Parallel Output Serial Shift Register
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54HSC/T Series
54HSC/T165 : Parallel Load 8-Bit Shift Register

The 54HSC/T165 is an 8-Bit Serial Shift Register that shifts the data in the direction of QA to QH when clocked. Inputs Shift/ Load L H H H H Clock Inhibit X L L L H Clock X L X Serial X X H L X Parallel A...H a...h X X X X Internal Outputs QA a QAO H L QAO QB b QBO QAN QAN QBO Output QH h QHO QGN QGN QHO
H = high level, L = low level, X = irrelevant, = transition from low to high, a...h = the level of steady state inputs at inputs A through H. QO = level of Q before the indicated steady state input conditions were set up. QN = level of Q before the most recent active transition indicated by .
SHIFT/LOAD CLOCK E F G H QH VSS
1 2 3 4 5 6 7 8 Top View
16 VDD 15 CLOCK INHIBIT 14 D 13 C 12 B 11 A 10 SERIAL INPUT 9 QH
Figure 2: Pin Out
+25C Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation delay. Load to Any Output. Propagation delay. Load to Any Output. Propagation delay. Clock to Any Output. Propagation delay. Clock to Any Output. Propagation delay. H to QH. Propagation delay. H to QH. Propagation delay. H to QBH. Propagation delay. H to QBH. Typ. 18 16 18 18 18 18 18 18 Figure 3: Switching Characteristics 60/101 Max. 25 25 25 25 25 25 25 25
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54HSC/T Series
54HSC/T165 : Parallel Load 8-Bit Shift Register

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54HSC/T Series
54HSC/T166 : 8-Bit Shift Register

The 54HSC/T166 is an 8-Bit parallel in or serial in, serial out Shift Register with a gated clock input and an overriding clear input.
Inputs Clear L H H H H H Shift/ Load X X L H H X Clock Inhibit X L L L L H Clock X L Serial X X X H L X Parallel A...H X X a...h X X X
Internal Outputs QA L QAO a H L QAO QB L QBO b QAN QAN QBO
Output QH L QHO h QGN QGN QHO
H = high level, L = low level, X = irrelevant, = transition from low to high, a...h = the level of steady state inputs at inputs A through H. QO = level of Q before the indicated steady state input conditions were set up. QN = level of Q before the most recent active transition indicated by .
SERIAL INPUT A B C D CLOCK INHIBIT CLOCK VSS
1 2 3 4 5 6 7 8 Top View
16 VDD 15 SHIFT/LOAD 14 H 13 QH 12 G 11 F 10 E 9 CLEAR
Figure 2: Pin Out
+25C Symbol tPHL tPHL tPLH Parameter Propagation delay. Clear to QH. Propagation delay. Clock to QH. Propagation delay. Clock to QH. Typ. 15 15 15 Figure 3: Switching Characteristics Max. 25 25 25
-55C / +125C Typ. 18 18 18 Max. 28 28 28 Units ns ns ns
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Figure 5: Logic Diagram 64/101
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54HSC/T Series
54HSC/T521 : 8-Bit Magnitude Comparator

The 54HSC/T521 is an 8-Bit Magnitude Comparator. Inputs Data P,Q Enable G P=Q P>Q P<Q X L L L H Outputs P=Q L H H H
G P0 Q0 P1 Q1 P2 Q2 P3 Q3
1 2 3 4 5 6 7 8 9 Top View
20 VDD 19 P = Q 18 Q7 17 P7 16 Q6 15 P6 14 Q5 13 P5 12 Q4 11 P4
VSS 10
Figure 2: Pin Out
Figure 3: Logic Diagram +25C Symbol tPLH tPHL tPLH tPHL Parameter Propagation delay. P or Q to PN = QN. Propagation delay. P or Q to PN = QN. Propagation delay. GN to PN = QN. Propagation delay. GN to PN = QN. Typ. 15 16 14 15 Max. 25 25 25 25 -55C / +125C Typ. 18 19 17 18 Max. 28 28 28 28 Units ns ns ns ns
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54HSC/T Series
54HSC/T521 : 8-Bit Magnitude Comparator

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54HSC/T Series
54HSC/T240 : Octal 3-State Driver, Inverting

The 54HSC/T240 is an Octal 3-State Driver, inverting. Inputs E L L H I0-3 L H X Outputs O0-3 H L Z
H = high level L = low level X = irrelevant Z = high impedance
EA I0A O0B I1A O1B 12A O2B I3A O3B
1 2 3 4 5 6 7 8 9 Top View
20 VDD 19 EB 18 O0A 17 I0B 16 O1A 15 I1B 14 O2A 13 I2B 12 O3A 11 I3B
VSS 10
Figure 2: Pin Out
+25C Symbol tPLH tPHL tPZL tPZH tPLZ tPHZ Parameter Propagation delay, low to high level output. Propagation delay, high to low level output. Propagation delay, enable to low level. Propagation delay, enable to high level. Propagation delay, disable from low. Propagation delay, disable from high. Typ. 12 14 19 14 22 21 Max. 20 22 27 22 30 30
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54HSC/T Series
54HSC/T240 : Octal 3-State Driver, Inverting

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54HSC/T Series
54HSC/T241 : Octal 3-State Driver, Complementary Enable

The 54HSC/T241 is an Octal 3-State Driver, complementary enable. Inputs EA L L H EB H H L I0-3 L H X Outputs O0-3 H L Z
1 2 3 4 5 6 7 8 9 Top View
VSS 10
Figure 2: Pin Out
+25C Symbol tPLH tPHL tPZL tPZH tPLZ tPHZ Parameter Propagation delay, low to high level output. Propagation delay, high to low level output. Propagation delay, enable to low level. Propagation delay, enable to high level. Propagation delay, low to disable. Propagation delay, high to disable. Typ. 11 13 19 19 22 21 Max. 19 21 27 27 30 30
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54HSC/T Series
54HSC/T241 : Octal 3-State Driver, Complementary Enable

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54HSC/T Series
54HSC/T244 : Octal 3-State Driver

The 54HSC/T244 is an Octal 3-State Driver. Inputs E L L H I0-3 L H X Outputs O0-3 H L Z
1 2 3 4 5 6 7 8 9 Top View
VSS 10
Figure 2: Pin Out
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54HSC/T Series
54HSC/T244 : Octal 3-State Driver

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54HSC/T Series
54HSC/T540 : Octal 3-State Driver/Buffer Inverting

The 54HSC/T540 is an Octal 3-State Driver/Buffer Inverting. Inputs EA L L H X EB L L X H I0-7 L H X X Outputs O0-7 H L Z Z
EA I0 I1 I2 I3 I4 I5 I6 I7
1 2 3 4 5 6 7 8 9 Top View
20 VDD 19 EB 18 O0 17 O1 16 O2 15 O3 14 O4 13 O5 12 O6 11 O7
VSS 10
Figure 2: Pin Out
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54HSC/T Series
54HSC/T540 : Octal 3-State Driver/Buffer Inverting

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54HSC/T Series
54HSC/T541 : Octal 3-State Driver/Buffer

The 54HSC/T541 is an Octal 3-State Driver/Buffer. Inputs EA L L H X EB L L X H I0-7 L H X X Outputs O0-7 L H Z Z
EA I0 I1 I2 I3 I4 I5 I6 I7
1 2 3 4 5 6 7 8 9 Top View
20 VDD 19 EB 18 O0 17 O1 16 O2 15 O3 14 O4 13 O5 12 O6 11 O7
VSS 10
Figure 2: Pin Out
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54HSC/T Series
54HSC/T541 : Octal 3-State Driver/Buffer

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54HSC/T Series
54HSC/T245 : Octal Bus Transceiver

The 54HSC/T245 is an Octal Bus Transceiver. Inputs E L L H DIR L H X B data to Bus A A data to Bus B Isolation Outputs
DIR A0 A1 A2 A3 A4 A5 A6 A7
1 2 3 4 5 6 7 8 9 Top View
20 VDD 19 E 18 B0 17 B1 16 B2 15 B3 14 B4 13 B5 12 B6 11 B7
VSS 10
Figure 2: Pin Out
Figure 3: Logic Diagram +25C Symbol tPLH tPHL tPZL tPZH tPLZ tPHZ Parameter Propagation delay, low to high level output. Propagation delay, high to low level output. Propagation delay, enable to low level. Propagation delay, enable to high level. Propagation delay, low to disable. Propagation delay, high to disable. Typ. 10 11 21 16 24 24 Max. 19 19 26 25 28 28 -55C / +125C Typ. 13 14 24 19 27 27 Max. 23 23 30 28 33 33 Units ns ns ns ns ns ns
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54HSC/T Series
54HSC/T245 : Octal Bus Transceiver

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54HSC/T Series
54HSC/T373 : Octal Transparent Latch, 3-State Outputs

The 54HSC/T373 is an Octal Transparent Latch with 3-State Outputs. Inputs OC L L L H C H H L X D H L X X Outputs Q H L Q0 Z
OC 1Q 1D 2D 2Q 3Q 3D 4D 4Q
1 2 3 4 5 6 7 8 9 Top View
20 VDD 19 8Q 18 8D 17 7D 16 7Q 15 6Q 14 6D 13 5D 12 5Q 11 C
VSS 10
Figure 2: Pin Out +25C Symbol tPLH tPHL tPZL tPZH tPLZ tPHZ Parameter Propagation delay. Low to high output. Propagation delay. High to low output. Propagation delay. Enable to low. Propagation delay. Enable to high. Propagation delay. Low to disable. Propagation delay. High to disable. Min. Typ. 15 14 13 16 14 13 Max. 20 20 25 20 25 25 Min. -55C / +125C Typ. 20 21 14 18 18 19 Max. 24 24 25 24 25 25 Units ns ns ns ns ns ns
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54HSC/T Series
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54HSC/T Series

The 54HSC/T573 is an Octal Transparent Latch with 3-State Outputs. Inputs OC L L L H C H H L X D H L X X Outputs Q H L Q0 Z
OC 1D 2D 3D 4D 5D 6D 7D 8D
1 2 3 4 5 6 7 8 9 Top View
20 GND 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q 11 C
VSS 10
Figure 2: Pin Out +25C Symbol tPLH tPHL tPZL tPZH tPLZ tPHZ Parameter Propagation delay. Low to high output. Propagation delay. High to low output. Propagation delay. Enable to low. Propagation delay. Enable to high. Propagation delay. Low to disable. Propagation delay. High to disable. Min. Typ. 19 19 13 16 14 13 Max. 24 24 21 24 22 21 Min. -55C / +125C Typ. 22 22 16 19 17 16 Max. 29 29 24 27 25 24 Units ns ns ns ns ns ns
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54HSC/T Series
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54HSC/T Series
54HSC/T670 : 4 x 4 Register Files with Tri-State Outputs

The 54HSC/T670 is a register storing 4 words of 4 bits each. Separate on-chip decoding is provided for addressing the four word locations to either write or retrieve data. This allows simultaneous writing into one location and reading from another location.
D2 D3 D4 RB RA Q4 Q3 VSS 1 2 3 4 5 6 7 8 Top View 16 VDD 15 D1 14 WA 13 WB 12 GW 11 GR 10 Q1 9 Q2
Figure 1: Pin Out
Write Inputs WB L L H H X WA L H L H X GW L L L L H 1 Q=D Q0 Q0 Q0 Q0 2
Word 3 Q0 Q0 Q=D Q0 Q0 4 Q0 Q0 Q0 Q=D Q0 WB L L H H X
Read Inputs WA L H L H X GW L L L L H 1 W1D1 W2D1 W3D1 W4D1 Z
Outputs 2 W1D2 W2D2 W3D2 W4D2 Z 3 W1D3 W2D3 W3D3 W4D3 Z 4 W1D4 W2D4 W3D4 W4D4 Z
Q0 Q=D Q0 Q0 Q0
Q0 = level of Q before inputs were established H = high level, L = low level, X = irrelevant
Figure 3: Read Function Table
Figure 2: Write Function Table
+25C Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation delay. Read select to Q. Propagation delay. Read select to Q. Propagation delay. Write enable to Q. Propagation delay. Write enable to Q. Propagation delay. Data to Q. Propagation delay. Data to Q. Propagation delay. Read Enable to Q. Propagation delay. Read Enable to Q. Propagation delay. Read Enable to Q. Propagation delay. Read Enable to Q. Typ. 25 18 18 18 27 23 18 18 18 18 Max. 30 25 25 25 35 25 25 25 25 25
-55C / +125C Typ. 28 21 21 21 30 26 21 21 21 21 Max. 33 28 28 28 38 28 28 28 28 28 Units ns ns ns ns ns ns ns ns ns ns
VCC = 5V, TMAX = +125C, CL = 50pF
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CHARACTERISATION DATA
Device base listing as below: MA9003 Base 00 02 03 04 08 10 14 21 27 32 74 86 109 125 126 148 151 157 164 253 Pin Count 14 14 14 14 14 14 14 14 14 14 14 14 16 14 14 16 16 16 14 16 MA9007 Base 154 161 163 165 166 191 273 283 670 Pin Count 24 16 16 16 16 16 20 16 16 BMS011 Base 138 139 238 240 241 244 245 373 374 521 540 541 573 574 Pin Count 16 16 16 20 20 20 20 20 20 20 20 20 20 20
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PACKAGE: LI/AS/4/IN/02001 - 14 Lead Bottombraze Flatpack (MIL-STD-38510H)
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FINISHED PRODUCT OUTLINE: LI/AS/4/IN/02001 - 14 Lead Bottombraze Flatpack (MIL-STD-38510H)
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PACKAGE OUTLINE: XG 257 - 20 Lead Bottombraze Flatpack (MIL-STD-38510H)
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PACKAGE OUTLINE: 16 Lead Bottombraze Flatpack (MIL-STD-38510H)
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FINISHED PRODUCT OUTLINE: 24 Lead Ceramic Flatpack (MIL-M-38510)
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FINISHED PRODUCT OUTLINE: 16 Lead Flatpack (MIL-M-38510H)
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DYNAMIC Idd for OCTAL DEVICE BASES

BMS011 Base
STATIC Idd (A)
STATIC Idd Vs RADIATION

450 400 350 300 250 200 150 100 50 9003 Base 9007 Base BMS011 Base
15
DYNAMIC Idd (mA)
10
9007 Base 9003 Base
0
1 10 FREQUENCY (MHz) 100
100 200 RAD LEVELS (Krads)
300
STATIC Idd Vs TEMP.
IOZL Vs TEMP.
30
BMS011 Base 9007 Base
250 200 150 100 50 0
25 20
BMS011 Base 9007 Base 9003 Base
9003 Base
IOZL (-A)
Idd (A)
15 10 5 0
-100
-50
50
100
150
20
40
60
80
100
120
140
TEMPERATURE (deg C)
TEMPERATURE (deg C)
IOZH Vs TEMP.
300 250 200 150 100 50 0 0 20 40 60 80 100 120 140 TEMPERATURE (deg C) BMS011 Base 9007 Base 9003 Base 350 300 250
IIL Vs TEMP.
9003 Base
IOZH (nA)
IIL (-nA)
200 150 100 50 0 0 20 40 60 80 100 TEMPERATURE (deg C) 120 140 9007 Base BMS011 Base
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IIH Vs TEMP.
VOL Vs TEMP.
0.22 9007 Base BMS011 Base
500 400 300 200 100 0

9003 Base
VOL (V)
0.2 0.18
IIH (nA)
0.16 0.14 0.12 0.1 0.08 -60 -40 -20 0 20 40 60
9003 Base
9007 Base BMS011 Base
20
40
60
80
100
120
140
80 100 120 140
TEMPERATURE (deg C)
TEMPERATURE (deg C)
VOH Vs TEMP.
4.1 4.0 3.9
VOH (V)
VOL Vs IOL
MA9003 Base 0.4 Hot (125) Room Temp. Cold (-55)
3.8 3.7 3.6 3.5 3.4 3.3 -60 -40 -20 0 20 40 60
9003 Base VOL (V) 9007 Base BMS011 Base 80 100 120 140
0.3
0.2
0.1
0 0 Vdd = 5.5V 2 4 6 8 IOL (mA) 10 12 14 16
TEMPERATURE (deg C)
VOL Vs IOL
MA9007 Base 0.4 Hot (125) 0.3 VOL (V) Room Temp. Cold (-55) 0.3 VOL (V) 0.4
VOL Vs IOL
BMS011 Base Hot (125) Room Temp. Cold (-55) 0.2
0.2
0.1
0.1
0 0 Vdd = 5.5V 2 4 6 8 IOL (mA) 10 12 14 16
0 0 Vdd = 5.5V 2 4 6 8 IOL (mA) 10 12 14 16
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VOH Vs IOH
MA9003 Base 4.5 4.3 4.1 VOH (V) 3.9 3.7 3.5 3.3 0 Vdd = 4.5V 2 4 6 8 IOL (-mA) Vdd = 4.5V 10 12 14 16 Cold (-55) Room Temp. Hot (125) VOH (V) 4.5 4.3 4.1 3.9 3.7 3.5 3.3 0 2 4
VOH Vs IOH
MA9007 Base
Cold (-55) Room Temp. 6 8 IOL (-mA) 10 12 14 Hot 16 (125)
VOH Vs IOH
BMS011 Base 4.5 4.3 4.1 VOH (V) 3.9 3.7 3.5 3.3 0 Vdd = 4.5V 2 4 6 8 IOL (-mA) 10 12 14 16 Cold (-55) Room Temp. Hot (125)
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54 hsc 14 SCHMITT I/P HYSTERESIS

Cold at -55C i/p decreasing i/p increasing 6 5 Test at +25C i/p decreasing i/p increasing Hot at +125C i/p decreasing i/p increasing
O/P VOLTAGE
4 3 2 1 0 0 i/p pin 3 1 2 I/P VOLTAGE 3 4 5
54 hsc 14 SCHMITT I/P HYSTERESIS

Pre Rad i/p decreasing i/p increasing 6 5 Post Rad (100Krad) i/p decreasing i/p increasing
O/P VOLTAGE
4 3 2 1 0 0 i/p pin 9 1 2 I/P VOLTAGE 3 4 5
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TIMING DIAGRAMS
Figure 3: Set-Up Times, Hold Times, Removal Time and Propagation Delay Times
Figure 4: Three-State Propagation Delay Wave Shapes and Test Circuit
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RADIATION TOLERANCE
Total Dose (Function to specification)* Transient Upset (Stored data loss) Transient Upset (Survivability) Neutron Hardness (Function to specification) Single Event Upset** Latch Up 3x105 Rad(Si) 1x1011 Rad(Si)/sec >1x1012 Rad(Si)/sec >1x1015 n/cm2 <1x10-10 Errors/bit day Not possible
* Other total dose radiation levels available on request ** Worst case galactic cosmic ray upset - interplanetary/high altitude orbit Figure 5: Radiation Hardness Parameters
ORDERING INFORMATION
Unique Circuit Designator
Radiation Tolerance No tolerance implied Blank Radiation Hard Processing S 100 kRads (Si) Guaranteed R 300 kRads (Si) Guaranteed Q H 1000 kRads (Si) Guaranteed* * HSC Only
54xHSC139xxxxx 54xHST139xxxxx
QA/QCI Process (See Section 9 Part 4)
Test Process (See Section 9 Part 3)
Package Type C F L N Ceramic DIL (Solder Seal) Flatpack (Solder Seal) Leadless Chip Carrier Naked Die
Assembly Process (See Section 9 Part 2)
Reliability Level L C D E B S Rel 0 Rel 1 Rel 2 Rel 3/4/5/STACK Class B Class S
For details of reliability, QA/QC, test and assembly options, see Manufacturing Capability and Quality Assurance Standards Section 9.
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HEADQUARTERS OPERATIONS DYNEX SEMICONDUCTOR LTD Doddington Road, Lincoln. Lincolnshire. LN6 3LF. United Kingdom. Tel: +44-(0)1522-500500 Fax: +44-(0)1522-500550 CUSTOMER SERVICE Tel: +44 (0)1522 502753 / 502901. Fax: +44 (0)1522 500020 SALES OFFICE Tel: +44 (0)1522 500500. Fax: +44 (0)1522 502777
These offices are supported by Representatives and Distributors in many countries world-wide. Dynex Semiconductor 2002 TECHNICAL DOCUMENTATION NOT FOR RESALE. PRODUCED IN UNITED KINGDOM
Datasheet Annotations: Dynex Semiconductor annotate datasheets in the top right hard corner of the front page, to indicate product status. The annotations are as follows:Target Information: This is the most tentative form of information and represents a very preliminary specification. No actual design work on the product has been started. Preliminary Information: The product is in design and development. The datasheet represents the product as it is understood but details may change. Advance Information: The product design is complete and final characterisation for volume production is well in hand. No Annotation: The product parameters are fixed and the product is available to datasheet specification.
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior notice the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request. All brand names and product names used in this publication are trademarks, registered trademarks or trade names of their respective owners.
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54HSC/T Series

DC CHARACTERISTICS AND RATINGS

Figure 1: Absolute Maximum Ratings

Output Low Voltage

IIL IOL IDD

Input Leakage Current Output Leakage Current Quiescent Current

54HSC/T00 : Quadruple 2-Input Positive NAND Gates

Figure 2: Logic Diagram

H = high level, L = low level

Figure 1: Function Table

Figure 3: Pin Out

-55C / +125C Typ. 17 18 Max. 22 20 Units ns ns

Figure 4: Switching Characteristics

54HSC/T02 : Quadruple 2-Input Positive NOR Gates

Figure 2: Logic Diagram

H = high level, L = low level

Figure 1: Function Table

Figure 3: Pin Out

-55C / +125C Typ. 17 18 Max. 22 20 Units ns ns

Figure 4: Switching Characteristics

Figure 2: Logic Diagram

H = high level, L = low level

Figure 1: Function Table

54HSC/T04 : Hex Inverters

Outputs Y L H Figure 2: Logic Diagram

H = high level, L = low level

Figure 1: Function Table

Figure 3: Pin Out

-55C / +125C Typ. 17 18 Max. 22 20 Units ns ns

Figure 4: Switching Characteristics

54HSC/T08 : Quadruple 2-Input Positive AND Gates

Figure 2: Logic Diagram

H = high level, L = low level

Figure 1: Function Table

Figure 3: Pin Out

-55C / +125C Typ. 17 18 Max. 22 20 Units ns ns

Figure 4: Switching Characteristics

54HSC/T10 : Triple 3-Input Positive NAND Gates

Figure 2: Logic Diagram

H = high level, L = low level, X = irrelevant

Figure 1: Function Table

Figure 3: Pin Out

-55C / +125C Typ. 17 18 Max. 22 20 Units ns ns

Figure 4: Switching Characteristics

54HSC14 : Hex Schmitt-Trigger Inverters

Outputs Y H L Figure 2: Logic Diagram

H = high level, L = low level

Figure 1: Function Table

Figure 3: Pin Out

-55C / +125C Typ. 17 18 Max. 22 20 Units ns ns

Figure 4: Switching Characteristics

54HSC/T21 : Dual 4-Input Positive AND Gates

Figure 2: Logic Diagram

Figure 3: Pin Out

H = high level, L = low level

54HSC/T27 : Triple 3-Input Positive NOR Gates

Figure 2: Logic Diagram

H = high level, L = low level

Figure 1: Function Table Figure 3: Pin Out

-55C / +125C Typ. 17 18 Max. 22 20 Units ns ns

Figure 4: Switching Characteristics

54HSC/T32 : Quadruple 2-Input Positive OR Gates

Figure 2: Logic Diagram