APPLICATION NOTE--AN067 LDMOS Bias Temperature Compensation

Introduction
This paper is intended to provide useful guidance building a temperature compensating bias network for Sirenza LDMOS power modules and Sirenza packaged LDMOS transistors.

LDMOS Characteristics
The quiescent current (IDQ) of a Class AB LDMOS amplifier is primarily a function of gate to source voltage (VGS) and temperature. The IDQ changes proportionally with both VGS and temperature. This means that an amplifier that has been biased at room temperature to achieve required gain, gain flatness, efficiency, and linearity will be overbiased at high temperatures and underbiased at cold temperatures. See Figure 1 for the typical change in IDQ vs a change in temperature.
Typical LDMOS Amplifier Bias Change vs. Temperature with Constant Vgs
340 330 320 310 300 290 280 270 260 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature (Deg C)

IDQ (mA)

30W Amplifier IDQ

Figure 1. Amplifier IDQ as a Function of Baseplate Temperature

Amplifier gain and efficiency tend to degrade slightly at high temperatures, but it is possible to maintain consistent linearity over a temperature range by keeping IDQ constant in that range. Therefore a gate bias network that adjusts the VGS supplied to the transistor is required. See Figure 2 for a generalized block diagram of an LDMOS Class AB amplifier circuit.
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APPLICATION NOTE--AN067 LDMOS Bias Temperature Compensation

Charge Storage Network Bias Circuit

Input Matching Network

Output Matching Network

Figure 2. LDMOS Class AB Block Diagram Circuit

The VGS change applied to the amplifier to maintain constant IDQ varies linearly with temperature. See Figure 3 for a graph of VGS vs as a function of temperature with a constant IDQ.
LDMOS Amplifier Vgs for Constant Idq
3.65 3.6
Vgs (Vdc)

3.55 3.5 3.45 3.4 3.35 3.3 -20 -10 0 10 20 30 40 50 60 70 80 90

Temperature (Deg C)

Vgs Required to Maintain Idq=300mA

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Figure 3. VGS to Maintain Constant IDQ

Bias Circuit
Sirenza recommends the following application circuit for external temperature compensation of LDMOS power modules and discrete amplifiers made from packaged Sirenza LDMOS transistors. To ensure accurate temperature sampling the voltage regulator U1 should be located as close as physically possible to the transistor.

Figure 4. Sirenza Recommended Bias Circuit

This bias circuit uses the temperature characteristics of U1 to change the bias voltage over temperature. The voltage between pin 2 and pin 3 is held at 5Vdc and is constant over temperature. This sets up a constant current through R1 and R2. Because the LDMOS transistor has very high impedance all of the current through this leg flows through R3 and the parallel combination of R4/RT1. In addition to the current from pin2, pin 3 of U1 contributes a small current into R3/R4/RT1. The current from pin 3 varies with temperature and is used to change the bias voltage with a change in temperature. See the manufacturer's data sheet for specifics.

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Component
U1 R1 R2 R3 R4 R5 RT1 C1 C2 C3

Description
Voltage Regulator, 100mA, 5V, SOT-23 Resistor, 324 Ohm, 1%, 0603 Pot, 330 Ohm, 3mm Resistor, 187 Ohm, 1%, 0603 Resistor, 115 Ohm, 1%, 0603 Resistor, 10 Ohm, 1%, 0603 Thermistor 100K Ohm, 5%, 0603 Capacitor, 1uF, 10V, 10%, 0805 Capacitor, 1000pF, 50V, +80/-20%, 0805 Capacitor, 47pF, 200V, 5%, 0805

Manufacturer
National Semiconductor Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic ATC

Part Number
LM3480IM3-5.0TR ERJ-3EKF3240V EVM7-JSX30BY2 ERJ-3EKF1870V ERJ-3EKF1150V ERJ-3EKF0100V ERT-J1VV104J ECJ-2YB1A105K ECJ1VB1H102K 650F470JT200T

Figure 5. BoM for Recommended Bias Circuit

R1 is used to desensitize R2 and set the VGS range that can be set with R2. Lowering the value of R1 increases the range, but also increases the sensitivity of R2. The series combination of R3 and R3 set the slope of VGS vs temperature. Decreasing R3 or R4 decreases the circuit's change in VGS as a function of temperature. Changing the value of R3 or R4 will also cause a large change in the bias set point across all temperatures, so R1/R2 must be adjusted to compensate. RT1 can be ignored at temperatures below 70oC when analyzing this circuit. It is used to slightly modify the VGS at high temperature which allows the circuit to more closely track the required VGS. C1, C2, and C3 are used for charge storage and RF decoupling. R5 helps maintain amplifier stability across temperature. An Excel spreadsheet with a model of this bias circuit is included within this PDF. Double Click on the paper clip below this paragraph to open the Excel document. The spreadsheet contains macros, but has been thoroughly checked to ensure no viruses exist. The model has been verified to run on Excel 2000 or later. Opening attached documents requires Adobe Acrobat Reader 6.0 or later. Acrobat Reader can be freely downloaded from Adobe's website. AN-067 Excel Spreadsheet Model
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Summary
This document has presented an overview on several important items to consider during the implementation of temperature compensated LDMOS bias circuits. An example circuit has been presented and explained. It is important for the designer to remember that not all situations can be addressed, and that each implementation may have specific challenges associated with it. For assistance with issues not addressed in this document contact Sirenza applications support at ipp-apps@sirenza.com.

References
National Semiconductor LM3480 Data Sheet Panasonic Multilayer Chip NTC Thermistors Data Sheet Adobe Systems Inc website: http://www.adobe.com

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