Section 1

memory map

Test block for 913x Verication guide

The testbench uses direct testing.

Internal sky blue regs:

Address 0x00 0x04 0x08 0x0c 0x10 0x14 0x18 0x1c 0x20 0x24 0x28 0x2c 0x30 0x34

Use Chip ID Fuse value 31:0 Chip ID Fuse value 63:32 Chip ID Fuse value 95:64 Chip ID Fuse value 127:96 BIST done platform BIST invoke CORE MBIST invoke register platform Titanium BIST cong ZBIST conguration register (BSTCFG) MBIST done register core MBIST Fail register - core Test Reset Cong. Word Low Register (TRCWHR) Test Reset Cong. Word High Register (TRCWLR)

Access R only R only R/W R/W R only W W R R/W R only R only R only R/W R/W --R/W W only R/W R only R/W R/W R only R only R only

0x38 0x3c domain select 0x40 SkyBlue UNLOCK Register (ULCKSB) 0x44 Platform Features Registers (PLATF) 0x48 BIST Bitmap Data Out 1 Register (MTBDO_1) 0x4C BIST Bitmap Data Out 2 Register (MTBDO_2) 0x50 BIST Bitmap Data Out 3 Register r (MTBDO_3) 0x54 0x58 0x5C Fuse location 0x60 MBIST Fail register - platform 0x64 0x68 Fuse enable locations 0x6c Reserved 0x70 Chip ID Fuse value 159:128 0x74 Chip ID Fuse value 191:160 0x78 Chip ID Fuse value 223:192 0x7C Chip ID Fuse value 255:224 0x80 - 0xff Reserved

R only R only ----

clocking. ipg_clk clock generated by the IP Green Initiator. ipt_tck - at least 4x slower than ipg_clk due to BIST clocking

ipp_ind_clockin - generated by the IP Green Initiator reset. trst_b from pin. For most logic poreset_b for bist erase logic Drivers, Monitors and Checkers

1.1

JTAG_STUB Description

1.1.1 jtagstub Functional Overview

The jtagstub gets jtag_data or jtag_command commands and translates these to JTAG interface signalling.

1.1.2 jtagstub Commands

Table 1-1 jtagstub Commands Command jtag_data jtag_command trst_assertion reset2idle Description Read or write data of {size} bits. Return shifted out TDO value command write jtag command. Size is always 8 bits. none asserst trst,wait 5 tck cycles, and then release trst navigate from reset to idle jtag_data and jtag_command all start and return to idle state, so we need a little push to get there from reset. Arguments size, data, return data

Jtag monitor

JTAG monitor tracks JTAG operation and reporst the values scanned in and out, it also translates the commands. 1.2 IO and Pads

JTAG I/F - tck,tdi,tdo,trst_b,tms. Section 2 Level Partition Outline These are the levels of verication: Level 0: Basic read/write operations, I/F check, reset. R/W all SB space registers via JTAG port.

Level 1: Level 0, plus R/W from SB side of all posible registers. Check combinatorical Decoding of test modes. Check LSRL mode. Level 2: None. Chip level tests

2.0.1 Test Outline Descriptions

Remarks ; Tests are for For chip level MJTAG/JTV is a fully automated testbench, to be run by I/O team. Table 2-2 feature and test list No Feature EXTEST SAMPLE PRELOAD CLAMP HIGHZ IDCODE BYPASS STATUS Clocking Control FREEZE USE_TCK TOF_USE_TCK TLM Instructions TLM_SELECT JTG2SB Instructions SB_ADDR SB_DATA_READ SB_DATA_READ_AI SB_DATA_WRITE SB_DATA_WRITE_AI BIST Instructions ACCESS_BIST ACCESS_FUSE MBIST_RA OCE Instructions ENABLE_ONCE DEBUG_REQUEST CHOOSE_ONCE READ_STATUS BIST bitmap mux test name MJTAG MJTAG MJTAG MJTAG MJTAG MJTAG MJTAG scenario Drive / sample all pins Sample all pins Drive values to all pins Hold BSR shifted value on pins Drive highz on all pins Read IDCODE of pacsun Check cell is 1 bit long Read platform status (currently all 0s) Scan in freeze signal, check clocks are stopped In LSRL mode, check TCK shifts long chain In LSRL mode, check control is returned to ipg_clk Select CE TAP part of CE BIST verication Scan SB regs Read all readable SB regs Read consecutive pair or more Write all writeable SB regs Write consecutive pair or more

Scan in alternate alg to BIST ACRs on all BIST machines Write/read all possible fuses Run BIST on memory with defects Read BIST solution and scan back into fuses Check chosen cores registers can be accessed via jtag data register shift Check cores receive debug request Check any and all cores can be chosen Read core status For all BISTS that have parallel output, select that BIST,activate parallel bitmap mode, check parallel IO Check that for status out mode done/fail bits can be seen on IO

DC-scan AC-scan Reserved JTAG instructions BURN-IN: all BISTS are on in loop mode write/read fuses Memory Erase mode

Combinatorically selectable modes set test mode select pins, check that ipt_clk reaches blocks directly set test mode select pins, check that PLL is working, dividers can be set to correct ratio, ---check nothing happens Set the mode select pins Check all BISTS are running Check Efuse can be programmed Check erase is done corectly in all cases : secure/non secure, 4/6 cores, not blocked by trst

OCE activation from JTAG ow OCE (On chip emulator) is the DSP debugger. In verifcation enviroment DSP debugger can be accessed in from JTAG port by using these utilities: 1) $td/neon/miscellaneous/bin/gen_stim_for_oce.pl : reads an instruction le (*.ins) and compiles it into a stimulus le (*.stim) 2) oce_driver $td/neon/testbench/tasks_v/pacsun_oce_driver_basic_task.v This task reads the .stim le dynamically in runtime and calls tasks in the jtagstub to execute them. When .stim le is generated, it consists of lines of 280 bit wide data . opcode = stims[279:272]; data_size = stims[271:256]; data = stims[255:0]; Commands available in oce_driver:

Table 1: Stim opcodes Stim Opcode 8'h14 8'h15 8'h16 8'h17 8'h50 8'h51 JTAG Data if((data[23:16]==8'ha3) decoding then data[5:0] select core for rd_status

JTAG Command if((data[23:16]==8'ha3) then data[5:0] select core for rd_status CORE Command CORE Data wait_ee0_assert; end wait_ee1_assert; end

Table 1: Stim opcodes Stim Opcode 8'h52 8'h53 8'h54 8'h55 8'h57 8'ha0 8'ha1 8'ha2 8'ha3 8'ha4 8'ha5 8'hb0 8'hb1 8'hb2 8'hb3 8'hb4 8'hb5 8'hc0 8'hc1 8'hc2 8'hc3 8'hc4 8'hc5 8'hd0 8'hd1 8'hd2 8'hd3 assert_ee0 wait_ee0_negate; end wait_ee1_negate; end negate_ee0 wait_all_in_debug_mode wait_debug_mode_0 wait_debug_mode_1 wait_debug_mode_2 wait_debug_mode_3 wait_debug_mode_4 wait_debug_mode_5 wait_stop_mode_0 wait_stop_mode_1 wait_stop_mode_2 wait_stop_mode_3 wait_stop_mode_4 wait_stop_mode_5 wait_wait_mode_0 wait_wait_mode_1 wait_wait_mode_2 wait_wait_mode_3 wait_wait_mode_4 wait_wait_mode_5 wait_hreset hreset tpr_read32_compare( 32'hc007_0000,32'h11223344,32'hffffffff) tpr_read32_compare( 32'hc007_0010,32'h55667788 , 32'hffffffff) decoding

Table 1: Stim opcodes Stim Opcode 8'he0 8'he1 8'he2 8'he3 8'he4 8'he5 8'he6 8'he7 8'hff MY_DEBUG_0 MY_DEBUG_1 MY_DEBUG_2 MY_DEBUG_3 RESET_2_IDLE TRST_ASSERTION STAY_IDLE RESET finish_test = 1 decoding

OCE testcases OCE (On chip emulator) is the DSP debugger. In verifcation enviroment DSP debugger can be accessed in 2 methods: 1) By using a special setup of commands in an instruction le (*.ins) that are precompiled into a stimulus le (*.stim) and are read by the oce_driver. 2) In case of a short test the instructions can be mapped manually to jtag command, jtag_data type transactions. Commands available in oce_driver: Example #1: This test writes to Eonce transmit register within core address space (addresses 0x7ff7_ff10 and 0x7ff7_ff14 )and reads back through jtag interface. Instruction le: WR:GO:CORE_CMD:{move.l #$007ff7ff10,r11} WR:GO:CORE_CMD:{move.l #$900d900d,d11} WR:GO:CORE_CMD:{move.l d11,(r11)} WR:GO:CORE_CMD:{move.l #$007ff7ff14,r11}

WR:GO:CORE_CMD:{move.l #$900d900d,d11} WR:GO:CORE_CMD:{move.l d11,(r11)} RD:ETRSMT CMPR_TDO_2LONG Note assenbler commands are represented as opcodes 16100000000000000000000000000000017e Core command 173000000000000000000000dc081451c002 Core Data move.l #$007ff7ff10,r11 16100000000000000000000000000000017e 173000000000000000000000b00ac0309ccb 16100000000000000000000000000000017e 1730000000000000000000000000000c9c2d 16100000000000000000000000000000017e 173000000000000000000000dc281451c002 16100000000000000000000000000000017e 173000000000000000000000b00ac0309ccb 16100000000000000000000000000000017e 1730000000000000000000000000000c9c2d 161000000000000000000000000000000204 174000000000000000000000000000000000 c30000000000000000000000000000000000