Companion Website

Companion Website of the book DIGITAL ELECTRONICS: PRINCIPLES, DEVICES AND APPLICATIONS
-------------------------------------------------------------------------------------------------------------------Digital Electronics: Principles, Devices and Applications Anil K.Maini 2007 John Wiley & Sons, Ltd
Companion website of the book Digital Electronics: Principles, Devices and Applications
Application Relevant Information on DIGITAL INTEGRATED CIRCUITS

The companion website contains application relevant information on different categories of digital integrated circuits discussed in detail in the text. The information is presented under the following headings. 1. Numerical index of digital integrated circuits of TTL family 2. Functional index of digital integrated circuits of TTL family 3. Numerical index of digital integrated circuits of CMOS logic family 4. Functional index of digital integrated circuits of CMOS logic family 5. Numerical index of digital integrated circuits of ECL family 6. Functional index of digital integrated circuits of ECL family 7. Popular A/D converters 8. Popular D/A converters 9. Popular microprocessors 10. Popular microcontrollers 11. Pin connection diagrams and other relevant application information on logic gates and related devices 12. Pin connection diagrams and other relevant application information on multiplexers and de-multiplexers 13. Pin connection diagrams and other relevant application information on digital ICs for arithmetic operations 14. Pin connection diagrams and other relevant application information on flip flops and related devices 15. Pin connection diagrams and other relevant application information on counters 16. Pin connection diagrams and other relevant application information on shift registers 17. Pin connection diagrams and other relevant application information on microprocessors and peripheral devices 18. Pin connection diagrams and other relevant application information on microcontrollers
1. Numerical index of digital integrated circuits of TTL family

Table C.1 lists the numerical index of the digital integrated circuits belonging to the TTL family. The devices covered include logic gates and related devices, arithmetic circuits, multiplexers, de-multiplexers, encoders and decoders, flip flops and counters and registers. (TTL family is discussed in detail in chapter-5, logic gates in chapter-4, arithmetic circuits in chapter-7, multiplexers, demultiplexers, encoders and decoders in chapter 8, flip flops in chapter 10 and counters and registers in chapter-11 of the book). Table C.1
Numerical index of Digital Integrated Circuits Type No. 7400 7401 7402 7403 7404 7405 7408 7409 7410 74107 74109 7411 74112 74113 74114 7412 74121 74122 74123 74125 74126 7413 74132 74133 74136 74138 74139 7414 74145 74147 Function Quad 2-input NAND gate Quad 2-input NAND gate (open collector) Quad 2-input NOR gate Quad 2-input NAND gate (open collector) Hex Inverter Hex Inverter (open collector) Quad 2-input AND gate Quad 2-input AND gate (open collector) Triple 3-input NAND gate Dual JK Flip Flop with CLEAR Dual JK Positive Edge Triggered Flip Flop with PRESET and CLEAR Triple 3-input AND gate Dual JK Negative Edge Triggered Flip Flop with PRESET and CLEAR Dual JK Negative Edge Triggered Flip Flop with PRESET Dual JK Negative Edge Triggered Flip Flop with PRESET and CLEAR Triple 3-input NAND gate (open collector) Monostable Multivibrator Retriggerable Monostable Multivibrator Dual Retriggerable Monostable Multivibrator Quad tristate Non-inverting buffer (LOW Enable) Quad tristate Non-inverting buffer (HIGH Enable) Dual 4-input Schmitt NAND gate Quad 2-input Schmitt trigger NAND gate 13-input NAND gate Quad 2-input EX-OR gate (open collector) 1-of-8 decoder/demultiplexer Dual 1-of-4 decoder/demultiplexer Hex Schmitt trigger Inverter 1-of-10 decoder/driver (open collector) 10-line-to 4-line priority encoder
Table C.1 (contd.) Type No.

74148 74150 74151 74152 74153 74154 74155 74156 74157 74158 74160 74161 74162 74163 74164 74165 74166 74174 74175 74178 7418 74181 74182 74183 7419 74190 74191 74192 74193 74194 74198 74199 7420 7421 7422 16-input Multiplexer 8-input multiplexer 8-input multiplexer Dual 4-input multiplexer 4-of-16 decoder/demultiplexer Dual 1-of-4 decoder/demultiplexer Dual 1-of-4 decoder/demultiplexer (open collector) Quad 2-input non-inverting multiplexer Quad 2-input inverting multiplexer BCD Decade Counter with Asynchronous CLEAR 4-Bit Binary Counter with Asynchronous CLEAR BCD Decade Counter with Synchronous CLEAR 4-Bit Binary Counter with Synchronous CLEAR 8-bit Shift Register (Serial-in/Parallel-out) 8-bit shift register (Parallel-in/Serial-out) 8-bit Shift Register (Parallel-in/Serial-out) Hex D-type Flip Flop with CLEAR Quad Edgr Triggered D-type Flip Flop with CLEAR 4-bit Parallel Access Shift Register Dual 4-input NAND gate 4-Bit ALU and Function Generator Look Ahead Carry Generator Dual Carry Save Full Adder Hex Schmitt trigger inverter Presettable BCD-Decade UP/DOWN Counter Presettable 4-Bit Binary UP/DOWN Counter Presettable BCD-Decade UP/DOWN Counter Presettable 4-Bit Binary UP/DOWN Counter 4-bit Right/Left Universal Shift Register 8-bit universal shift register (Parallel-in/Parallel-out Bidirectional) 8-bit universal bidirectional) shift register (Parallel-in/Parallel-out
Function
8-line-to 3-line priority encoder
Dual 4-input NAND gate Dual 4-input AND gate Dual 4-input NAND gate (open collector)

74221 74240 74241 74242 74243 74244 74245 74247 74248 74251 74253 74256 74256 74257 74258 74259 74259 74266 7427 74273 74279 74283 74290 74293 74298 7430 7432 74348 74353 74365 74366 74367 74368 74373 74374
Function
Dual Monostable Multivibrator Octal tristate Inverting Bus/Line driver Octal tristate Bus/Line driver Quad tristate Inverting Bus Transceiver Quad tristate Non-inverting Bus Transceiver Quad tristate Non-inverting Driver Quad tristate Non-inverting Bus Transceiver BCD-to-7 segment decoder/driver (open collector) BCD-to-7 segment decoder/driver with Pull-ups 8-input 3-state multiplexer Dual 4-input 3-state multiplexer Dual 4-bit addressable latch Dual 4-bit Addressable Latch Quad 2-input 3-state non-inverting multiplexer Quad 2-input 3-state inverting multiplexer 8-bit addressable latch 8-bit Addressable Latch Quad 2-input Exclusive-NOR gate (open collector) Triple 3-input NOR gate Octal D-type Flip Flop with Master RESET Quad SET/RESET Latch 4-Bit Full Binary Adder Decade Counter 4-Bit Binary Counter Dual 2-input multiplexer with output latches 8-input NAND gate Quad 2-input OR gate 8-line-to 3-line priority encoder (3-state) Dual 4-input multiplexer Hex tristate Non-inverting Buffer with Common Enable Hex tristate Inverting Buffer with Common Enable Hex tristate Non-inverting Buffer Hex tristate Inverting buffer Octal Transparent Latch (3-state) Octal D-type Flip flop (3-state)

74377 74378 74379 74386 74390 74393 74398 74399 7442 74465 7451 74533 74534 7454 74540 74541 7455 74573 74574 74640 74641 74645 7473 7474 7475 7476 7478 7483 7485 7486 74885 7490 7491 7493
Function
Octal D-type Flip Flop with common ENABLE Hex D-type Flip Flop with ENABLE 4-Bit D-type Flip Flop with ENABLE Quad 2-input EX-OR gate Dual Decade Counter Dual 4-Bit Binary Counter Quad 2-input multiplexer with output register Quad 2-input multiplexer with output register 1-of-10 decoder Octal tristate Non-inverting Buffer Dual 2-wide 2-input 3-input AND-OR-INVERT gate Octal Transparent Latch (3-state) Octal D-type Flip Flop (3-state) 4-wide AND-OR-INVERT gate Octal tristate Inverting Buffer/Line Driver Octal tristate Non-inverting Buffer/Line Driver 2-wide 4-input AND-OR-INVERT gate Octal D-type Latch (3-state) Octal D-type Flip Flop (3-state) Octal tristate Inverting Bus Transceiver Octal tristate Non-inverting Bus Transceiver (Open collector) Octal tristate Non-inverting Bus Transceiver Dual JK Negative Edge Triggered Flip flop with CLEAR Dual D-type Positive Edge Triggered Flip Flop with PRESET and CLEAR 4-Bit D-type Latch Dual JK flip flop with PRESET and CLEAR Dual JK flip flop with PRESET and CLEAR 4-Bit Full Adder 4-Bit Magnitude Comparator Quad 2-input EX-OR gate 8-bit Magnitude Comparator Decade Counter 8-bit Shift Register (Serial-in/Serial-out) 4-bit Binary Counter
2. Functional index of digital integrated circuits of TTL family

Tables C.2 to C.6 list the functional indices of the digital integrated circuits of the TTL family for logic gates and related devices, arithmetic circuits, multiplexers and de-multiplexers, flip flops, counters and registers respectively. (TTL family is discussed in detail in chapter-5, logic gates in chapter-4, arithmetic circuits in chapter-7, multiplexers, demultiplexers, encoders and decoders in chapter 8, flip flops in chapter 10 and counters and registers in chapter-11 of the book). Table C.2 Logic Gates belonging to the TTL Family Type Number
7400 7401 7402 7403 7404 7405 7408 7409 7410 7411 7412 7413 7414 7418 7419 7420 7421 7422 7427 7430 7432 7451 7454 7455 7486 74125 74126 74132
Function
Quad 2-input NAND gate Quad 2-input NAND gate (open collector) Quad 2-input NOR gate Quad 2-input NAND gate (open collector) Hex Inverter Hex Inverter (open collector) Quad 2-input AND gate Quad 2-input AND gate (open collector) Triple 3-input NAND gate Triple 3-input AND gate Triple 3-input NAND gate (open collector) Dual 4-input Schmitt NAND gate Hex Schmitt trigger Inverter Dual 4-input NAND gate Hex Schmitt trigger inverter Dual 4-input NAND gate Dual 4-input AND gate Dual 4-input NAND gate (open collector) Triple 3-input NOR gate 8-input NAND gate Quad 2-input OR gate Dual 2-wide 2-input 3-input AND-OR-INVERT gate 4-wide AND-OR-INVERT gate 2-wide 4-input AND-OR-INVERT gate Quad 2-input EX-OR gate Quad tristate Non-inverting buffer (LOW Enable) Quad tristate Non-inverting buffer (HIGH Enable) Quad 2-input Schmitt trigger NAND gate
Table C.2 (contd.) Type Number

74133 74136 74240 74241 74242 74243 74244 74245 74266 74365 74366 74367 74368 74386 74465 74540 74541 74640 74641 74645 13-input NAND gate Quad 2-input EX-OR gate (open collector) Octal tristate Inverting Bus/Line driver Octal tristate Bus/Line driver Quad tristate Inverting Bus Transceiver Quad tristate Non-inverting Bus Transceiver Quad tristate Non-inverting Driver Quad tristate Non-inverting Bus Transceiver Quad 2-input Exclusive-NOR gate (open collector) Hex tristate Non-inverting Buffer with Common Enable Hex tristate Inverting Buffer with Common Enable Hex tristate Non-inverting Buffer Hex tristate Inverting buffer Quad 2-input EX-OR gate Octal tristate Non-inverting Buffer Octal tristate Inverting Buffer/Line Driver Octal tristate Non-inverting Buffer/Line Driver Octal tristate Inverting Bus Transceiver Octal tristate Non-inverting Bus Transceiver (Open collector) Octal tristate Non-inverting Bus Transceiver
Function
Table C.3 Arithmetic Circuits belonging to TTL family
Type Number
7483 7485 74181 74182 74183 74283 74885 4-Bit Full Adder
Function
4-Bit Magnitude Comparator 4-Bit ALU and Function Generator Look Ahead Carry Generator Dual Carry Save Full Adder 4-Bit Full Binary Adder 8-bit Magnitude Comparator
Table C.4 Multiplexers and Demultiplexer Circuits belonging to TTL family Type Number
7442 74138 74139 74145 74147 74148 74150 74151 74152 74153 74154 74155 74156 74157 74158 74247 74248 74251 74253 74256 74257 74258 74259 74298 74348 74353 74398 74399 1-of-10 decoder 1-of-8 decoder/demultiplexer Dual 1-of-4 decoder/demultiplexer 1-of-10 decoder/driver (open collector) 10-line-to 4-line priority encoder 8-line-to 3-line priority encoder 16-input Multiplexer 8-input multiplexer 8-input multiplexer Dual 4-input multiplexer 4-of-16 decoder/demultiplexer Dual 1-of-4 decoder/demultiplexer Dual 1-of-4 decoder/demultiplexer (open collector) Quad 2-input non-inverting multiplexer Quad 2-input inverting multiplexer BCD-to-7 segment decoder/driver (open collector) BCD-to-7 segment decoder/driver with Pull-ups 8-input 3-state multiplexer Dual 4-input 3-state multiplexer Dual 4-bit addressable latch Quad 2-input non-inverting 3-state multiplexer Quad 2-input 3-state inverting multiplexer 8-bit addressable latch Dual 2-input multiplexer with output latches 8-line-to 3-line priority encoder (3-state) Dual 4-input multiplexer Quad 2-input multiplexer with output register Quad 2-input multiplexer with output register
Function
Table C.5 Flip flops belonging to the TTL family Type Number
7473 7474 7475 7476 7478 74107 74109 74112 74113 74114 74121 74122 74123 74174 74175 74221 74256 74259 74273 74279 74373 74374 74377 74378 74379 74533 74534 74573 74574
Function
Dual JK Negative Edge Triggered Flip flop with CLEAR Dual D-type Positive Edge Triggered Flip Flop with PRESET and CLEAR 4-Bit D-type Latch Dual JK flip flop with PRESET and CLEAR Dual JK flip flop with PRESET and CLEAR Dual JK Flip Flop with CLEAR Dual JK Positive Edge Triggered Flip Flop with PRESET and CLEAR Dual JK Negative Edge Triggered Flip Flop with PRESET and CLEAR Dual JK Negative Edge Triggered Flip Flop with PRESET Dual JK Negative Edge Triggered Flip Flop with PRESET and CLEAR Monostable Multivibrator Retriggerable Monostable Multivibrator Dual Retriggerable Monostable Multivibrator Hex D-type Flip Flop with CLEAR Quad Edgr Triggered D-type Flip Flop with CLEAR Dual Monostable Multivibrator Dual 4-bit Addressable Latch 8-bit Addressable Latch Octal D-type Flip Flop with Master RESET Quad SET/RESET Latch Octal Transparent Latch (3-state) Octal D-type Flip flop (3-state) Octal D-type Flip Flop with common ENABLE Hex D-type Flip Flop with ENABLE 4-Bit D-type Flip Flop with ENABLE Octal Transparent Latch (3-state) Octal D-type Flip Flop (3-state) Octal D-type Latch (3-state) Octal D-type Flip Flop (3-state)
10
Table C.6 Counters and Registers belonging to TTL family Type Number
7490 7491 7493 74160 74161 74162 74163 74164 74165 74166 74178 74190 74191 74192 74193 74194 74198 74199 74290 74293 74390 74393 Decade Counter 8-bit Shift Register (Serial-in/Serial-out) 4-bit Binary Counter BCD Decade Counter with Asynchronous CLEAR 4-Bit Binary Counter with Asynchronous CLEAR BCD Decade Counter with Synchronous CLEAR 4-Bit Binary Counter with Synchronous CLEAR 8-bit Shift Register (Serial-in/Parallel-out) 8-bit shift register (Parallel-in/Serial-out) 8-bit Shift Register (Parallel-in/Serial-out) 4-bit Parallel Access Shift Register Presettable BCD-Decade UP/DOWN Counter Presettable 4-Bit Binary UP/DOWN Counter Presettable BCD-Decade UP/DOWN Counter Presettable 4-Bit Binary UP/DOWN Counter 4-bit Right/Left Universal Shift Register 8-bit universal shift register (Parallel-in/Parallel-out Bidirectional) 8-bit universal Bidirectional) Decade Counter 4-Bit Binary Counter Dual Decade Counter Dual 4-Bit Binary Counter shift register (Parallel-in/Parallel-out
Function
11
3. Numerical index of digital integrated circuits of CMOS logic family

Table C.7 lists the numerical index of the digital integrated circuits of the CMOS family. The devices covered include logic gates and related devices, arithmetic circuits, multiplexers, demultiplexers, encoders and decoders, flip flops and counters and registers. (CMOS family is discussed in detail in chapter-5, logic gates in chapter-4, arithmetic circuits in chapter-7, multiplexers, demultiplexers, encoders and decoders in chapter 8, flip flops in chapter 10 and counters and registers in chapter-11 of the book). Table C.7 Numerical index of Digital Integrated Circuits of the CMOS logic family Type Number
4001B 4002B 4008 40097B 40098B 4011B 4012B 4013 4014 B 40147 4015 B 40160 B 40161 B 40162 B 40163 B 4017 B 40174 40175 40181 40182 4019 40192B 40193 B 4021 B 4023B 4025B 4027 4028 4029 B Quad 2-input NOR gate Dual 4-input NOR gate 4-Bit Binary Full Adder Tristate Hex Non-inverting Buffer Tristate Inverting Buffer Quad 2-input NAND gate Dual 4-input NAND gate Dual D-type Flip Flop 8-Bit Static Shift Register (Synchronous Parallel or Serial-in/Serial-out) 10-line to 4-line BCD priority encoder Dual 4-bit Static Shift Register (Serial-in/Parallel-out) Decade Counter with Asynchronous Clear Binary Counter with Asynchronous Clear Decade Counter Binary Counter 5-stage Johnson Counter Hex D-type Flip Flop Quad D-type Flip Flop 4-Bit Arithmetic Logic Unit Look Ahead Carry Generator Quad 2-input multiplexer Presettable BCD UP/DOWN Counter Presettable Binary UP/DOWN Counter 8-bit Static Shift Register (Asynchronous Parallelin or Synchronous Serial-in/Serial-out) Triple3-input NAND gate Triple 3-input NOR gate Dual JK Flip Flop 1-of-10 decoder Synchronous Presettable 4-bit UP/DOWN Counter
Function
12
Table C.7 (Contd.)
Type Number
4030B 4035 B 4042 4044 4047 4049B 4050B 4069UB 4070B 4071B 4076 4081B 4086B 4093B 4510 B 4511 4511 4512 4514 4515 4518 B 4520B 4522 B 4527 4528 4532 4539 4543 4543 4555 4556 4585 4722 B 4723 4723 4724 4724 4731 B
Function
Quad 2-input EX-OR gate 4-bit Universal Shift Register Quad D-type Latch Quad R/S Latch with 3-state output Low Power Monostable/Astable Multivibrator Hex Inverting Buffer Hex Non-inverting Buffer Hex Inverter Quad 2-input EX-OR gate Quad 2-input OR gate Quad D-type Flip Flop with 3-state output Quad 2-input AND gate 4-wide 2-input AND-OR-INVERT gate Quad 2-input Schmitt NAND Presettable UP/DOWN BCD Counter BCD to 7-segment latch/decoder/driver BCD-to-7 segment Latch/Decoder/Driver 8-input 3-state multiplexer 1-of-16 decoder/demultiplexer with input latch 1-of-16 decoder/demultiplexer with input latch Dual 4-bit Decade Counter Dual 4-bit binary counter 4-bit BCD Programmable divide-by-N counter BCD Rate Multiplier Dual Retriggerable Resettable Monostable Multivibrator 8-line to 3-line priority encoder Dual 4-input multiplexer BCD to 7-segmnt latch/decoder/driver for LCD displays BCD-to-7 segment Latch/Decoder/Driver for LCD Dual 1-of-4 decoder/demultiplexers Dual 1-of-4 decoder/demultiplexers 4-Bit Magnitude Comparator Programmable Counter/Timer Dual 4-bit addressable latch Dual 4-bit Addressable Latch 8-bit addressable latch 8-bit Addressable Latch Quad 64-bit Static Shift Register
13
4. Functional index of digital integrated circuits of CMOS logic family

Table C.8 to Table C.12 list the functional indices of the digital integrated circuits of the CMOS family for Logic gates and related devices, arithmetic circuits, multiplexers and demultiplexers, Flip Flops and Counters and Registers respectively. (CMOS family is discussed in detail in chapter-5, logic gates in chapter-4, arithmetic circuits in chapter-7, multiplexers, demultiplexers, encoders and decoders in chapter 8, flip flops in chapter 10 and counters and registers in chapter-11 of the book) Table C.8 Logic Gates belonging to CMOS family Type Number
4001B 4002B 4011B 4012B 4023B 4025B 4030B 4049B 4050B 40097B 40098B 4069UB 4070B 4071B 4081B 4086B 4093B Quad 2-input NOR gate Dual 4-input NOR gate Quad 2-input NAND gate Dual 4-input NAND gate Triple3-input NAND gate Triple 3-input NOR gate Quad 2-input EX-OR gate Hex Inverting Buffer Hex Non-inverting Buffer Tristate Hex Non-inverting Buffer Tristate Inverting Buffer Hex Inverter Quad 2-input EX-OR gate Quad 2-input OR gate Quad 2-input AND gate 4-wide 2-input AND-OR-INVERT gate Quad 2-input Schmitt NAND
Function
14
Table C.9 Arithmetic circuits belonging to CMOS family
Type Number
4008 4527 4585 40181 40182 4-Bit Binary Full Adder BCD Rate Multiplier
Function
4-Bit Magnitude Comparator 4-Bit Arithmetic Logic Unit Look Ahead Carry Generator
15
Table C.10 Multiplexer and Demultiplexer Circuits belonging to CMOS family
Type Number
4019 4028 40147 4511 4512 4514 4515 4532 4539 4543 4555 4556 4723 4724
Function
Quad 2-input multiplexer 1-of-10 decoder 10-line to 4-line BCD priority encoder BCD to 7-segment latch/decoder/driver 8-input 3-state multiplexer 1-of-16 decoder/demultiplexer with input latch 1-of-16 decoder/demultiplexer with input latch 8-line to 3-line priority encoder Dual 4-input multiplexer BCD to 7-segmnt latch/decoder/driver for LCD displays Dual 1-of-4 decoder/demultiplexers Dual 1-of-4 decoder/demultiplexers Dual 4-bit addressable latch 8-bit addressable latch
16
Table C.11 Flip Flops belonging to CMOS family
Type Number
4013 4027 4042 4044 4047 4076 40174 40175 4511 4528 4543 4723 4724
Function
Dual D-type Flip Flop Dual JK Flip Flop Quad D-type Latch Quad R/S Latch with 3-state output Low Power Monostable/Astable Multivibrator Quad D-type Flip Flop with 3-state output Hex D-type Flip Flop Quad D-type Flip Flop BCD-to-7 segment Latch/Decoder/Driver Dual Retriggerable Resettable Monostable Multivibrator BCD-to-7 segment Latch/Decoder/Driver for LCD Dual 4-bit Addressable Latch 8-bit Addressable Latch
17
Table C.12 Counters and Registers belonging to the CMOS family
Type Number 4014 B 4015 B 4017 B 4021 B 4029 B 4035 B 40160 B 40161 B 40162 B 40163 B 40192B 40193 B 4510 B 4518 B 4520B 4522 B 4722 B 4731 B
Function 8-Bit Static Shift Register (Synchronous Parallel or Serial-in/Serial-out) Dual 4-bit Static Shift Register (Serial-in/Parallel-out) 5-stage Johnson Counter 8-bit Static Shift Register (Asynchronous Parallel-in or Synchronous Serial-in/Serial-out) Synchronous Presettable 4-bit UP/DOWN Counter 4-bit Universal Shift Register Decade Counter with Asynchronous Clear Binary Counter with Asynchronous Clear Decade Counter Binary Counter Presettable BCD UP/DOWN Counter Presettable Binary UP/DOWN Counter Presettable UP/DOWN BCD Counter Dual 4-bit Decade Counter Dual 4-bit binary counter 4-bit BCD Programmable divide-by-N counter Programmable Counter/Timer Quad 64-bit Static Shift Register
18
5. Numerical index of digital integrated circuits of ECL family

Table C.13 lists the numerical index of the digital integrated circuits of the ECL family. The devices covered include logic gates and related devices, arithmetic circuits, multiplexers, demultiplexers, encoders and decoders, flip flops and counters and registers. (ECL family is discussed in detail in chapter-5, logic gates in chapter-4, arithmetic circuits in chapter-7, multiplexers, demultiplexers, encoders and decoders in chapter 8, flip flops in chapter 10 and counters and registers in chapter-11 of the book).
Table C.13 Numerical Index of Digital Integrated circuits of ECL family Type Number
10100 10101 10102 10103 10104 10113 10114 10115 10116 10117 10118 10123 10128 10129 10130 10131 10132 10133 10134 10135 10136 10137 10141 10153 10154 10158 10159 10161
Function
Quad 2-input NOR gate with strobe Quad 2-input OR/NOR gate Quad 2-input NOR gate Quad 2-input OR gate Quad 2-input AND gate Quad 2-inpu EX-OR gate Triple Line Receiver Quad Line Receiver Triple Line Receiver Dual 2-wide 2-3 input OR-AND/OR-AND-INVERT gate Dual 2-wide 3-input OR-AND gate Triple 4-3-3 Input Bus Driver Dual Bus Driver Quad Bus Driver Quad D-type Latch Dual D-type Master/Slave Flip Flop Dual 2-input multiplexer with latch and common reset Quad D-type Latch (Negative transition) Dual multiplexer with latch Dual JK Master/Slave Flip Flop Universal Hexadecimal Counter Universal Decade Counter 4-Bit Universal Shift Register Quad Latch (Positive transition) Binary Counter (4-bit) Quad 2-input multiplexer (non-inverting) Quad 2-input multiplexer (inverting) 3-to-8 line decoder (LOW)
19
Table C.13 (contd.)
10162 10164 10165 10168 10171 10172 10173 10174 10175 10176 10178 10179 10180 10181 10182 10183 10188 10192 10194 10195 10198 10231 1658 1666 1668 1670
3-to-8 line decoder (HIGH) 8-line multiplexer 8-input priority encoder Quad D-type Latch Dual 2-to-4 line decoder (LOW) Dual 2-to-4 line decoder (HIGH) Quad 2-input multiplexer/latch Dual 4-to-1 multiplexer Quint Latch Hex D-type Master/Slave Flip Flop 4-bit binary counter Look Ahead Carry Block Dual High Speed 2-Bit Adder/Subtractor 4-Bit Arithmetic Logic Unit/Function Generator 4-Bit Arithmetic Logic Unit/Function Generator 42 Multiplier Hex Buffer with Enable Quad Bus Driver Dual Simultaneous Transceiver Hex Buffer with Invert/ Non-invert control Monostable multivibrator High Speed Dual D-type M/S Flip Flop Voltage Controlled Multivibrator Dual Clocked RS Flip Flop Dual Clocked Latch D-type Master/slave Flip Flop
20
6. Functional index of digital integrated circuits of ECL family

Table C.14 to Table C.19 list the functional indices of the digital integrated circuits of the ECL family for Logic gates and related devices, arithmetic circuits, multiplexers and demultiplexers, Flip Flops and Counters and Registers respectively. (ECL family is discussed in detail in chapter-5, logic gates in chapter-4, arithmetic circuits in chapter-7, multiplexers, demultiplexers, encoders and decoders in chapter 8, flip flops in chapter 10 and counters and registers in chapter-11 of the book). Table C.14 Logic Gates belonging to ECL family Type Number
10100 10101 10102 10103 10104 10113 10114 10115 10116 10117 10118 10123 10128 10129 10188 10192 10194 10195
Function
Quad 2-input NOR gate with strobe Quad 2-input OR/NOR gate Quad 2-input NOR gate Quad 2-input OR gate Quad 2-input AND gate Quad 2-inpu EX-OR gate Triple Line Receiver Quad Line Receiver Triple Line Receiver Dual 2-wide 2-3 input OR-AND/OR-AND-INVERT gate Dual 2-wide 3-input OR-AND gate Triple 4-3-3 Input Bus Driver Dual Bus Driver Quad Bus Driver Hex Buffer with Enable Quad Bus Driver Dual Simultaneous Transceiver Hex Buffer with Invert/Non-invert control
21
Table C.15 Arithmetic Circuits belonging to ECL family
Type Number
10179 10180 10181 10182 10183
Function
Look Ahead Carry Block Dual High Speed 2-Bit Adder/Subtractor 4-Bit Arithmetic Logic Unit/Function Generator 4-Bit Arithmetic Logic Unit/Function Generator 42 Multiplier
22
Table C.16 Multiplexers and Demultiplexer Circuits belonging to ECL family
Type Number
10132 10134 10158 10159 10161 10162 10164 10165 10171 10172 10173 10174
Function
Dual 2-input multiplexer with latch and common reset Dual multiplexer with latch Quad 2-input multiplexer (non-inverting) Quad 2-input multiplexer (inverting) 3-to-8 line decoder (LOW) 3-to-8 line decoder (HIGH) 8-line multiplexer/latch 8-input priority encoder Dual 2-to-4 line decoder (LOW) Dual 2-to-4 line decoder (HIGH) Quad 2-input multiplexer/latch Dual 4-to-1 multiplexer
23
Table C.17 Flip Flops belonging to ECL family
Type Number MC10130 MC10131 MC10133 MC10135 MC10153 MC10168 MC10175 MC10176 MC10198 MC10231 MC1666 MC1668 MC1670 MC1658 Quad D-type Latch
Function
Dual D-type Master/Slave Flip Flop Quad D-type Latch (Negative transition) Dual JK Master/Slave Flip Flop Quad Latch (Positive transition) Quad D-type Latch Quint Latch Hex D-type Master/Slave Flip Flop Monostable multivibrator High Speed Dual D-type M/S Flip Flop Dual Clocked RS Flip Flop Dual Clocked Latch D-type Master/slave Flip Flop Voltage Controlled Multivibrator
24
Table C.18 Counters and Registers belonging to ECL family
Type Number
MC 10136 MC 10137 MC 10141 MC 10154 MC 10178
Function
Universal Hexadecimal Counter Universal Decade Counter 4-Bit Universal Shift Register Binary Counter (4-bit) 4-bit binary counter
25
7. Popular A/D converters

Table C.19 enlists some of the popular A/D converter type numbers along with their salient features. (A/D converters are discussed in detail in chapter 12 of the book). Table C.19 Popular A/D Type Numbers Type Number
AD 570 AD 571 AD 572 AD 573 AD 574A AD 575 AD 578 AD 579 AD 670 AD 673 AD 674A AD 678 AD 679 AD 770 AD 779 AD 1170 AD 1376 AD 1377 AD 1380 AD 1678 AD 1679 AD 1779 AD 1871 AD 5200/ 5210 series AD 7572 AD 7575 AD 7576 8-bit A/D converter 10-bit A/D converter 12-bit successive approximation type A/D converter 10-bit A/D converter 12-bit A/D converter 10-bit A/D converter with serial output 12-bit A/D converter 10-bit A/D converter Low cost 8-it A/D converter 8-it A/D converter 12-it A/D converter 12-bit 200 KSPS complete sampling A/D converter 14-bit 100 KSPS complete sampling A/D converter 200 MSPS wide band 8-bit A/D converter 14-bit 100 KSPS complete sampling A/D converter High resolution integrating A/D converter High speed 16-bit A/D converter High speed 16-bit A/D converter Low cost 16-bit sampling A/D converter 12-bit 200 KSPS sampling A/D converter 14-bit 100 KSPS sampling A/D converter 14-bit 100 KSPS sampling A/D converter 24-bit 96 kHz multi-bit sigma-delta A/D converter 12-bit successive approximation high accuracy A/D converter LC2MOS high speed 12-bit A/D converter LC MOS 5 s 8-bit A/D converter with Track/Hold
2
Description
Manufacturer
Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices
LC2MOS 10 s P-compatible 8-bit A/D converter
26
Table C.19 (contd.) Type Number

AD 7578 AD 7579/ 7580 AD 7582 AD 7672 AD 7772 AD AD 7820/7821 7824/7828
2
Description
CMOS 12-bit successive approximation A/D converter LC MOS 10-bit sampling A/D converter CMOS 12-bit successive approximation A/D converter LC MOS high speed 12-bit A/D converter LC MOS serial output 12-bit A/D converter LC MOS High speed P-compatible 8-bit A/D converters with Track/Hold function
2 2 2
Manufacturer
Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices
LC2MOS High speed 4 (7824) and 8 (7828) channel 8-bit converters LC2MOS 12-bit 100 kHz sampling A/D converter LC MOS 14-bit sampling A/D converters
2 2
A/D
AD 7870 AD 7871/ 7872 AD 7878 AD 9000 AD 9002 AD 9003 AD 9005 AD 9006/9016 AD 9011 AD 9012 AD 9028/9038 AD 9048 AD-ADC 71/72 AD-ADC80 AD-ADC84/85, AD 5240 ADC 1130/1131 ADC 1140 CAV 1040 CAV 1205 CAV 1220 HAS 1201 HAS 1204 HAS 1409 MOD 1205
LC MOS 12-bit 100 kHz sampling A/D converter with DSP interface High speed 6-bit A/D converter High speed 8-bit A/D converter 12-bit 1 MHz A/D converter 12-bit 10MSPS A/D converter High speed 6-bit A/D converters 8-bit 10MSPS A/D converter High speed 8-bit TTL A/D converter High speed 8-bit A/D converters 8-bit video A/D converter High resolution 16-bit A/D converters 12-bit successive approximation A/D converter Fast 12-bit A/D converters 14-bit high speed A/D converter Low cost 16-bit A/D converter 10-bit video A/D converter 12-bit 5 MHz Eurocard A/D converter 12-bit video A/D converter 12-bit 1 MHz A/D converter Ultra high speed 12-bit A/D converter 14-bit 125KHz A/D converter 12-bit video A/D converter
27
Table C.19 (Contd.)
Type Number
ADC 700 ADC 774 ADS 574 ADS 602 ADS 774 ADS 7800 ADS 7803 DSP 101/ 102 ADC 601 ADC 603 ADC 614 ADC 701/ SHC 702 ADC 7802 PCM 78P ADC-908 ADC 910 ADC 912 ADC 922 PM 0820 PM 7572 PM 7574 ADC 0800 ADC 0801/ 0802/0803/ 0804/0805 ADC 0808/0809 ADC 0816/0817 ADC 0833 ADC 1001/1021 ADC 1080/1280 ADC1210/ 1211
Description
16-bit P-compatible A/D converter 12-bit P-compatible A/D converter 12-bit P-compatible sampling CMOS A/D converter 12-bit 1MHz sampling A/D converter 12-bit P-compatible sampling CMOS A/D converter 12-bit 3 s sampling A/D converter Auto calibrating 4-channel 12-bit A/D converter DSP compatible sampling single channel (DSP 101)/ Dual channel (DSP 102) A/D converters 12-bit 900 ns A/D converter 12-bit 10 MHz sampling A/D converter 14-bit 5.12 MHz sampling A/D converter 16-bit 512 kHz sampling A/D converter Auto calibrating 4-channel 12-bit A/D converter 16-bit audio A/D converter CMOS P-compatible fast A/D converter 10-bit P-compatible high speed A/D converter CMOS P-compatible 12-bit A/D converter 12-bit 3 s A/D converter CMOS 8-bit high speed A/D converter 12-bit high speed BiCMOS A/D converter CMOS P-compatible 8-bit A/D converter 8-bit A/D converter 8-bit P-compatible A/D converter
Manufacturer
Burr Brown Burr Brown Burr Brown Burr Brown Burr Brown Burr Brown Burr Brown Burr Brown Burr Brown Burr Brown Burr Brown Burr Brown Burr Brown Burr Brown PMI PMI PMI PMI PMI PMI PMI National National
8-bit P-compatible A/D converter with 8-channel multiplexer 8-bit P-compatible A/D converter with 16-channel multiplexer 8-bit serial multiplexer input/output A/D converter with 4-channel
National National National National National National
10-bit P-compatible A/D converter 12-bit successive approximation A/D converter 12-bit CMOS A/D converter
28
Table C.19 (Contd.)
Type Number
TLC 0820 TLC 7135 TLC 0808/0809 TLC 5501 TLC 5502-5 TLC 5503-2 TLC 5503-5 ICL 7106 4 digit A/D converter
Description
8-bit high speed A/D converter TI TI TI TI TI TI TI
Manufacturer
Low power CMOS 8-bit A/D converter with 8-channel multiplexer Ultra high speed 6-bit A/D converter Ultra high speed 8-bit A/D converter Low power ultra high speed video A/D converter Low power ultra high speed 8-bit flash A/D converter High performance low power A/D converter of dual slope integrating type with LCD interface for DPM and DVM applications High performance low power A/D converter of dual slope integrating type with LED interface for DPM and DVM applications
INTERSIL
ICL 7107
INTERSIL
29
8. Popular D/A converters

Table C.20 enlist some of the popular D/A converter type numbers along with their salient features. (D/A converters are discussed in detail in chapter-12 of the book). Table C.20 Popular D/A Type Numbers Type Number
AD 390 AD 392 AD 394/395 AD 396 AD 561 AD 562/563 AD 565A/566A AD 568 AD 569 AD 662 AD 664 AD 667 AD 668 AD 1145 AD 1147/1148 AD 7111 AD 7224 AD 7225 AD 7226 AD 7228 AD 7237/47 AD 7245/48 AD 7524 AD 7528 AD 7533 AD 7534 AD 7535 AD 7536 AD 7537 AD 7538
Description
Quad 12-bit P-compatible D/A converter Quad 12-bit D/A converter Quad 14-bit P-compatible multiplying D/A converter Quad 14-bit P-compatible multiplying D/A converter Low cost monolithic 10-bit D/A converter 12-bit D/A converters High speed 12-bit monolithic D/A converters Ultra-high speed 12-bit monolithic D/A converter 16-bit Monotonic voltage output D/A converter 12-bit single supply 12-bit voltage output D/A converter Quad 12-bit D/A converter 12-bit P-compatible D/A converter 12-bit ultra-high speed multiplying D/A converter Low cost 16-bit D/A converter 16-bit P-compatible D/A converter CMOS logarithmic D/A converter LC MOS 8-bit D/A converter with output amplifier LC MOS quad 8-bit D/A converter with separate Reference inputs LC2MOS quad 8-bit D/A converter LC MOS octal 8-bit D/A converter LC MOS dual 12-bit D/A converter LC2MOS 12-bit D/A converter CMOS 8-bit buffered multiplying D/A converter CMOS dual 8-bit buffered multiplying D/A converter CMOS low cost 10-bit multiplying D/A converter LC MOS P-compatible 14-bit D/A converter
2 2 2 2 2
Manufacturer
Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices
LC2MOS P-compatible 14-bit D/A converter LC2MOS P-compatible 14-bit D/A converter LC MOS P-compatible (8+4) loading dual 12-bit D/A converter
2
LC2MOS P-compatible 14-bit D/A converter
30
Table C.20 (Contd.) Type Number

AD 7541A AD 7542 AD 7543 AD 7545 AD 7547 AD 7548 AD 7549 AD 7840 AD7845 AD 7846 AD 9700 AD 9701 AD 9768 AD-DAC71/72 AD-DAC80/ DAC85/DAC87 DAC 667 DAC 700/01/02/03 DAC 707/08/09 DAC 813 DAC 2814 DAC 2815 DAC 4814 DAC 4815 DAC 7800/01/02 DAC 65 DAC 650 DSP 201/202 DAC 800/0801/0802 DAC 806/0807/0808 DAC 830/0831/0832 DAC 000/01/02 /06//07/08 DAC 1020/21/22 DAC 1200/01 DAC 1208/09/10 DAC 1218/19
Description
12-bit CMOS multiplying D/A converter 12-bit CMOS P-compatible D/A converter 12-bit CMOS serial-input D/A converter 12-bit CMOS buffered multiplying D/A converter LC2MOS parallel loading dual 12-bit D/A converter LC MOS P-compatible 12-bit D/A converter
2
Manufacturer
Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Burr Brown Burr Brown Burr Brown Burr Brown Burr Brown Burr Brown Burr Brown Burr Brown Burr Brown Burr Brown Burr Brown Burr Brown National National National National National National National National
LC2MOS dual 12-bit P-compatible D/A converter LC MOS complete 14-bit D/A converter LC MOS complete 12-bit multiplying D/A converter LC MOS 16-bit voltage output D/A converter Monolithic video D/A converter 250 MHz video D/A converter Ultra-high speed D/A converter 16-bit D/A converter Complete low cost monolithic D/A converter 12-bit P-compatible D/A converter 16-bit D/A converters 16-bit P-compatible D/A converter 12-bit P-compatible D/A converter Dual 12-bit D/A converter with serial interface Dual 12-bit D/A converter with 8-bit port interface Quad 12-bit D/A converter with serial interface Quad 12-bit D/A converter with 8-bit port interface Dual monolithic CMOS multiplying D/A converters 12-bit high speed D/A converter 12-bit 500 MHz D/A converter DSP compatible single/dual D/A converter 8-bit D/A converters 8-bit D/A converters 8-bit P-compatible double buffered D/A converters P-compatible double buffered D/A converters 10-bit binary multiplying D/A converters 12-bit D/A converters 12-bit P-compatible double buffered D/A converters 12-bit binary multiplying D/A converters
2 2 2
31
Table C.20 (Contd.) Type Number

DAC 1220/21/22 DAC 1230/31/32 DAC 1280/80A DAC 1285/85A (DAC 85/87) AD 7520/7530 AD 7521/7531 TLC 7524 TLC 7528 TL 5601 TL 5602 DAC-08 series MC 1508-8/14088/1408-7 NE 5007/5008 /SE 5008 NE/SE 5009 NE/SE 5018 NE/SE 5118 NE/SE 5119 NE 5020 DAC-08 DAC-10 DAC 4881 DAC 4888 DAC 6012 DAC 8565 DAC-01 DAC-02/03 DAC-08 DAC-10 DAC-20 DAC-86 DAC-88 DAC-89 DAC-100
Description
12-bit binary multiplying D/A converters 12-bit P-compatible double buffered D/A converters 12-bit D/A converters 12-bit D/A converters 10-bit multiplying D/A converters 12-bit multiplying D/A converters 8-bit multiplying D/A converter Dual 8-bit multiplying D/A converter Ultra-high speed 6-bit D/A converter Ultra-high speed video D/A converter 8-bit high speed multiplying D/A converters 8-bit multiplying D/A converters 8-bit high speed multiplying D/A converters 8-bit high speed multiplying D/A converters 8-bit P-compatible D/A converters 8-bit P-compatible D/A converters (current output) 8-bit P-compatible D/A converters (current output) 10-bit P-compatible D/A converter 8-bit high speed multiplying D/A converter 10-bit high speed multiplying D/A converter High performance P-compatible 12-bit D/A converter 8-bit P-compatible D/A converter 12-bit high speed multiplying D/A converter 12-bit high speed multiplying D/A converter 6-bit voltage output D/A converter 10-bit voltage output D/A converters 8-bit high speed multiplying D/A converter 10-bit high speed multiplying D/A converter 2-digit BCD high speed multiplying D/A converter Companding D/A converter Companding D/A converter Companding D/A converter 10-bit current output D/A converter
Manufacturer
National National National National National National TI TI TI TI Signetics Signetics Signetics Signetics Signetics Signetics Signetics Signetics Raytheon Raytheon Raytheon Raytheon Raytheon Raytheon PMI PMI PMI PMI PMI PMI PMI PMI PMI
32
Table C.20 (Contd.)
Type Number
DAC-108 DAC-312 DAC-400 DAC-888 DAC-1408 DAC-8012 DAC-8043 DAC-8143 DAC-8212 DAC-8221 DAC-8222 DAC-8228/29 DAC-8248 DAC-8408 DAC-8412 DAC-8426 DAC-8800 PM-562 PM-6012 PM-7224 PM-7226 PM-7228 PM-7524 PM-7528 PM-7533 PM-7541 PM-7542 PM-7543 PM-7545/ PM-7645 PM-7628
Description
8-bit high speed multiplying D/A converter 12-bithigh speed multiplying D/A converter 12-bit Ultra-high speed multiplying D/A converter 8-bit high speed P-compatible Multiplying D/A converter 8-bit multiplying D/A converter 12-bit CMOS multiplying D/A converter with memory 12-bit CMOS multiplying D/A converter with serial input 12-bit serial daisy-chain CMOS D/A converter Dual 12-bit buffered multiplying CMOS D/A converter Dual 12-bit buffered multiplying CMOS D/A converter Dual 12-bit double buffered multiplying CMOS D/A converter Dual 8-bit CMOS D/A converter with voltage output Dual 12-bit double buffered CMOS D/A converter Quad 8-bit multiplying CMOS D/A converter with memory Quad 12-bit voltage output Bi-CMOS D/A converter Quad 8-bit voltage output CMOS D/A converter with internal 10 volts reference Octal 8-bit CMOS D/A converter 12-bit multiplying current output D/A converter 12-bit high speed multiplying D/A converter 8-bit CMOS D/A converter with voltage output Quad 8-bit CMOS D/A converter with voltage output Octal 8-bit D/A converter 8-bit CMOS buffered multiplying D/A converter Dual 8-bit CMOS buffered multiplying D/A converter CMOS low cost 10-bit multiplying D/A converter 12-bit CMOS multiplying D/A converter 12-bit CMOS multiplying D/A converter 12-bit CMOS multiplying D/A converter with serial input 12-bit buffered multiplying CMOS D/A converter Dual 8-bit buffered multiplying CMOS D/A converter
Manufacturer
PMI PMI PMI PMI PMI PMI PMI PMI PMI PMI PMI PMI PMI PMI PMI PMI PMI PMI PMI PMI PMI PMI PMI PMI PMI PMI PMI PMI PMI PMI
33
9. Popular Microprocessors
Table C.21 to C.24 enlist some of the popular 8-bit, 16-bit, 32-bit and 64-bit microprocessors respectively along with their salient features. (Microprocessors are discussed in detail in chapter-13 of the book).
Table C.21 8-bit microprocessors

Type Number 8080 8085 8088 6800 6809 NSC800 SC/MP II 1802 2650 Intel Intel Intel Motorola Motorola National Semiconductor National Semiconductor RCA Signetics Manufacturer Salient Features Successor to Intel 8008 CPU Enhanced version of Intel 8080 CPU 8 bit version of Intel 8086 CPU Motorolas first microprocessor. Had very similar architecture to the 8080 Enhanced version of the 6800 microprocessor 8-bit CMOS CPU with the instruction set of Zilog's Z80 and the multiplexed bus of Intel's 8085 Designed to fill the gap between four-bit CPUs (4004, 4040) and eight-bit microprocessors one-chip implementation of the earlier two-chip RCA 1801 Had a full complement of video, communications, and keyboard interface chips designed for use in video display terminals RISC like microprocessor Improved version of 8080 processor High-integration version of Z80 processor
8X300 Z80 Z180
Signetics Zilog Zilog
34
Table C.22 16-bit microprocessors

Type Number 8086 80186 80188 80286 68000 68010 68012 V30 V50 TMS9900 Z800x Intel Intel Intel Intel Motorola Motorola Motorola NEC NEC TI Zilog Manufacturer Salient Features First generation of 80X86 processors Mostly used as embedded processor Mostly used as embedded processor Second generation of 80X86 processors First generation of Motorola 680X0 processors Second generation of Motorola 680X0 processors Second generation of Motorola 680X0 processors 8086-compatible processor with 8080 emulation mode 8086-compatible processor with integrated peripherals and 8080 emulation mode Single chip version of the TI 990 microcomputer series 16-bit microprocessor with separate code, data and stack memory space
35
Table C.23 32-bit microprocessors Type Number

29000 29030 29040 K5 K6 K6-2 K6-III K7 SA-110 ARM 80386 80486 Pentium Pentium II Celeron Pentium III Pentium IV Xeon 80860 80960 68020 68030 68040 68060 PowerPC 603 32016 Intel Intel Intel Intel Intel Intel Intel Intel Intel Intel Motorola Motorola Motorola Motorola Motorola National semiconductor
Manufacturer
AMD AMD AMD AMD AMD AMD AMD AMD
Salient Features
Embedded RISC microprocessor Embedded RISC microprocessor High performance embedded RISC microprocessor Pentium class processor Pentium/Pentium II class processor Pentium II class processor, enhanced version of K6 Pentium II class processor enhanced version of K6-2 Pentium III/IV processor Low-power embedded strongARM microprocessor Third generation of 80x86 processors Fourth generation of 80x86 processors Fifth generation of 80x86 processors superscalar architecture MMX Sixth generation of 80x86 processors Low cost version of Pentium II Enhanced and faster version of Pentium II New generation of Pentium processors High performance version of Pentium IV Embedded 32-bit microprocessor with integrated 3D graphics Embedded 32-bit microprocessor Third generation of 680X0 series of processors Fourth generation of 680x0 series of processors Fifth generation of 680x0 series of processors Sixth generation of 680x0 series of processors RISC microprocessor 32-bit microprocessor with 16-bit data bus
36
Table C.24 64-bit microprocessors Type Number

K8 Itanium Core 2 R4000 R4400 R4600 R5000 R10000 UltraSparc II UltraSparcIIi UltraSparc III AMD Intel Intel MIPS Technologies MIPS Technologies MIPS Technologies MIPS Technologies MIPS Technologies Sun Microsystems Sun Microsystems Sun Microsystems RISC processor Enhanced version of R4000 RISC processor Enhanced version of R4400 RISC processor Super-scalar RISC microprocessor Super-scalar RISC microprocessor Second generation of UltraSparc processors Second generation of UltraSparc processors Third generation of UltraSparc processors
Manufacturer
Salient Features
Eighth generation of X86 processors High performance
37
10. Popular microcontrollers

Table C.25-27 lists some of the popular 8-bit, 16-bit and 32-bit microcontroller type numbers along with their salient features. (Microcontrollers are discussed in detail in chapter-14 of the book). Table C.25 8-bit microcontrollers
Type Number 80C51/87C51/ 80C31 80C31FA/8XC 51FA/FB/FC 80C31RA+/8X C51RA+/RB+/ RC+ 8XC51RD+ Manufacturer Dallas Semiconductor and Other Manufacturers Dallas Semiconductor and Other Manufacturers Dallas Semiconductor and Other manufacturers Dallas Semiconductor and Other manufacturers Dallas Semiconductor and Other Manufacturers ATMEL and Other Manufacturers Freescale Semiconductor Freescale Semiconductor Salient features MCS-51 architecture, CMOS technology Same as 80C51 except for the size of ROM and RAM, which is 0K/8K/16K/32K ROM and 256 bytes RAM The same as 80C51 except for the size of ROM and RAM, which is 0K/8K/16K/32K ROM and 512 bytes RAM The same as 80C51 except for the size of ROM and RAM, which is 64K ROM and 1024 bytes RAM The same as 80C51 except for the size of ROM and RAM, which is 0K/8K/16K/32K ROM and 256 bytes RAM MCS-51 architecture, CMOS technology, 4K 8 of in-system reprogrammable ROM, 128 8 internal RAM Eight-bit M68HC05 core, a clock speed of 4 MHz, 920 bytes of on-chip RAM, 32K of ROM Fully static chip design using an eight-bit M68HC11 core, a clock speed of 5 MHz, 0/256/512/768/1024 bytes of on-chip RAM (in different variants), 0/12/20 kB of on-chip ROM or EPROM High-performance RISC CPU, 14-bit wide instructions, eight-bit wide data path, 1024 14 EEPROM program memory, 64 bytes of on-chip data EEPROM High performance microcontrollers 128 or 256 bytes of RAM up to 128 bytes of I/O, 512 bytes to 64kB ROM 8-bit Harvard architecture ROM/EPROM/OTP microcontroller with on-chip SRAM Improved version of Z8 with better pipelining feature and with on-chip flash memory and SRAM
80C32/8XC52/ 54/58 89C51
68HC05 Family of 68HC11 Family
PIC 16X84 Family
(Microchip Technology)
XC-800 Family MCS-51 Z8 eZ8 (Encore Z8)
Infineon Intel Zilog Zilog
38
Table C.26 16-bit microcontrollers
Type Number
68HC12 Family 68HC16 Family XC166 Family
Manufacturer
Freescale Semiconductor
Salient features
High-performance 16-bit CPU core with 1024 bytes of RAM, 32K of flash EEPROM and 768 bytes of EEPROM 16-bit enhancement of the eight-bit 68HC11 family with 8K of ROM, 4K of RAM The same as 80C51 except for the size of ROM and RAM, which is 0K/8K/16K/32K ROM and 512 bytes RAM 16-128 kB of Flash memory, 4kB/8kB data RAM 12-256 kB of Flash memory, 1kB/8kB/16kB data RAM Commonly used in Embedded systems Improved version of MCS-96 family
Freescale Semiconductor Infineon
PIC 24F PIC 24H MCS-96 family MCS 296 family
Microchip Technology Microchip Technology Intel Intel
39
Table C.27 32-bit microcontrollers

Type Number 683XX Family Manufacturer Freescale Semiconductors Salient features 10K of RAM, 256K of flash, a clock speed of 33 MHz, 48 I/O lines, a 16-bit timer, a 16-channel/10bit A/D converter and four serial communication channels 32K of RAM, 256K of flash, 33 MHz of clock speed, two serial communication channels, 104 I/O lines, an eight-channel A/D converter and two timers Configured around a 32-bit PowerPC core with 36K of RAM, 1024K of flash, a 66 MHz clock, three serial communication channels, 101 I/O lines, 40 channels of A/D conversion and 70 timer channels Configured around ColdFire Version 2 core with 64K RAM, 66 MHz clock, 5 serial communication channels, including an I2C bus and CAN support, 150 I/O lines and 4 timer channels Based on Philips Nexperia platform, configured around an ARM926EJ core with the VFP9 floating-point coprocessor with 32K of instruction cache and 32K of data cache Unified, single-core 32-bit microcontroller DSP architecture optimized for real-time embedded systems
MCORE Family
Freescale Semiconductors
MPC500 Family
MCFXXX Family
LPC3000 Family
Philips Semiconductors
TRICORETM Family
Infineon
40
11. Pin connection diagrams and other relevant application information on logic gates and related devices
Figs.C.1 to C.31 give the pin connection diagram and other application relevant information of some of the popular logic gates and related devices. (Logic gates and other related devices are discussed in detail in chapter-4 of the book).
Quad 2-input NAND 1A 1B 1Y 2A 2B 2Y GND

7 8 1 1 7400 14 14 1 14
VCC 4B 4A 4Y 3B 3A 3Y
nA, nB = Data Inputs nY = Data Output

A 0 0 1 1 B 0 1 0 1 Y 1 1 1 0
Y=A.B = A+B
Fig.C.1
Quad 2-input NOR 1Y 1A 1B 2Y 2A 2B GND

7 8 7402 1 14
VCC 4Y 4B 4A 3Y 3B 3A

A 0 0 1 1 B 0 1 0 1 Y 1 0 0 0
Y=A+B=A.B
Fig.C.2
Hex Inverter 1A 1Y 2A 2Y 3A 3Y GND 7 8 1 1 7404 7400 14 14 1 14 VCC 6A 6Y 5A 5Y 4A 4Y nA = Data Inputs nY = Data Output
A 0 1 Y=A Y 1 0
Fig.C.3
41
Quad 2-Input AND 1A 1B 1Y 2A 2B 2Y GND 7 8 1 1 7408 7400 14 14 1 14 VCC 4B 4A 4Y 3B 3A 3Y nA, nB = Data Inputs nY = Data Output
A 0 0 1 1 B 0 1 0 1 Y=A .B Y 0 0 0 1
Fig.C.4
Triple 3-Input NAND nA, nB, nC = Data Inputs nY = Data Output 1A 1B 2A 2B 2C 2Y GND 7 8 7410 1 14 VCC 1C 1Y 3C 3B 3A 3Y
A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Y 1 1 1 1 1 1 1 0
Y=A.B.C
Fig.C.5
Triple 3-Input AND

nA, nB, nC = Data Inputs nY = Data Output 1A 1B 2A 2B 2C 2Y GND 7 8 1 14 VCC 1C 1Y A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Y 0 0 0 0 0 0 0 1
7411
3C 3B 3A 3Y
Y=A.B.C
Fig.C.6
42
Dual 4-Input NAND nA, nB, nC, nD = Data Inputs nY = Data Output 1A 1B NC 1C 1D 1Y GND 7 8 7420 1 14 VCC 2D 2C NC 2B 2A 2Y
A 0 X X X 1 B X 0 X X 1 C X X 0 X 1 D X X X 0 1 Y 1 1 1 1 0
Y=A.B.C.D
Fig.C.7
Dual 4-Input AND nA, nB, nC, nD = Data Inputs nY = Data Output 1A 1B NC 1C 1D 1Y GND 7 8 7421 1 14 VCC 2D 2C NC 2B 2A 2Y
A 0 X X X 1 B X 0 X X 1 C X X 0 X 1 D X X X 0 1 Y 0 0 0 0 1
Y=A.B.C.D
Fig.C.8
Triple 3-Input NOR nA, nB, nC = Data Inputs nY = Data Output 1A 1B 2A 2B 2C 2Y GND 7 8 7427 1 14 VCC 1C 1Y 3C 3B 3A 3Y
A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Y 1 0 0 0 0 0 0 0
Y=(A+B+C)
Fig.C.9
43
8-Input NAND A through H = Data Inputs Y = Data Output A B C D E F GND 7 8 7430 1 14 VCC NC H G NC NC Y
A 0 X X X X X X 1 B X 0 X X X X X 1 C X X 0 X X X X 1 D X X X 0 X X X 1 E X X X X 0 X X 1 F X X X X X 0 X 1 G X X X X X X 0 1 H X X X X X X X 1 Y 1 1 1 1 1 1 1 0
Y =(A.B.C.D.E.F.G.H )
Fig.C.10
Quad 2-Input OR 1A 1B 1Y 2A 2B 2Y GND 7 8 7432 1 14 VCC 4B 4A 4Y 3B 3A 3Y nA, nB = Data Inputs nY = Data Output
A 0 0 1 1 B 0 1 0 1 Y=A+B Y 0 1 1 1
Fig.C.11
Quad 2-Input NOR 1A 1B 1Y 2A 2B 2Y GND 7 8 7436 1 14 VCC 4B 4A 4Y 3B 3A 3Y nA, nB = Data Inputs nY = Data Output
A 0 0 1 1 B 0 1 0 1 Y=(A+B) Y 1 0 0 0
Fig.C.12
44
Dual 4-Input NAND

nA, nB, nC, nD = Data Inputs nY = Data Output 1A 1B NC 1C 1D 1Y GND 7 8 1 14 VCC 2D 2C A 0 X X X 1 B X 0 X X 1 C X X 0 X 1 D X X X 0 1 Y 1 1 1 1 0
7440
NC 2B 2A 2Y
Y=A.B.C.D
Fig.C.13
Quad Non-inverting tristate buffer nA = Data Inputs nY = Data Output nOC = 3-state active control (Active LOW for 74125, Active HIGH for 74126)
74125 OC 0 0 1 A 0 1 X Y 0 1 Z 74126 OC 1 1 0 A 0 1 X Y 0 1 Z
1OC 1A 1Y 2OC 2A 2Y GND
14
VCC 4OC 4A
74125/ 74126
4Y 3OC 3A
3Y
Fig.C.14
Dual 4-Bit Buffer 1G 1A0 2Y3 1A1 2Y2 1A2 2Y1 1A3 2Y0 GND 10 11 74240/ 74241/ 74244 1 20 VCC nA0 through nA3 = Data Inputs nY0 through nY3 = Data Outputs 2G 1Y0 2A3 74240 : Inverting outputs 1Y1 74241 : Non-inverting outputs 74244 : Non-inverting outputs 2A2 1Y2 2A1 1Y3 2A0
742 40 G 0 0 1 A 1 0 X 742 41 1G 0 0 1 1A 0 1 X 1Y 0 1 Z 742 44 G 0 0 1 A 0 1 X 1Y 0 1 Z 2G 0 1 1 2A X 0 1 2Y Z 0 1 Y 0 1 Z
Fig.C.15
45
Quad 2-Input NOR 1A 1B 1Y 2Y 2A 2B VSS 7 8 4001 1 14 VDD 4B 4A 4Y 3Y 3B 3A

Y=A+B = A.B

A 0 0 1 1 B 0 1 0 1 Y 1 0 0 0
Fig.C.16
Du al 4-Inp ut NOR nA, nB, nC, nD = Data Inputs nY = Data Output 1Y 1A 1B 1C 1D NC

VSS
14
VDD 2Y 2D
A 0 1 X X X B 0 X 1 X X C 0 X X 1 X D 0 X X X 1 Y 1 0 0 0 0
4002
2C 2B 2A
NC
Y=A+B+C+D
Fig.C.17
Quad 2-Input NAND 1A 1B 1Y 2Y 2A 2B VSS 7 8 4011 1 14 VDD 4B 4A 4Y 3Y 3B 3A nA, nB = Data Inputs nY = Data Output
A 0 0 1 1 B 0 1 0 1 Y=A.B Y 1 1 1 0
Fig.C.18
46
Quad 2-Input EX-OR A1 B1 Y1 Y2 A2 B2 VSS 7 8 4030 1 14 VDD B4 A4 Y4 Y3 B3 A3 An, Bn = Data Inputs Yn = Data Output
A 0 0 1 1 B 0 1 0 1 Y=A + B Y 0 1 1 0
Fig.C.19
Hex Inverting Buffer VDD 1Y 1A 2Y 2A 3Y 3A VSS 8 9 4049 1 16 NC 6Y 6A NC 5Y 5A 4Y 4A

Y= A
nA = Data Inputs nY = Data O utput

A 0 1 Y 1 0
Fig.C.20
He x Non-inverting Buffer VDD 1Y 1A 2Y 2A 3Y 3A VSS 8 9 4050 1 16 NC 6Y 6A NC 5Y 5A 4Y 4A nA = Data Inputs nY = Data Output

A 0 1 Y=A Y 0 1
Fig.C.21
47
Quad 2-input EX-OR 1A 1B 1Y 2Y 2A 2B VSS 7 8 4070 1 14 VDD 4B 4A 4Y 3Y 3B 3A nA, nB = Data Inputs nY = Data Output
A 0 0 1 1 B 0 1 0 1 Y=A + B Y 0 1 1 0
Fig.C.22
Quad 2-Input OR 1A 1B 1Y 2Y 2A 2B VSS 7 8 4071 1 14 VDD 4B 4A 4Y 3Y 3B 3A nA, nB = Data Inputs nY = Data Outputs
A 0 0 1 1 B 0 1 0 1 Y=A+B Y 0 1 1 1
Fig.C.23
Quad 2-Input AND 1A 1B 1Y 2Y 2A 2B VSS 7 8 4081 1 14 VDD 4B 4A 4Y 3Y 3B 3A nA, nB = Data Inputs nY = Data Output
A 0 0 1 1 B 0 1 0 1 Y=A.B Y 0 0 0 1
Fig.C.24
48
Quad 2-Input Schmitt NAND 1A 1B 1Y 2Y 2A 2B VSS 7 8 4093 1 14 VDD 4B 4A 4Y 3Y 3B 3A nA, nB = Data Inputs nY = Data Output
A 0 0 1 1 B 0 1 0 1 Y=A.B Y 1 1 1 0
Fig.C.25
Quad 2-Input OR/NOR

nA = Independent Data Input nB = Common Data input nY = OR (true) Output nY = NOR (inverted) Output B 1 0 0 nA nY nY X 1 0 0 0 1 1 1 0
VCC1 1Y 2Y 1A 1Y 2Y 2A V EE
16
VCC2 4Y 3Y 4A B 3Y 3A
10101
4Y
nY = nA+B
Fig.C.26
Quad 2-Input OR Gate nA, nB = Data Inputs VCC2 1Y through 3Y= Data Outputs 4Y, 4Y = Complementary 4Y Output (gate 4) 3Y nB nA nY 4 B 4 A 4 Y 4Y 4B 0 0 0 0 0 0 1 4A 0 1 1 0 1 1 0 3B 1 0 1 1 0 1 0 3A 1 1 1 1 1 1 0 4Y 4Y = (4A+4B) Y = (nA+nB) n = 1,2,3
VCC1 1Y 2Y 1A 1B 2A 2B VEE
16
10103
Fig.C.27
49
Quad 2 -input AND Vcc1 1Y 2Y 1A 1B 2A 2B VEE 8 9 10104 Vcc2 4Y 3Y 4B 4A 3B 3A 4Y nY = (nA.nB) n= 1,2,3 4Y = (4A.4B)
nB nA nY 0 0 0 0 1 0 1 0 0 1 1 1 4B 0 0 1 1
16
nA,nB = Data Inputs 1Y through 3Y= Data o utputs 4Y, 4Y = Complemen tary Output (gate 4)
4 A 4 Y 4Y 0 0 1 1 0 1 0 0 1 1 1 0
Fig.C.28
Quad 2-Input Ex-OR Gate VCC1 1Y 2Y 1A 1B 2A 2B VEE 8 9 10113 nA, nB = Data Inputs VCC2 nY = Data Outputs 4Y OE B A Y 3Y X X 0 1 4B 4A 3B 3A OE
0 0 0 0 0 0 0 1 1 0 1 1 Y=OE (A + 0 1 1 0
16
B)
Fig.C.29
Triple Line Re ceiver (Differential Inputs and Outputs) Ain through Cin VCC1 Aout Aout Ain Ain Bout Bout VEE 8 9 10114/ 10116 1 16 VCC2 Cout Cout Cin Cin V Bin Bin
xin 0 0 1 1 xin xout xout 0 0 0 0 1 1 0 1 1 1 0 1
= Active-high data inputs Aout through C out = Active-low data ou tputs VBB = Input bias voltage
Fig.C.30
50
Quad Line Receiver (Differential Inputs, single-ended Outputs) Ain through Din VCC1 Aout Bout Ain Ain Bin Bin VEE 8 9 10115 1 16 VCC2 Dout Cout Din Din Cin Cin VBB
xin xin xout 0 0 0 0 1 1 1 0 1 0 0 1
= Active-high data inputs Aout through Dout = data outputs V = Input Bias voltage
Fig.C.31
51
12. Pin connection diagrams and other relevant application information on multiplexers and de-multiplexers
Figs.C.32 to C.48 give the pin connection diagram and other application relevant information of some of the popular multiplexer and demultiplexer devices. (Multiplexers and demultiplexers are discussed in detail in chapter-8 of the book).
BCD-to-Decimal Decoder (Open Collector Outputs) D CBA 0 1 2 3 4 5 6 7 8 9 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 01 10 11 11 11 11 11 11 11 11 01 10 11 11 11 11 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1
8 9 A D V c c B C 2
16
0 1 5 4
7441
Gnd 6 7
Over range
A through D: Data Inputs (A is LSB) 0 through 9 : Decoded Outputs (Active LOW)
Fig.C.32
BCD-to-Decimal decoder 0 1 2 3 4 5 6 Gnd 8 9 7442 1 16 Vcc A B C D 9 8 7 D CBA 0 1 2 3 4 5 6 7 8 9 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 01 10 11 11 11 11 11 11 11 11 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0
Invalid 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 11 11 11 11 11 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A through D: Data Inputs (A is LSB) 0 through 9 : Decoded Outputs (Active LOW)
Fig.C.33
52
BCD-to-Decimal decoder
0 1 2 3 4 5 6 Gnd
16
Vcc A B C
D C BA
0 1 2 3 4 5 6 7 8 9
7445
D 9 8
0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 1 1 1 0 0
0 0 1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1 0 1
0 1 1 1 1 1 1 1 1 1
1 0 1 1 1 1 1 1 1 1
1 1 0 1 1 1 1 1 1 1
1 1 1 0 1 1 1 1 1 1
1 1 1 1 0 1 1 1 1 1
1 1 1 1 1 0 1 1 1 1
1 1 1 1 1 1 0 1 1 1
1 1 1 1 1 1 1 0 1 1
1 1 1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 1 1 0
Invalid
A through D : Data Inputs (A is LSB) 0 through 9 : Decoded Outputs (Active LOW)
1 1 1 1 1 1
0 0 1 1 1 1
1 1 0 0 1 1
0 1 0 1 0 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
Fig.C.34
BCD-to-7 Segment Decoder(Active LOW Open Collector Outputs)
B C LT BI/RBO
16
Vcc f g
Funtion 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Blank Ripple Blank LampTest
LT RBI D C B A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 x 1 0 1 x x x x x x x x x x x x x x x x 0 x 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x 0 x 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x 0 x 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 x 0 x 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 x 0 x
BI/ a RBO 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 0 1 0 1 0 0 0 1 1 1 0 1 1 1 1 0
b 0 0 0 0 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0
c 0 0 1 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 0
d 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0
e f 0 1 0 1 1 1 0 1 0 1 0 1 1 1 0 1 1 1 0 0 1 1 1 0 0 0 1 0 0 1 1 0 0 0 1 1 1 0
g 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0
7447
a b c d
RBI D A Gnd
8 9
A through D : Data Inputs (A is LSB) a through g : Decoded Outputs (Active LO W) LT : Lamp Test Input RBI : Ripple Blanking Input BI/RBO : Blanking Input/ Blanking Output
Fig.C.35
53
BCD-to-7 Segment Decoder(Active LOW Open Collector O utputs)
B C LT BI/RBO
16
Vcc f g a
Funtion 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Blank Ripple Blank LampTest
LT RBI D C B A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 x 1 0 1 x x x x x x x x x x x x x x x x 0 x 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x 0 x 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x 0 x 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 x 0 x 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 x 0 x
BI/ a RBO 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 1 0 1 0 1 1 1 0 0 0 1 0 0 0 0 1
b 1 1 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 1
c 1 1 0 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 1
d 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0 0 0 1
e f 1 0 1 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 1 1 0 0 0 1 1 1 0 1 1 0 0 1 1 1 0 0 0 1
g 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1
7448
RBI D A Gnd
8 9
b c d e
A through D : Data Inputs (A is LSB) a through g : Decoded Outputs (Active LOW) LT : Lamp Test Input RBI : Ripple Blanking Input BI/RBO : Blanking Input/ Blanking Output
Fig.C.36
3 : 8 Line Decoder/Demultiplexer
A B C Clk G2 G1 Y7 Gnd
16
Vcc Y0 Y1 Y2
Clk X X X
G1 X 0 1 1 1 1 1 1 1 1 1
G2 1 X 0 0 0 0 0 0 0 0 0
C X X 0 0 0 0 1 1 1 1 X
B X X 0 0 1 1 0 0 1 1 X
A X X 0 1 0 1 0 1 0 1 X
Y0 1 1 0 1 1 1 1 1 1 1 0
Y1 1 1 1 0 1 1 1 1 1 1 0
Y2 1 1 1 1 0 1 1 1 1 1 0
Y3 1 1 1 1 1 0 1 1 1 1 0
Y4 1 1 1 1 1 1 0 1 1 1 0
Y5 1 1 1 1 1 1 1 0 1 1 0
Y6 1 1 1 1 1 1 1 1 0 1 0
Y7 1 1 1 1 1 1 1 1 1 0 0
74131
Y3 Y4 Y5
Y6
A, B, C Y0 through Y7 Clk G1, G2
: Select Inputs : Data Outputs : Clock Input : Output Enables
Fig.C.37
54
Decimal-to-BCD Priority Encoder (Active LOW Inputs/Outputs)
4 5 6 7 8 C B Gnd
16
Vcc NC D 3
74147
2 1 9
1 1 X X X X X X X X 0
2 1 X X X X X X X 0 1
3 1 X X X X X X 0 1 1
4 1 X X X X X 0 1 1 1
5 1 X X X X 0 1 1 1 1
6 1 X X X 0 1 1 1 1 1
7 1 X X 0 1 1 1 1 1 1
8 1 X 0 1 1 1 1 1 1 1
9 1 0 1 1 1 1 1 1 1 1
D 1 0 0 1 1 1 1 1 1 1
C 1 1 1 0 0 0 0 1 1 1
B 1 1 1 0 0 1 1 0 0 1
A 1 0 1 0 1 0 1 0 1 0
1 through 9 : Decimal Inputs A, B, C, D : BCD Priority Outputs
Fig.C.38
16 : 1 Multiplexer
D D7 D6 D5 D4 D3 D2 D1 D0 S W D Gnd 12 13 74150 1 24 Vcc D8 D9 D10 D11 D12 D13 D14 D15 A B C X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
C X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
B X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
S 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W 1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
D0 through D15 W A, B, C, D S
: Data Inputs : Data Output (Active LOW) : Select Inputs : Strobe
Fig.C.39
55
8 : 1 Multiplexer (With strobe input) D3 G 1 0 0 0 0 0 0 0 0 S2 S1 S0 X 0 0 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 Y 0 D0 D1 D2 D3 D4 D5 D6 D7 W D2 1 D0 D1 D2 D3 D4 D5 D6 D7 D1 D0 Y W G Gnd 8 9 74151 1 16 Vcc D4 D5 D6 D7 S0 S1 S2
D0 through D7 : Data Inputs Y : Data Output (Active HIGH) W : Data Output (Active LOW) S2, S1, S0 : Select Inputs G : Strobe Input
Fig.C.40
4 : 16 Line Decoder 0 1 2 3 4 5 6 7 8 9 10 Gnd 12 13 74154 G1 15 14 13 12 11 1 24 Vcc S0 S1 S2 S3 G2
S0 through S3 : Select Inputs 0 through 15 : Data Outputs G1, G2 : Strobe Inputs
Fig.C.41
56
BCD-to-Seven Segment Decoder B C LT BI/RBO RBI D A Gnd 8 9 74247/ 74248/ 74249 1 16 Vcc f g a b c d e 74247 : Active LOW outputs, Open Collector Outputs Function Table same as that of 7447 74248 : Active HIGH outputs, Internal Pull-up resistors Function Table same as that of 7448 74249 : Active HIGH outputs, Open Collector outputs Function Table same as that of 7448 A through D : BCD Inputs a through g : Seven Segment outputs LT : Lamp Test input RBI : Ripple Blanking Input BI/RBO : Blanking Input/Ripple blanking Output
Fig.C.42
8 : 1 Data Selector/Multiplexer S0, S1, S2 : Select Inputs D0 through D7 : Data inputs W : Inverted Data output Y : Non-inverted Data output G : 3-state output control
D3 D2 D1 D0 Y W G Gnd
16
Vcc D4 D5 D6
74251
D7 S0 S1
S2
Fig.C.43
Dual 4 : 1 Data Selector/Multiplexer 1G S1 1C3 1C2 1C1 1C0 1Y Gnd 8 9 74253 1 16 Vcc 2G S0 S0, S1 nC0 through nC3 2C3 nY 2C2 nG 2C1 2C0 2Y : Select Inputs : Data inputs : Data output : 3-state output control
Fig.C.44
57
BCD-to-7 Segment Latch Decoder Driver B C LT BL LE/Strobe D A Vss 8 9 4511 1 16 VDD f g a b c d e A, B, C, D : BCD inputs 'a' through 'g' : SevenSegment outputs LT : Lamp Test input BL : Blanking input LE : Latch Enable input
Fig.C.45
10-line to 4-line BCD priority encoder Inputs 0 1 2 3 4 5 6 7 8 4 5 6 7 8 C B Vss 8 9 40147 1 16 Vcc 0 D 3 2 1 9 A 0 1 X X X X X X X X X 0 0 1 X X X X X X X X 0 0 0 1 X X X X X X X 0 0 0 0 1 X X X X X X 0 0 0 0 0 1 X X X X X 0 0 0 0 0 0 1 X X X X 0 0 0 0 0 0 0 1 X X X 0 0 0 0 0 0 0 0 1 X X 0 0 0 0 0 0 0 0 0 1 X 9 0 0 0 0 0 0 0 0 0 0 1 Outputs D C B A 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1
Fig.C.46
Dual Multiplexers Vcc1 1Q 1Q 1D0 1D1 A0 Cc VEE 8 9 10134 1 16 Vcc 2Q 2Q 2D0 2D1 A1 0CE 1CE A0, A1 nD0-nD1 nQ, nQ nCE C L L L L H A0 L L H H X : Input Select : Data Inputs : Data Outputs : Clock Enable
nD0 nD1 Qn+1 L L L H H H L X L H H X X Qn Qn
C=CE+Cc
Fig.C.47
58
Quad 2-input Multiplexer
1Y 2Y 2D1 2D0 1D1 1D0 NC VEE
16
Vcc 3Y 4Y
SEL nY 0 1 nD1 nD0
10158/ 10159
3D0 3D1 4D0 4D1
nD0, nD1 : Data inputs nY : Data outputs SEL : Select input 10158 : Non-inverting outputs 10159 : Inverting outputs
SEL
Fig.C.48
59
13. Pin connection diagrams and other relevant application information on digital ICs for arithmetic operations
Figs.C.49 to C.60 give the pin connection diagram and other application relevant information of some of the popular digital ICs for arithmetic operations. (Arithmetic circuits discussed in detail in chapter-7 of the book).
A4 S3 A3 B3 V cc S2 B2 A2
16
B4 S4 C4
A1 to A4 B1 to B4 C0 S1 to S4 C4
: Word A Inputs : Word B Inputs : Carry Input : Sum Word Outputs : Carry Output
7483
C0 Gnd B1 A1
S1
Fig.C.49
B3 A<B A=B A>B A>B A=B A<B Gnd
16
Vcc A3
Inputs
}
8
Outputs
7485 TTL LS S ALS AS
B2 A2 A1 B1 A0 9 B0 A0 to A3 : Word A Inputs B0 to B3 : Word B Inputs
Fig.C.50
60
B0 A0 S3 S2 S1 S0
24
Vcc A1 B1 A2 B2 A3
74181 Cn M F0 F1 F2 Gnd 12 13
B3 G Cn+4 P A=B F3
A0 through A3 : Word A input B 0 through B3 : Word B input F0 through F3 : Output Word S 0 through S3 : Function Select input M : Mode Select input Cn : Carry input A=B : Equality Output (Active HIGH) Cn + 4 : Carry Output G : Carry Generate Output (Active LOW) P : Carry Propagate Output (Active LOW)
SELECTION S3 S2 S1 S0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 0 1 0
M=1 Logic Function A AB A+B 1 (A+B) B A +B A+B AB A +B B A+B 0 AB AB A
M=0 Cn = 0 Arithmetic Fuction A Minus 1 AB Minus 1 A B Minus 1 Minus 1 A Plus (A+B) AB plus (A+B) A Minus B minus 1 A+B A Plus (A + B) A plus B A B plus (A + B) A+ B A Plus A AB plus A A B minus A A
0 1 1 0 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1
Fig.C.51
61
G1 P1 G0 P0 G3 P3 P Gnd
16
Vcc P2 G2 G0 through G3 : Carry Generate Inputs P0 through P3 : Carry Propagate Inputs Cn : Carry Inputs Cn + x, Cn +y, Cn + z : Carry Outputs G : Carry Generate Output P : Carry Propagate Output
74182
Cn Cn+x Cn+y G
Cn+z
Cn X 0 X 1 X X 0 X X 1 X X X 0 X X X 1
G0 1 1 0 X X 1 1 X 0 X X X 1 1 X X 0 X X X X 1 X X X 0
P0 1 X X 0 X 1 X X X 0 X X 1 X X X X 0
G1
P1
G2
P2
G3
P3
Cn+x Cn+y Cn+z G P 0 0 1 1
1 1 1 0 X X X 1 1 1 X 0 X X X X 1 1 X X 0 X
1 X X X 0
1 X X X 0 0 X 1 X X X X 0 0 X X 1 X X X X 0 X 1 X X 0
0 0 0 1 1 1 1 1 1 1 0 X X X X 1 1 1 X 0 X X 1 X X X X 0 0 0 X 1 X X X X 0 0 X X 1 X 0 0 0 0 0 1 1 1 1 1 1 1 1 0 X X X 1 X X X X 0 0 0 X X X 1 0 1 1 1 1 0 0 0 0 1 1 1 1 0
Fig.C.52
62
S2 B2 A2 S1 A1 B1 C0 Gnd
16
Vc c B3 A3
74283
S3 A4 B4 S4
C4
OUTPUT INPUT A1 A3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 B1 B3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 C0=0 C2=0 S2 C2 S4 C4 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 1 C0=1 C2=1 S1 S2 S3 S4 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 0 1 0 0 1 1 1 C2 C4 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1
A2 B2 S1 A4 B4 S3 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 1 1 1 1 1 1 1 0
Fig.C.53
L/A (P<Q)IN (P>Q)IN Q7 Q6 Q5
24
Vcc PLE Comparison P7 P6 P5 P4 LOGICAL LOGICAL LOGICAL ARITHMETIC ARITHMETIC ARITHMETIC L/A H H H L L L
Function Table Data Inputs P0-P7, Q0-Q7 P> Q P< Q P= Q P AG Q Q AG P P= Q Input P>Q Input P<Q Output P<Q P>Q L H H ORL L H H ORL
74885 Q4 Q3 Q2 Q1 Q0 Gnd 12 13
P3 P2 P1 P0 (P<Q)OUT (P>Q)OUT
X H X X X L H ORL H ORL H ORL X H X X X L H ORL H ORL H ORL
For P = Q cases, (P > Q) output follows (P > Q) input and (P < Q) output follows (P < Q) input AG : Arithmetically greater than PLE : P Latch Enable L/A : Function select (HIGH for logic operations and LOW for Arithmetic operations
Fig.C.54
63
A3 B2 A2 B1 A1 B0 A0 Vss
16
V DD B3 Co
4008
S3 S2 S1 S0
Ci
Ci 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
A 0 1 0 1 0 1 0 1
Co S 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1 A0 through A3 : Word A input B0 through B3 : Word B input S0 through S3 : Sum output Ci : Carry input C0 : Carry output
Fig.C.55
B0 A0 S3 S2 S1 S0 Cn M F0 F1 F2 V ss
24
VDD A1 B1 A2 B2 A3 A0 through A3 : Word A input (Active LOW) B0 through B3 : Word B input (Active LOW) S0 through S3 : Function select inputs Cn : Carry IN, Cn+4 :Ripple Carry OUT M : Mode control G, P : Look ahead carry outputs F0 through F3 : Function outputs (Active LOW)
40181 B3 G Cn+4 P A=B 12 13 F3
Fig.C.56
64
G1 P1 G0 P0
16
VDD P2 G2 Cn
40182 G3 P3 P V ss 8 9 Cn+x Cn+y G Cn+z
G0 through G3 : Active LOW Carry Generate inputs P0 through P3 : Ac tive LOW Carry propagate inputs Cn : Active HIGH Carry input Cn + x, Cn + y, Cn + z :Active HIGH c arry outputs G : Active LOW group carry generate input P : Active LOW group carry propagate input
Fig.C.57
B2 A2 (A = B) OUT (A > B) IN
16
VDD A3 B3 (A > B) OUT A0 - A3: Word A inputs B0 - B3: Word B inputs
4585 (A < B) IN (A = B) IN A1 Vss 8 9 (A < B) OUT B0 A0 B1
Fig.C.58
2S 1S 1 Cout 1Cin
16
VCC 1S 2S 2Cout nA, nB : Data inputs n Cin : Carry input nS, nS : Data outputs S0, S1 : Mode selects
10180 1A 1B S0 VEE 8 9 2Cin 2A 2B S1
Fig.C.59
65
Vcc1 F0 F1 GG Cn+4 F3 F2 PG B3 A3 B2 VEE
24
Vcc2 M Cn A0 B0 B1
A0 through A3 : Word A inputs B0 through B3 : Word B inputs Cn : Carry input F0 through F3 : Word F inputs GG : Group generate output Cn + 4 : Carry output M : mode Select S0 through S3 : Function Selects
10181
A1 S1 A2 S2 S0
12 13
S3
S3 S2 S1 S0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
M=1 A A+B A+B Logical '1' AB B A+B A+B AB A+B B A+B Logical '0' AB AB A
M = 0, Cn = 0 A A Plus A B A Plus AB A time s 2 (A+B) Plus 0 (A + B) plus (AB) A Plus B A plus (A + B) (A+B) plus 0 A minus B minus 1 (A + B) plus (AB) A plus (A + B) minus 1 A B minus 1 AB minus 1 A minus 1
Fig.C.60
66
14. Pin connection diagrams and other relevant application information on flip flops and related devices
Figs.C.61 to C.84 give the pin connection diagram and other application relevant information of some of the popular flip flops and related devices. (Flip Flops and related devices are discussed in detail in chapter-10 of the book).
Clk(1) Clr(1) 1K VCC Clk(2) Clr(2) 2J
14
1J 1Q 1Q
J K Clk Clr Q, Q Q0 : J-Input : K-input : Clock Input : Clear Input (Active LOW) : Outputs : Q-Output prior to the occurrence of clock's negative going edge 7473 is available in two triggering schemes (i) Negative Edge Triggered (ii) Master Slave Type
Clk 0 1 1 1 1 1
Clr X 1
J X 0 1 0 1 X
M/S
K X 0 0 1 1 X
Q 0 Q0 1 0 Q0 Q 0 Q0 1 0
Q 1 Q0 0 1 Q0 Q 1 Q0 0 1
Toggle
7473
Gnd 2K 2Q
2Q
Clr 0 1 1 1 1
Clk X
J X 0 1 0 1
K X 0 0 1 1
Toggle
Fig.C.61
Dual D-Type Flip-Flop

nD nClk nPR nClr Q, Q : Data Input : Clock Input : Preset Input : Clear Input : Outputs
1Clr 1D 1Clk 1PR 1Q 1Q Gnd
14
VCC 2Clr 2D
7474
2Clk 2PR 2Q
2Q
PR 0 1 0 1 1 1
Clr 1 0 0 1 1 1
Clk X X X 0
D X X X 1 0 X
Q Q 0 1 1 0 Unstable 0 1 1 0 Q0 Q0
Fig.C.62
Dual 2-Bit D-Type Latch
1Q0 1D0 1D1 1G Vcc 2D0 2D1 2Q1
16
1Q0 1Q1 1Q1

nD0, nD1 : Data Inputs nG : Latch Enable Input nQ0 , nQ1, nQ0, nQ1 : Output
7475
2G Gnd 2Q0 2Q0 D 0 1 X G 1 1 0 Q 0 1 Q0 Q 1 0 Q0
2Q1
Q0 = State of Q prior to occurrence of negative going edge at G-input
Fig.C.63
67
Dual Positive Edge Trigger J-K Flip Flop 1CLR 1J 1K 1Clk 1PR 1Q 1Q Gnd 8 9 74109 1 16 Vcc 2CLR 2J : J-Input : K-Input : Preset input 2K (Active LOW) nCLR : Clear input 2Clk (Active LOW) nCLK : Clock Input 2PR nQ, nQ , : Outputs 2Q 2Q nJ nK nPR
Fig.C.64
Monostable Multvibrator (Positive and Negative Edge Triggered) Q NC A1 A2 B Q Gnd 7 8 74121 1 14 VCC NC NC R/CEXT CEXT RINT NC
A1, A2 : Negative going trigger input B : Positive going trigger input RINT : Connection to internal timing resistor CEXT : Connection for external timing capacitor R/C EXT : Connection for common point between external timing capacitor and resistor Q, Q : Outputs
A1 0 X X 1 1 0 X
A2 X 0 X 1 1 X 0
Q 0 0 0 0
Q 1 1 1 1
Fig.C.65
Retriggerable Monostable Multivibrator (Positive an Negative Edge Trigger)
A1 A2 B1 B2 Clr Q Gnd
14
VCC R/CEXT NC
74122
CEXT NC RINT
A1, A2 : Negative going trigger input B : Positive going trigger input RINT : Connection to internal timing resistor CEXT : Connection for external timing capacitor R/CEXT : Connection for common point between external timing capacitor and resistor Q, Q: Outputs
Fig.C.66
68
Dual Retriggerable Monostable Multivibrator (Positive and Negative Edge Triggered) 1A 1B 1Clr 1Q 2Q 2CEXT 2R/CEXT Gnd 8 9 74123 1 16 Vcc 1R/CEXT 1CEXT 1Q 2Q 2Clr 2B 2A nA nB nCEXT : Negative going trigger inputs : Positive going trigger inputs : Connection for external timing capacitor nR/CEXT : Connection for common point between resistor and capacitor nQ, nQ : Outputs
Fig.C.67
6-Bit D-Type Flip-Flop
Clr 1Q 1D 2D 2Q 3D 3Q Gnd
16
Vcc 6Q 6D
74174
5D 5Q 4D 4Q nD nQ Clk Clr : Data Inputs : Data Outputs : Clock (Positive Edge Trigger) : Clear Input (Active LOW)
Clk
Fig.C.68
Dual Monostable Multivibrator (Non-Retriggerable)

nA nB nCext : Negative going trigger input : Positive going trigger input : Connection for external timing capacitor nR/Cext : Connection for common point between external timing resistor and capacitor nQ, nQ : Outputs
1A 1B 1Clr 1Q 2Q 2Cext 2R/Cext Gnd
16
Vcc 1R/Cext 1Cext
74221
1Q 2Q 2Clr 2B
2A
Fig.C.69
69
4-Bit D-Type Flip-Flop (Complementary Outputs)
Clr 1Q 1Q 1D 2D 2Q 2Q Gnd
16
Vcc 4Q 4Q 4D
nD : Data Inputs nQ, nQ : Data Outputs CLK : Clock (Positive Edge Trigger) CLR : Clear Input (Active LOW)
74175
3D 3Q 3Q
Clk
Fig.C.70
Dual 4-Bit Addressable D-Type Latch A0 A1 1D 1Q0 1Q1 1Q2 1Q3 Gnd 8 9 74256 2D3 2Q2 2Q1 2Q0 Memory Addressable Latch output Demultiplex 1 16 Vcc Clr EI 2D MODE CLEAR
nD : Data Inputs nQ0 through nQ3 :Data outputs (Active HIGH) A0, A1 : Data Output Selects Clr : Clear Control (Active LOW) EI : Latch Control (Active LOW)
Fig.C.71
8-bit D-Type Flip Flop
Clr Q0 D0 D1 Q1 Q2 D2 D3 Q3 Gnd
20
Vcc Q7 D7 Q6 D6
D0 through D7 : Data inputs Q0 through Q7 : Data outputs CLK : Clock input (Positive Edge) Clr : Clear Input (Active LOW)
74273
Q5 D5 Q4 D4
10
11
Clk
Fig.C.72
70
Octal D-Type Latch
OE Q0 D0 D1 Q1 Q2 D2 D3 Q3 Gnd
20
Vcc Q7 D7 D6 Q6
D0 through D7 : Data inputs Q0 through Q7 : Data outputs G : Latch Enable (Active LOW) OE : 3-state output enable (Active LOW)
74373
Q5 D5 D4 Q4
10
11
Fig.C.73
OE Q0 D0 D1 Q1 Q2 D2 D3 Q3 Gnd
20
Vcc Q7 D7 D6 Q6
D0 through D7 : Data inputs Q0 through Q7 : Data outputs Clk : Clock input (Positive Edge) OE : 3-state output enable
74374
Q5 D5 D4 Q4
10
11
Clk
Fig.C.74
Clr Q0 D0 D1 Q1 Q2 D2 D3 Q3 Gnd
20
Vcc Q7 D7 Q6 D6
nS : SET input nR : RESET input nD : Data input nCLK : Clock nQ, nQ : Data outputs
4013
Q5 D5 Q4 D4
10
11
Clk
R = S = 1 is invalid
Fig.C.75
71
DualJ-K Flip-Flop
2Q 2Q 2CLK 2RST 2K 2J 2SET VSS
16
VDD 1Q 1Q 1CLK
nJ, nK : J-K inputs nRST : RESET inputs nQ, nQ : Outputs
nSET : SET inputs nCLK : Clock
4027 1RST 1K 1J 8 9 1SET Toggle Invalid No change
Fig.C.76
Dual Monostable Multivibrator
Cx (1) Rx Cx (1) RST (1) +TR (1)
16
VDD Cx (2) Rx Cx (2) RST (2)

nCx : External Capacitor nRx-Cx : Common point of external R and C nRST : Reset(Active LOW) (n) + TR : Positive edge trigger input (n) - TR : Negative edgetrigger input nQ, nQ : Output
4098 TR (1) Q1 Q1 VSS 8 9 +TR (2) TR (2) Q2 Q2
Fig.C.77
Clear Q1 D1 D2 Q2 D3 Q3 VSS
16
VDD Q6 D6
nD : Data inputs nQ : Outputs Clear : Clear input (Active LOW)
40174
D5 Q5 D4 Q4
Clock
Fig.C.78
72
Quad D-Type Flip Flop Clear Q1 Q1 D1 D2 Q2 Q2 VSS 8 9 40175
16
VDD Q4 Q4 D4 D3 Q3 Q3 Clock
nD : Data inputs nQ : True Outputs nQ : Inverted outputs Clear : Clear input (Active LOW)
Fig.C.79
Dual Precision Monostable Multivibrator
Cx (1) Rx Cx (1) RST (1) +TR (1) TR (1) Q1 Q1 VSS
16
VDD Cx (2) Rx Cx (2) RST (2)
4538
+TR (2) TR (2) Q2 Q2
Fig.C.80
Dual J-K Flip Flop VCC1 1Q 1Q 1R 1S 1K 1J VEE 8 9 10135 2R 2S 2K 2J CLK 1 16 VCC 2 2Q

nR nS nJ, nK nQ, nQ C : R input (RESET) : S input (SET) : J, K inputs : Data outputs : Clock input
Fig.C.81
73
Quad D-Type Latch VCC1 1Q 1D 2G 1G 2Q 2D VEE 8 9 10168 1 16 VCC2 4Q 4D LE 3G 3Q 4G 3D
nD : Data inputs nQ : Data outputs nG : Output Enable LE : Latch Enable G 1 0 0 0 LE X 0 1 1 D X X 0 1 Q 0 Q0 0 1
Fig.C.82
Hex D-Type Flip Flop VCC1 1Q 2Q 3Q 1D 2D 3D VEE 8 9 10176 1 16 VCC2 6Q 5Q 4Q 6D 5D 4D CLK
nD : Data inputs nQ : Data outputs CLK : Clock input (Postive edge trigger) CLK 0 Q Q0 D
Fig.C.83
Hex D-Type Flip Flop RST Q0 Q1 Q2 10186 D0 D1 D2 VEE 8 9 D5 D4 D3 CLK 1 16 VCC Q5 Q4 Q3

nD : Data inputs nQ : Data outputs CLK : Clock input (Postive edge trigger) RST : RESET input RST 1 0 0 CLK X 0 Qn 0 Dn Qn
Fig.C.84
74
15. Pin connection diagrams and other relevant application information on counters
Figs.C.85 to C.100 give the pin connection diagram and other application relevant information of some of the popular counter devices. (Counters are discussed in detail in chapter-11 of the book).
BCD Counter (Decade)
Inputs B R01 R02 NC VCC R91 R92
16
Input A NC QA R01 R02 R19 R92 1 1 X X 0 0 1 1 X 0 X X 0 0 X 1 X 0 X 0 X 0 1 0 X 0 X QD 0 0 1 QC QB QA 0 0 0 Count Count Count Count 0 0 0 0 0 1
7490
QD Gnd QB
QC
Input A, B : Inputs QA through QD : Outputs R01, R02 : Reset to '0' inputs R91, R92 : Reset to '9' inputs
Fig.C.85
4-Bit Binary Counter
Input B R01 R02 NC VCC R91 R91
16
Input A NC QA
Input A, B : Inputs QA through QD : Outputs R01, R02 : Reset to '0' inputs
7493
QD Gnd QB
R01 R02 1 0 X 1 X 0
QD 0
QC QB QA 0 Count Count 0 0
QC
Fig.C.86
75
4-Bit Counter D0 through D3 : Preset Data Inputs Q0 throughQ3 : Data Outputs RCO : Ripple Carry Output Clk : Clock Input (Positive Edge Triggered) LOAD : Preset Control (Synchronous, Active LOW) Clr : Clear Input (Asynchronous, Active LOW) for74160 and synchronous, Active LOW for 74162 ENP : Count Enable Parallel ENT : Count Enable Trickle
Clr Clk D0 D1 D2 D3 ENP Gnd
16
VCC RCO Q0
74160/ 74162
Q1 Q2 Q3 ENT
LOAD
74160 Clk Clr ENP X X X X 0 1 1 1 1 1 X 1 0 0 X 1 ENT X 0 1 0 X 1 LOAD X 1 1 1 0 1 74162 Clk Clr ENP 0 X X X 1 1 1 1 1 X 1 0 0 X 1 ENT X 0 1 0 X 1 LOAD X 1 1 1 0 1 Clear Count/RCO Disabled Count Disabled Count/RCO Disabled LOAD COUNT Function Function Clear Count/RCO Disabled Count Disabled Count/RCO Disabled LOAD COUNT
Fig.C.87
76
4-Bit Binary Up-Counter Clr Clk D0 D1 D2 D3 ENP Gnd 8 9 74161/ 74163 1 16 VCC RCO Q0 Q1 Q2 Q3 ENT LOAD D0 through D3 : Preset Data Inputs Q0 throughQ3 : Data Outputs RCO : Ripple Carry Output Clk : Clock Input (Positive Edge Triggered) LOAD : Preset Control (Synchronous, Active LOW) Clr : Clear Input (Asynchronous, Active LOW) for74161 and synchronous, Active LOW for 74163 ENP : Count Enable Parallel ENT : Count Enable Trickle
74161 Clk Clr ENP X X 0 1 X 1 ENT X 0 LOAD X 1 Function Clear Count/RCO Disabled Count Disabled LOAD COUNT
1 1 1
0 X 1
1 X 1
1 0 1 74162
Clk Clr ENP 0 X 1 X 1
ENT X 0
LOAD X 1
Function Clear Count/RCO Disabled Count Disabled Count/RCO Disabled LOAD COUNT
X X
1 1
0 0
1 0
1 1
1 1
X 1
X 1
0 1
Fig.C.88
77
Synchronous Up/Down Counter LD 1 1 0 74190/ 74191 RCO 1 Max/Min LD D2 8 9 D3 D0 through D3 : Parallel data inputs Q0 through Q3 : Count outputs CLK : Clock input U/D : Count Up/Down control LD : Parallel Load Control Max/Min : Max/Min count output RCO : Ripple Clock Output 74190 : BCD 74191 : 4-Bit Binary 1 X X No Change EN U/D CLK 0 0 X 0 1 X X Function Count UP Count DOWN Load
D1 Q1 Q0 EN U/D Q2 Q3 Gnd
16
VCC D0 CLK
Fig.C.89
Synchronous Up/Down Counter
D1 Q1 Q0 CK DN CK UP Q2 Q3 Gnd
16
VCC D0 Clr CKUP CKDN 1 1 X X X X Clr 0 0 1 0 LD 1 1 X 0 Function Count UP Count Down Clear Load D0 through D3 : Parallel data inputs Q0 through Q3 : Count outputs CK UP : Up-Count clock input CK DN : Down-Count clock input LD : Parallel load control Clr : Clear input CRY : Carry input BRW : Borrow output 74192 : BCD 74193 : 4-Bit Binary
74192/ 74193
BRW CRY LD D2
D3
Fig.C.90
78
BCD Counter (Divide-by-2/Divide-by-5) CKA : Clock for section A, CKB : Clock for section B, C, D, QA through QD : Outputs R01, R02 : Reset-to-0 Inputs R91, R92 : Reset-to-9 Inputs CKA, CKB : Negative edge Triggered
R91 NC R92 QC QB NC Gnd
14
VCC R02 R01
R01 R02 R91 R92 1 1 X 1 1 X 0 X X 0 0 X 1 X 0 X 0 X 0 1 0 X 0 X
QD 0 0 1
QC 0 0 0 Count Count Count Count
QB QA 0 0 0 0 0 1
74290
CKB CKA QA
X 0 0 X
QD
Fig.C.91
NC NC NC QC QB NC Gnd
14
VCC R02 R01
CKA : Clock for section A, CKB : Clock for section B, C, D QA through QD : Outputs R01, R02 : Reset-to-0 Inputs R91, R92 : Reset-to-9 Inputs CKA, CKB : Negative edge Triggered R01 R02 1 0 X 1 X 0 QD 0 Count Count QC QB QA 0 0 0
74293
CKB CKA QA
QD
Fig.C.92
Decade Counter Count Sequence Table 5 1 0 2 4017 6 7 3 VSS 8 9 1 16 VDD RST Clk CI CO 9 4 8 Clk : Clock 0 through 9 : Decimal outputs RST : Reset C : Clock Inhibit CO : Carry Out Function Table RST CE Clk Function 1 0 0 X 0 1 X Reset to '0' Count Count 0 1 2 3 4 5 6 7 8 9 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 CO 1 1 1 1 1 0 0 0 0 0
Fig.C.93
79
Synchronous Programmable 4-Bit Counter Clear Clock P1 P2 P3 P4 PE VSS 8 9 40160/ 40161/ 40162/ 40163 1 16 VDD Carry Out Q1 Q2 Q3 CP TE LOAD
40160 : Decade with Asynchronous Clear 40161 : Binary with Asynchronous Clear 40162 : Decade with Synchronous Claear
Fig.C.94
Presettable 4-Bit UP/DOWN Counter J2 Q2 Q1 Clock DOWN Clock UP Q3 Q4 VSS 8 9 40192/ 40193 1 16 VDD J1 RESET BORROW CARRY PRESET ENBALE J3 J4
40192 : BCD Counter 40193 : Binary Counter
Fig.C.95
80
Presettable UP/DOWN Counter
Enable /Preset Q4 P4 P1 CI Q1 CO VSS
16
VDD Clk Q3
4510/ 4516
P3 P2 Q2 U/D
P1 through P4 : preset inputs Q1 through Q4 : outputs RST : Reset input Clk : Clock input CI : Carry IN CO : Carry OUT NOTE 4510 in a BCD-counter while 4516 is a 4-bit binary counter
RST
Fig.C.96
Dual UP Counter
Clka ENABA Q1A Q2A Q3A Q4A RSTA VSS
16
VDD RSTB Q4B
RSTA, RSTB : RESET (Active HIGH) Clka, Clkb : Clock input (Positive edge trigger) Q1A-Q4A, Q1B-Q4B :Output ENABA, ENABB : Enable input 4518 : Dual BCDUP-counter 4520 : Dual Binary UP-counter
4518/ 4520
Q3B Q2B Q1B ENABB
ClkB
Fig.C.97
4-Bit Counter (10136/10137) D0 through D3 : Preset data inputs Q0 through Q3 : Data outputs Cin : Carry input S0, S1 : Mode controls Clk : Clock input Cout : Carry output
VCC1 Q2 Q3 Cout D3 D2 S1 VSS
16
VCC2 Q1 Q0
Cin S0 X 0 1 0 1 0 0 0 1 1 1
S1 0 1 1 0 0 1
MODE Load Count UP Hold Count Count DOWN Hold Count Stop Count
10136/ 10137
Clk D0 D1 Cin
S0
Fig.C.98
81
4-Bit Binary Counter
VCC1 Q3 Q3 Q2
16
VCC2 Q0 Q0 Q1
10154 S3 S2 S1 VEE 8 9 Clk1 S0 Clk2 RST
S0 through S3 : SET inputs RST : RESET input Clk0 : Clock for section 0 Clk 1 : Clock for sections 1,2 and 3 Q0 through Q3 : Active HIGH count outputs Q0, Q3 : Active LOW outputs RST = S = 1 is invalid
RST 0 0 1
S Clk 0 1 0 X X
Q Count 1 0
Fig.C.99
4-Bit Binary Counter VCC1 Q3 Q3 Q2 10178 S3 S2 S1 VEE 8 9 Clk1 S0 Clk2 RST 1 16 VCC2 Q0 Q0 Q1
S0 through S3 : SET inputs RST : RESET input Clk0 : Clock for section 0 Clk 1 : Clock for sections 1,2 and 3 Q0 through Q3 : Active HIGH count outputs Q0, Q3 : Active LOW outputs
Fig.C.100
82
16. Pin connection diagrams and other relevant application information on shift registers
Figs.C.101 to C.105 give the pin connection diagram and other application relevant information of some of the popular shift register devices. (Shift Registers are discussed in detail in chapter-11 of the book).
8-Bit SIPO Shift Register Clr SIA SIB 0 1 QA QB QC QD Gnd 7 8 74164 Q6 QF QE Clr Clk SIA, SIB :Serial Inputs QA through Q4 : Data Outputs Clk : Clock Input Clr : Clear Input 1 1 X 1 0 X X 1 0 X Clk X QA QB QC QD QE QF 0 0 0 0 0 0 QG QH 0 0
SIA SIB
14
VCC Q4
1 QAN QBN QCN QDN QEN QFN Q0 0 Q00 Q10 Q20 Q30 Q40 Q50 Q60 0 Q00 Q10 Q20 Q30 Q40 Q50 Q60
Fig.C.101
8-Bit Shift Register (Serial/Parallel in/Serial OUT) Inputs Clr S/L CKIN Clk SI D0 D1 D2 74166 D3 CKIN Clk Gnd 8 9 D6 D5 D4 CLR S/L Q7 D7 0 1 1 1 1 X X 1 1 X X L 0 0 1 X L X X 1 0 X Internal Q0 0 D0 1 0 Q6 0 D6 Q50 Q50 Output Q7 0 D7 Q60 Q60 Q70
SI
16
VCC
Q00 Q60
D0 through D7 : Parallel inputs SI : Serial input CLK : Clock Q7 :Data Output S/L : Shift/Parallel-load Control CKIN : Clock Inhibit
Fig.C.102
83
4-Bit Universal Shift Register
D1 D0 SI Q0 Clk Q1 GND
14
VCC D2 D3
Shift 0 0 1
Load 0 1 X X
Clk
SI X X 1 0
Q0
Q1
Q2
Q3
Q00 Q10 Q20 Q30 D0 1 0 D1 D2 D3
74178
Q00 Q10 Q20 Q00 Q10 Q20
Shift Q3 Load
Q2
D0 through D3 : Parallel inputs SI : Serial input Q0 through Q3 : Data Outputs Load : Parallel Load Control Shift : Serial Shift Control Clk : Clock Input
Fig.C.103
8-Bit Shift Register P7 Q5 Q7 P3 4021 P2 P1 P0 VSS 8 9 1 16 VDD P6 P5 P4 Clk P/S Q6 X S Clk P/S 1 0 Parallel in Shift right Function P0 through P7 : Parallel Data input Clk : Clock P/S : Parallel/Serial Select Q5, Q6, Q7 : Data output
Fig.C.104
4-Bit Bidirectional universal Shift Register RESET Shift R ight D0 Parallel Data Inputs D1 40194 D2 D3 Shift Left VSS 8 9 1 16 VDD Q0 Q1 Q2 Q3 Clock S1 S0 Select Inputs Parallel Outputs
Fig.C.105
84
17. Pin connection diagrams and other relevant application information on microprocessors and peripheral devices
Figs.C.106 to C.126 give the pin connection diagram and other application relevant information of some of the popular microprocessors. (Microprocessors and peripheral devices are discussed in detail in chapter-13 of the book).
8 bit microprocessor
X1 X2 RESET OUT SOD SID TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD 7 GND 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vcc HOLD HLDA CLK(OUT) RESET IN READY 10/M S1 RD WR ALE S0 A15 A14 A13 A12 A11 A10 A9 A8
24
8085
Fig.C.106
VSS HALT f1 IRQ VMA NMI BA VCC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 RESET TSC N.C. f2 DBE N.C. R/W D0 D1 D2 D3 D4 D5 D6 D7 A15 A14 A13 A12 VSS
6800
31 30 29 28 27 26 25 24 23 22 21
Fig.C.107
85
A11 A12 A13 A14 A15 CLK D4 D3 D5 D6 Vcc D2 D7 D0 D1 INT NMI HALT MREQ IQRQ 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
24
Z80
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 GND REFSH MI RESET BUSRQ WAIT BUSAK WR RD
Fig.C.108
GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32
VCC AD15 A16 /S3 A17 /S4 A18/S5 A19/S6 BHE/S7 MN/MX RD RQ/GT0 (HOLD) RQ/GT1 (HLDA) LOCK (WR) S2 (M/IO) S1 (DT/R) S0 (DEN) QS0 (ALE) Qs1 (INTA) TEST READY RESET
8086
31 30 29 28 27 26 25 24 23 22 21
Fig.C.109
86
16-Bit Microprocessor
S0 S1 S2 ARDY CLKOUT RESET X2 X1 Vss ALE/QS0 RD/QSMD WR/QS1 (S7)BHE A19/S6 A18/S5 A17/S4 A16/S3
1
PIN NO.1 MARK
AD15 (A15) AD7 AD14 (A14) AD6 AD13 (A13) AD5 AD12 (A12) Ad4 Vcc AD11 (A11) AD3 AD10 (A10) AD2 AD9 (A9) AD1 AD8 (A8) AD0
80186
HLDA HOLD SRDY LOCK TEST NMI INT0 INT1 Vcc INT2/INTA0 INT3/INTA1 DT/R DEN MCS0 MCS1 MCS2 MCS3
35
18
UCS LCS PCS6/A2 PCS5/A1 PCS4 PCS3 PCS2 PCS1 Vss PCS0 RES TMR OUT1 TMR OUT0 TMR IN1 TMR IN0 DRQ1 DRQ0
Fig.C.110
87
ERROR D15 D14 D13 D12 D10 D11 Vss D0
35 36 33 31 29 34 32 30 28 26 24 22 20 18
D9 D2
39 40
D7
D6
D5
D4
D3
51
49 50
47 48
45 46
43 44
41 42
CAP BUSY NC NC Vss Vcc HOLD COD/INTA LOCK
D1
37 38
D8
ERROR NC INTR NMI PEREQ READY HLDA M/IO NC
52 54 56 58 60 62 64 66 68
53 55 57 59 61 63 65 67 2 1
D0 A1 CLK RESET A4 A6 A8 A10 A12
A0 A2 Vcc A3 A5 A7 A9 A11 A13
80286
27 25 23 21
4 3
6 5
8 7
10 9
12 11
14 13
16 15
19 17
Pin 1 Indicator
A22
A21
A19
A17
A15 A16
BHE
PEACK
A23
A20
A18
Fig.C.111
88
A14
Vss
NC
S0
A12
NC
SI
D4 D3 D2 D1 D0 AS UDS LDS R/W DTACK BG BGACK BR Vcc CLK GND HALT RESET VMA E VPA BERR IPL2 IPL1 IPL0 FC2 FC1 FC0 A1 A2 A3 A4 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
21 22 23 24 25 26 27 28 29 30 31 32
24
68000
DIP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40
39 38 37 36 35 34 33
D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 GND A23 A22 A21 Vcc A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5
9 10
61 LLCC Function 60
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 D4 D3 D2 D1 D0 AS UDS LDS R/W DTACK BG BGACK BR Vcc CLK GND GND NC HALT RESET VMA E VPA BERR IPL2 IPL1 IPL0 FC2 FC1 FC0 NC A1 A2 A3
LLCC Function
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 Vcc A21 A22 A23 GND GND D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5
68000
LLCC
26
44
27
43
Fig.C.112
89
P N M L K J G F E D C B A
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A30
A27
A26
A23 A21
A20
A17
A16
A15
A14
A11
A8
VSS
VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
VCC
A31
A29
A24
A22 VSS
A18 VCC
VSS
A13
A10
A7
A5
VSS
D30 D29 D26 VSS D24 VCC
VSS VCC D27 D25 VCC D23
VCC VSS D31 D28 VCC VSS
A28
A25 VSS
A19 VCC
VSS
A12
A9
A6 A2 VCC NC
A4 NC VSS NC INTR
A3 NC VCC VSS VCC
Intel 386DX PGA Top side
NC PEREO RESET LOCK# VSS
NMI ERROR# BUSY# W/R# VSS NC VSS VCC D/C# M/IO#
D22 D19 D18 D14
D21 D17 D16 D12
D20 VSS D15 D10 VCC D7 VSS D0 VCC CLK2 BC0# VCC
VCC
D13
D11
VCC
D8
D5
VSS
D1 READY# NC
NC
NA#
BE1#
BE2#
BE3#
VSS
D9
HLDA D6
D4
D3
D2
VCC
VSS ADS# HOLD BS16#
VSS
VCC
Intel 386DX PGA Pinout functional grouping
Signal/Pin
Signal/Pin
Signal/Pin
Signal/Pin
Signal/Pin
Signal/Pin
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23
C4 A3 B3 B2 C3 C2 C1 D3 D2 D1 E3 E2 E1 F1 G1 H1 H2 H3 J1 K1 K2 L1
A24 A25 A26 A27 A28 A29 A30 A31 ADS# BE0# BE1# BE2# BE3# BS16# BUSY# CLK2 D0 D1 D2 D3 D4 D5
L2 K3 M1 N1 L3 M2 P1 N2 E14 E12 C13 B13 A13 C14 B9 F12 H12 H13 H14 J14 K14 K13
D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27
L14 K12 L13 N14 M12 N13 N12 P13 P12 M11 N11 N10 P11 P10 M9 N9 P9 N8 P7 N6 P5 N5
D28 D29 D30 D31 D/C# ERROR# HLDA HOLD INTR LOCK# M/IO# NA# NMI PEREQ READY# RESET Vcc
M6 P4 P3 M5 A11 A8 M14 D14 B7 C10 A12 D13 B8 C8 G13 C9 A1 A5 A7 A10 A14 C5
Vcc
Vss
C12 D12 G2 G3 G12 G14 L12 M3 M7 M13 N4 N7 P2 P8 A2 A6 A9 B1 B5 B11 B14 C11
Vss
W/R# N.C.
F2 F3 F14 J2 J3 J12 J13 M4 M8 M10 N3 P6 P14 B10 A4 B4 B6 B12 C6 C7 E13 F13
Fig.C.113
90
D1 D2 Vss Vcc D3 D4 D5 D6 D7 Vcc D8 D9 D10 D11 D12 Vss Vcc D13 D14 D15 A23 A22 Vss Vss A21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
D0 Vss HLDA HOLD Vss NA# READY# Vcc Vcc Vcc Vss Vss Vss Vss CLK2 ADS# BHE# A1 BHE# NC Vcc Vss M/IO# D/C# W/R#
Intel 386SX TOP VIEW
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A20 A19 A18 A17 Vcc A16 Vcc Vss Vss A15 A14 A13 Vss A12 A11 A10 A9 A8 Vcc A7 A6 A5 A4 A3 A2
Address
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 18 51 52 53 54 55 56 58 59 60 61 62 64 65 66 70 72 73 74 75 76 79 80
LOCK# NC FLT# NC NC NC Vcc RESET BUSY# Vss ERROR# PEREQ NMI Vcc INTR Vss Vcc NC NC NC NC NC Vcc Vss Vss
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Data
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 1 100 99 96 95 94 93 92 90 89 88 87 86 83 82 81
Control
ADS# BHE# BLE# BUSY# CLK2 D/C# ERROR# FLT# HLDA HOLD INTR LOCK# M/IO# NA# NMI PEREQ READY# RESET W/R# 16 19 17 34 15 24 36 28 3 4 40 26 23 6 38 37 7 33 25
N/C
20 27 29 30 31 43 44 45 46 47
Vcc
8 9 10 21. 32 39 42 48 57 69 71 84 91 97
Vss
2 5 11 12 13 13 22 35 41 49 50 63 67 68 77 78 85 98
Fig.C.114
91
32-Bit Microprocessorr
Fig.C.115
92
17 Vcc GND BR A0 A1 A31 A30 GND A29 A28 A27 A26 Vcc A25 A24 A23 A22 GND A21 A20 A19 A18 A17 A16 A15 A14 GND A13 A12 A11 A10 Vcc NC
BGACK BG C OUT OCS RMC FC0 GND FC1 FC2 Vcc AVEC CLK GND Vcc DSACK0 GND GND DSACK1 STERM BERR HALT Vcc CBACK CDREO AS DS GND C IN DBEN SIZ0 SIZ1 ECS R/W 10 5 1 125 117 110 25 105 30
MC68030FE CQUAD 132 (TOP VIEW)

35
100
95 40
90 45
50
55
60
65
70
75
80
83
Vcc Vcc D31 D30 D29 D28 GND D27 D26 D25 D24 Vcc D23 D22 D21 D20 GND D19 D18 D17 D16 GND D15 D14 D13 D12 GND D11 D10 D9 D8 Vcc NC
93
A9 A8 A7 A6 A5 A4 GND A3 A2 GND NC IPEND Vcc RESET NC GND GND IPL2 IPL1 IPL0 CDIS Vcc REFILL STATUS D0 D1 GND D2 D3 D4 D5 D6 D7
Fig.C.116
Fig.C.117
94
Programmable Timer/Counter
D7 D6 D5 D4 D3 D2 D1 D0 CLK0 OUT0 GATE0 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC WR RD CS A1 A0 CLK2 OUT2 GATE2 CLK1 GATE1 OUT1
8254
Fig.C.118
Programmable Peripheral Interface

PA3 PA2 PA1 PA0 RD CS GND A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 24 40 39 38 37 36 35 34 33 32 8255A 31 30 29 28 27 26 25 24 23 22 21 PA4 PA5 PA6 PA7 WR RESET D0 D1 D2 D3 D4 D5 D6 D7 Vcc PB7 PB6 PB5 PB4 PB3
Fig.C.119
95
Programmable Interrupt Controller

CS WR RD D7 D6 D5 D4 D3 D2 D1 D0 CAS0 CAS1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 UM8259A-2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A0 INTA IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0 INT SP/EN CAS2
Fig.C.120
DMA Controller I/OR I/OW MEMR MEMW MARK READY HLDA ADSTB AEN HRQ CS CLK RESET DACK2 DACK3 DRQ3 DRQ2 DRQ1 DRQ0 GND 1 40 1 24 2 39 3 38 4 37 5 36 6 35 7 34 8 33 9 32 10 8257 31 11 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 A7 A6 A5 A4 TC A3 A2 A1 A0 Vcc D0 D1 D2 D3 D4 DACK0 DACK1 D5 D6 D7
Fig.C.121
96
Programmable Communication Interface
D2 D3 RXD GND D4 D5 D6 D7 TXC_n WR_n CS_n CD_n RD_n RXRDY
1 2 3 4 5 6 7 8 9 10 11 12 13 14 IA8251 28 Pin DIP
28 27 26 25 24 23 22 21 20 19 18 17 16 15
D1 D0 VCC RXC_n DTR_n RTS_n DSR_n RESET CLK TXD TXEMPTY CTS_n SYNDET_BD TXRDY
Fig.C.122
Math Coprocessor
S1 S0 COD/INTA N.C. D15 D14 D13 D12 V cc V ss D11 D10 N.C. D9 D8 D7 D6 D5 D4 D3 40 1 1 24 39 2 38 3 37 4 36 5 35 6 34 7 33 8 32 9 10 M80287 31 30 11 29 12 13 28 14 27 26 15 16 25 17 24 23 18 19 22 20 21 READY CKM HLDA CLK286 PEACK RESET NPS1 NPS2 CLK CMD1 Vss CMD0 NPWR NPRD ERROR BUSY PEREQ D0 D1 D2
Fig.C.123
97
Programmable Keyboard/ Display Interface

RL 2 RL 3 CLK IRQ RL 4 RL 5 RL 6 RL 7 RESET RD WR DB 0 DB 1 DB 2 DB 3 DB 4 DB 5 DB 6 DB 7 V ss 1 40 1 24 2 39 3 38 4 37 5 36 6 35 7 34 8 33 9 32 10 31 8279 11 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 VCC RL 1 RL 0 CNTL/STB SHIFT SL 3 SL 2 SL 1 SL 0 OUT B 0 OUT B 1 OUT B 2 OUT B 3 OUT A 0 OUT A 1 OUT A 2 OUT A 3 BD CS A0
Fig.C.124
Clock Generator
1 2 3 4 5 6 7 8 9 SAB 82284
ARDY SRDY SRDYEN READY EFI F/C X1 X2 GND
18 17 16 15 14 13 12 11 10
Vcc ARDYEN S1 S0 N.C. PCLK RESET RES CLK
Fig.C.125
98
Octal Bus Transceiver

A0 A1 A2 A3 A4 A5 A6 A7 OE GND 1 2 3 4 5 6 7 8 9 10 SAB 8286A 20 19 18 17 16 15 14 13 12 11 Vcc B0 B1 B2 B3 B4 B5 B6 B7 T
Fig.C.126
99
18. Pin connection diagrams and other relevant application information on microcontrollers
Figs.C.127 to C.137 give the pin connection diagram and other application relevant information of some of the popular microcontrollers. (Microcontrollers are discussed in detail in chapter-14 of the book).
8-bit Microcontroller
T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/3.7 XTAL2 XTAL1 VSS 1 1 24 2 3 4 5 6 7 8 80C51 9 DUAL 10 IN LINE 11 PACKAGE 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP ALE PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8
Fig.C.127
100
6 1 40
39
80C51 LCC 17 29
18 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function NIC* P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST P3.0/RxD NIC* P3.1/RxD P3.2/INT0 P3.3/INT1 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
28 Function P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS NIC* P2.0/A8 P1.1/A9 P2.2/A10 P3.3/A11 P4.4/A12 P5.5/A13 P6.6/A14 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P2.7/A15 PSEN ALE NIC* EA/VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC
*NO INTERNAL CONNECTION
Fig.C.128
101
44 34
1 80C51 PQFP 11
33
23
12 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function P1.5 P2.6 P3.7 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
22 Function VSS NIC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE NIC* EA/VPP P0.7/AD7 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC NIC* P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4
*NO INTERNAL CONNECTION
Fig.C.129
102
EXTAL STRB/R/W E STRA/AS MODA/LIR MODB/VSTBY VSS VRH VRL PE7/AN7 PE3/AN3 PE6/AN6 PE2/AN2 XTAL PC0/ADDR0/DATA0 PC1/ADDR1/DATA1 PC2/ADDR2/DATA2 PC3/ADDR3/DATA3 PC4/ADDR4/DATA4 PC5/ADDR5/DATA5 PC6/ADDR6/DATA6 PC7/ADDR7/DATA7 RESET *XIRQ/VPPE IRQ PD0/RxD 8 9 10 11 12 13 14 15 16 17 18 19 20 7 6 5 4 3 2 1 1 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
M68HC11 E SERIES PLCC and CLCC Package
PE5/AN5 PE1/AN1 PE4/AN4 PE0/AN0 PB0/ADDR8 PB1/ADDR9 PB2/ADDR10 PB3/ADDR11 PB4/ADDR12 PB5/ADDR13 PB6/ADDR14 PB7/ADDR15 PA0/IC3
103
PD1/TxD PD2/MISO PD3/MOSI PD4/SCK PD5/SS VDD PA7/PAI/OC1 PA6/OC2/OC1 PA5/OC3/OC1 PA4/OC4/OC1 PA3/OC5/IC4/OC1 PA2/IC1 PA1/IC2
21 22 23 24 25 26 27 28 29 30 31 32 33
Fig.C.130
PA1/IC2 PA2/IC1 PA3/OC5/IC4/OC1 NC NC PA4/OC4/OC1 PA5/OC3/OC1 PA6/OC2/OC1 PA7/PAI/O C1 VDD PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TxD VSS
PA0/IC3 NC NC NC PB7/ADDR15 PB6/ADDR14 PB5/ADDR13 PB4/ADDR12 PB3/ADDR11 PB2/ADDR10 PB1/ADDR9 PB0/ADDR18 PE0/AN0 PE4/AN4 PE1/AN1 PE5/AN5
M68HC11 E SERIES QFP Package
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
NC PD0/RxD IRQ XIRQ/VPPE(1) NC RESET PC7/ADDR7/DATA7 PC6/ADDR6/DATA6 PC5/ADDR5/DATA5 PC4/ADDR4/DATA4 PC3/ADDR3/DATA3 PC2/ADDR2/DATA2 PC1/ADDR1/DATA1 NC PC0/ADDR0/DATA0 XTAL
104
PE2/AN2 PE6/AN6 PE3/AN3 PE7/AN7 VRL VRH VSS VSS MODB/VSTBY NC MODA/LIR STRA/AS E STRB/R/W EXTAL NC
Fig.C.131
PA1/IC2 PA2/IC1 PA3/OC5/IC4/OC1 PA4/OC4/OC1 PA5/OC3/OC1 PA6/OC2/OC1 PA7/PAI/OC1 VDD PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TxD
PA0/IC3 PB7/ADDR15 PB6/ADDR14 PB5/ADDR13 PB4/ADDR12 PB3/ADDR11 PB2/ADDR10 PB1/ADDR9 PB0/ADDR8 PE0/AN0 PE4/AN4 PE1/AN1 PE5/AN5
M68HC11 E SERIES TQFP Package
39 38 37 36 35 34 33 32 31 30 29 28 27
PD0/RxD IRQ XIRQ/VPPE(1) RESET PC7/ADDR7/DATA7 PC6/ADDR6/DATA6 PC5/ADDR5/DATA5 PC4/ADDR4/DATA4 PC3/ADDR3/DATA3 PC2/ADDR2/DATA2 PC1/ADDR1/DATA1 PC0/ADDR0/DATA0 XTAL
105
PE2/AN2 PE6/AN6 PE3/AN3 PE7/AN7 VRL VRH VSS MODB/VSTBY MODA/LIR STRA/AS E STRB/R/W EXTAL
Fig.C.132
VSS MODB/VSTBY MODA/LIR STRA/AS E ESTRB/R/W EXTAL XTAL PC0/ADDR0/DATA0 PC1/ADDR1/DATA1 PC2/ADDR2/DATA2 PC3/ADDR3/DATA3 PC4/ADDR4/DATA4 PC5/ADDR5/DATA5 PC6/ADDR6/DATA6 PC7/ADDR7/DATA7 RESET *XIRQ/VPPE IRQ PD0/RxD EVSS PD1/TxD PD2/MISO PD3MOSI PD4/SCK PD5/SS VDD VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 24 56 55 54 53 52 51 50 49 48 47 46 45 44 43 M68HC11 E SERIES 42 SDIP 41 40 39 38 37 36 35 34 33 32 31 30 29 EVSS VRH VRL PE7/AN7 PE3/AN3 PE6/AN6 PE2/AN2 PE5/AN5 PE1/AN1 PE4/AN4 PE0/AN0 PB0/ADDR8 PB1/ADDR9 PB2/ADDR10 PB3/ADDR11 PB4/ADDR12 PB5/ADDR13 PB6/ADDR14 PB7/ADDR15 PA0/IC3 PA1/IC2 PA2/IC1 PA3/OC5/IC4/OC1 PA4/OC4/OC1 PA5/OC3/OC1 PA6/OC2/OC1 PA7/PAI/OC1 EVDD
Fig.C.133
106
PA7/PAI/OC1 PA6/OC2/OC1 PA5/OC3/OC1 PA4/OC4/OC1 PA3/OC5/IC4/OCI PA2/IC1 PA1/IC2 PA0/IC3 PB7/ADDR15 PB6/ADDR14 PB5/ADDR13 PB4/ADDR12 PB3/ADDR11 PB2/ADDR10 PB1/ADDR9 PB0/ADDR8 PE0/AN0 PE1/AN1 PE2/AN2 PE3/AN3 VRL VRH VSS MODB/VSTBY 1 24 48 47 2 46 3 45 4 44 5 43 6 42 7 41 8 40 9 39 10 38 11 12 MC68HC811E2 37 DIP 36 13 35 14 34 15 33 16 32 17 31 18 30 19 29 20 28 21 27 22 26 23 25 24 VDD PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TxD PD0/RxD IRQ XIRQ RESET PC7/ADDR7/DATA7 PC6/ADDR6/DATA6 PC5/ADDR5/DATA5 PC4/ADDR4/DATA4 PC3/ADDR3/DATA3 PC2/ADDR2/DATA2 PC1/ADDR1/DATA1 PC0/ADDR0/DATA0 XTAL EXTAL STRB/R/W E STRA/AS MODA/LIR
Fig.C.134
RA2 RA3 RA4/TOCKI MCLR VSS RB0/INT RB1 RB2 RB3
11 2418 2 17 3 16 4 15 5 PIC16C84 14 PDIP, SOIC 6 13 7 12 8 11 9 10
RA1 RA2 OSC1/CLKIN OSC2/CLKOUT VDD RB7 RB6 RB5 RB4
Fig.C.135
107
PW2/PP2 PW1/PP1 PW0/PP0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 PG7 KWG6/PG6 KWG5/PG5 KWG4/PG4 VDD PGUPD VSS IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 KWG3/PG3 KWG2/PG2 KWG1/PG1 KWG0/PG0 SMODN/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4
112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
PP3/PW3 PP4 PP5 PP6 PP7 VDDX VSSX PCAN0/RxCAN PCAN1/TxCAN PCAN2 PCAN3 PCAN4 PCAN5 PCAN6 PCAN7 VFP* PS7/SS PS6/SCK PS5/SDO/MOSI PS4/SDI/MISO PS3/TxD1 PS2/RxD1 PS1/TxD0 PS1/RxD0 VSSA VRL1 VRH1 VDDA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
68HC(9)12D60 112TQFP
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
PAD17/AN17 PAD07/AN07 PAD16/AN16 PAD06/AN06 PAD15/AN15 PAD05/AN05 PAD14/AN14 PAD04/AN04 PAD13/AN13 PAD03/AN03 PAD12/AN12 PAD02/AN02 PAD11/AN11 PAD01/AN01 PAD10/AN10 PAD00/AN00 VRL0 VRH0 VSS VDD PA7/ADDR15/DATA15/DATA7 PA6/ADDR14/DATA14/DATA6 PA5/ADDR13/DATA13/DATA5 PA4/ADDR12/DATA12/DATA4 PA3/ADDR11/DATA11/DATA3 PA2/ADDR10/DATA10/DATA2 PA1/ADDR9/DATA9/DATA1 PA0/ADDR8/DATA8/DATA0
108
ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 KWH7/PH7 KWH6/PH6 KWH5/PH5 KWH4/PH4 ECLK/DBE/CAL/PE7 CGMTST/MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSX PHUPD VDDX VDDPLL XFC VSSPLL RESET EXTAL XTAL KWH3/PH3 KWH2/PH2 KWH1/PH1 KWH0/PH0 LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
Fig.C.136
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PW2/PP2 PW1/PP1 PW0/PP0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 KWG4/PG4 VDD VSS IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 SMODN/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
PP3/PW3 PP4 PP5 PP6 PP7 VDDX VSSX PCAN0/RxCAN PCAN1/TxCAN VFP* PS7/SS PS6/SCK PS5/SDO/MOSI PS4/SDI/MISO PS3/TxD1 PS2/RxD1 PS1/TxD0 PS0/RxD0 VSSAD VDDAD
68HC(9)12D60 80 QFP
PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VRL0 VRH0 VSS VDD PA7/ADDR15/DATA15/DATA7 PA6/ADDR14/DATA14/DATA6 PA5/ADDR13/DATA13/DATA5 PA4/ADDR12/DATA12/DATA4 PA3/ADDR11/DATA11/DATA3 PA2/ADDR10/DATA10/DATA2 PA1/ADDR9/DATA9/DATA1 PA0/ADDR8/DATA8/DATA0
109
ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 KWH4/PH4 ECLK/DBE/CAL/PE7 CGMTST/MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSX VDDX VDDPLL XFC VSSPLL RESET EXTAL XTAL LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Fig.C.137

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Companion Website of the book DIGITAL ELECTRONICS: PRINCIPLES, DEVICES AND APPLICATIONS

Application Relevant Information on DIGITAL INTEGRATED CIRCUITS

1. Numerical index of digital integrated circuits of TTL family

Table C.1 (contd.) Type No.

Table C.1 (contd.) Type No.

Table C.1 (contd.) Type No.

2. Functional index of digital integrated circuits of TTL family

Table C.2 (contd.) Type Number

Table C.3 Arithmetic Circuits belonging to TTL family

3. Numerical index of digital integrated circuits of CMOS logic family

Table C.7 (Contd.)

4. Functional index of digital integrated circuits of CMOS logic family

Table C.9 Arithmetic circuits belonging to CMOS family

Table C.10 Multiplexer and Demultiplexer Circuits belonging to CMOS family

Table C.11 Flip Flops belonging to CMOS family

Table C.12 Counters and Registers belonging to the CMOS family

5. Numerical index of digital integrated circuits of ECL family

Table C.13 (contd.)

6. Functional index of digital integrated circuits of ECL family

Table C.15 Arithmetic Circuits belonging to ECL family

Table C.16 Multiplexers and Demultiplexer Circuits belonging to ECL family

Table C.17 Flip Flops belonging to ECL family

Table C.18 Counters and Registers belonging to ECL family

7. Popular A/D converters

LC2MOS 10 s P-compatible 8-bit A/D converter

Table C.19 (contd.) Type Number

Table C.19 (Contd.)

National National National National National National

Table C.19 (Contd.)

8. Popular D/A converters

LC2MOS P-compatible 14-bit D/A converter

Table C.20 (Contd.) Type Number

Table C.20 (Contd.) Type Number

Table C.20 (Contd.)

Table C.21 8-bit microprocessors

8X300 Z80 Z180

Signetics Zilog Zilog

Table C.22 16-bit microprocessors

Table C.23 32-bit microprocessors Type Number

Table C.24 64-bit microprocessors Type Number

10. Popular microcontrollers

80C32/8XC52/ 54/58 89C51

68HC05 Family of 68HC11 Family

PIC 16X84 Family

XC-800 Family MCS-51 Z8 eZ8 (Encore Z8)

Infineon Intel Zilog Zilog

Table C.26 16-bit microcontrollers

Freescale Semiconductor Infineon

PIC 24F PIC 24H MCS-96 family MCS 296 family

Microchip Technology Microchip Technology Intel Intel

Table C.27 32-bit microcontrollers

Quad 2-input NAND 1A 1B 1Y 2A 2B 2Y GND

nA, nB = Data Inputs nY = Data Output

Quad 2-input NOR 1Y 1A 1B 2Y 2A 2B GND

nA, nB = Data Inputs nY = Data Output

Triple 3-Input AND

Dual 4-Input NAND

1OC 1A 1Y 2OC 2A 2Y GND

742 40 G 0 0 1 A 1 0 X 742 41 1G 0 0 1 1A 0 1 X 1Y 0 1 Z 742 44 G 0 0 1 A 0 1 X 1Y 0 1 Z 2G 0 1 1 2A X 0 1 2Y Z 0 1 Y 0 1 Z

Quad 2-Input NOR 1A 1B 1Y 2Y 2A 2B VSS 7 8 4001 1 14 VDD 4B 4A 4Y 3Y 3B 3A

nA, nB = Data Inputs nY = Data Output

Du al 4-Inp ut NOR nA, nB, nC, nD = Data Inputs nY = Data Output 1Y 1A 1B 1C 1D NC

Hex Inverting Buffer VDD 1Y 1A 2Y 2A 3Y 3A VSS 8 9 4049 1 16 NC 6Y 6A NC 5Y 5A 4Y 4A