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Chapter 2. - DC Biasing - BJTs 1. BJT – A Review

Invented in 1948 by Bardeen, Brattain and Shockley Contains three adjoining, alternately doped semiconductor regions: Emitter (E), Base (B), and Collector (C) The middle region, base, is very thin Emitter is heavily doped compared to collector. So, emitter and collector are not interchangeable.

  • A. Three operating regions

Linear region operation:

Base – emitter junction forward biased

Base – collector junction reverse biased

Cutoff region operation:

Base – emitter junction reverse biased

Base – collector junction reverse biased

Saturation region operation:

Base – emitter junction forward biased

Base – collector junction forward biased

  • B. Three operating regions of BJT

Cut off: V CE = V CC , I C

0

Active or linear : V CE

V CC /2 , I C

Saturation: V CE

0 , I C

I C max

I C max /2

  • C. Q-Point (Static Operation Point)

Chapter 2. - DC Biasing - BJTs 1. BJT – A Review • • • •

The values of the parameters I B , I C and V CE together are termed as ‘operating point’ or Q ( Quiescent) point of the transistor.

The intersection of the dc bias value of I B with the dc load line determines the Q-

point. It is desirable to have the Q-point centered on the load line. Why?

When a circuit is designed to have a centered Q-point, the amplifier is said to be

midpoint biased. Midpoint biasing allows optimum ac operation of the amplifier.

2.

Introduction - Biasing

The analysis or design of a transistor amplifier requires knowledge of both the dc and ac response of the system.In fact, the amplifier increases the strength of a weak signal by transferring the energy from the applied DC source to the weak input ac signal •

The analysis or design of any electronic amplifier therefore has two components:

The dc portion and

The ac portion

During the design stage, the choice of parameters for the required dc levels will

affect the ac response.

A.

What is biasing circuit?

 

Once the desired dc current and voltage levels have been identified, a network must be constructed that will establish the desired values of I B , I C and V CE , Such a network is known as biasing circuit. A biasing network has to preferably make use of one power supply to bias both the junctions of the transistor.

B.

Purpose of the DC biasing circuit

To turn the device “ON”

To place it in operation in the region of its characteristic where the device operates most linearly, i.e. to set up the initial dc values of I B , I C , and V CE

C.

Important basic relationship

V BE = 0.7V

 

I E = (

+ 1) I B

I C

I C =

I B

D.

Biasing circuits:

 

Fixed – bias circuit

Emitter bias

Voltage divider bias

DC bias with voltage feedback

Miscellaneous bias

3. Fixed bias

3. Fixed bias A. Input loop • Applying KVL to the input loop: • V CC

A.

Input loop

Applying KVL to the input loop:

 

V CC = I B R B + V BE From the above equation, deriving for IB, we get,

 
 

I B

= [V CC – V BE ] / R B

The selection of R B sets the level of base current for the operating point.

 

B.

Output loop

Applying KVL for the output loop:

 

V CC = I C R C + V CE Thus,

 

V CE = V CC – I C R C

In circuits where emitter is grounded, V CE = V E V BE = V B

 

C.

Problem – Analysis

Given the fixed bias circuit with V CC = 12V, R B = 240 k Determine the values of operating point.

, R C = 2.2 k

and

= 75.

Equation for the input loop is:

I B

= [V CC – V BE ] / R B where V BE = 0.7V,

thus substituting the other given values in the equation, we get

I B = 47.08uA

I C =

I B = 3.53mA

V CE = V CC – I C R C = 4.23V When the transistor is biased such that I B is very high so as to make I C very high such that I C R C drop is almost V CC and V CE is almost 0, the transistor is said to be in saturation.

I C sat = V CC / R C

in a fixed bias circuit.

D.

Load line

• V = V – I R = 4.23V When the transistor is biased such that

The two extreme points on the load line can be calculated and by joining which

the load line can be drawn. To find extreme points, first, Ic is made 0 in the equation: V CE = V CC – I C R C . This

gives the coordinates (V CC ,0) on the x axis of the output characteristics. The other extreme point is on the y-axis and can be calculated by making V CE = 0

in the equation V CE = V CC – I C R C which gives I C( max) = V CC / R C thus giving the coordinates of the point as (0, V CC / R C ). The two extreme points so obtained are joined to form the load line.

The load line intersects the output characteristics at various points corresponding to different I B s. The actual operating point is established for the given I B .

E.

Q point variation

As I B is varied, the Q point shifts accordingly on the load line either up or down depending on I B increased or decreased respectively.

As R C is varied, the Q point shifts to left or right along the same I B line since the

slope of the line varies. As R C increases, slope reduces ( slope is

-1/R C ) which

results in shift of Q point to the left meaning no variation in I C and reduction in V CE .

Thus if the output characteristics is known, the analysis of the given fixed bias circuit or designing a fixed bias circuit is possible using load line analysis as mentioned above.

4. Emitter Bias

• • It can be shown that, including an emitter resistor in the fixed bias circuit
It can be shown that, including an emitter resistor in the fixed bias circuit
improves the stability of Q point.
Thus emitter bias is a biasing circuit very similar to fixed bias circuit with an
emitter resistor added to it.
a.
Input loop
Writing KVL around the input loop we get,
V CC = I B R B + V BE + I E R E
We know that,
(1)
I E = (
Substituting this in (1), we get,
+1)I B
(2)

Solving for I B :

V CC = I B R B + V BE + ( V CC – V BE = I B (R B + (

+1)I B R E +1) R E )

I B = (V CC – V BE ) /[(R B + ( The expression for I B in a fixed bias circuit was, I B = (V CC – V BE ) /R B

+1) R E )]

R EI in the above circuit is (

+1)R E which means that, the emitter resistance that

is common to both the loops appears as such a high resistance in the input loop.

Thus Ri = (

+1)R E ( more about this when we take up ac analysis)

B. Output loop

I = (V – V ) /[(R + ( The expression for I in a fixed

Collector – emitter loop

Applying KVL,

V CC = I C R C + V CE + I E R E

I C is almost same as I E

Thus,

V CC = I C R C + V CE + I C R E = I C (R C + R E ) +V CE V CE = V CC - I C (R C + R E ) Since emitter is not connected directly to ground, it is at a potential V E , given by,

V E = I E R E V C = V CE + V E OR V C = V CC – I C R C

Also, V B = V CC – I B R B OR V B = V BE + V E

C. Problem: Analyze the following circuit: given = 75, V CC = 16V, R B =
C.
Problem:
Analyze the following circuit: given
= 75, V CC = 16V, R B = 430k
, R C = 2k
and R E = 1k
Solution:
I B = (V CC – V BE ) /[(R B + (
+1) R E )]
= ( 16 – 0.7) / [ 430k + (76) 1k] = 30.24
A
I C = ( 75) (30.24
A) = 2.27mA
V CE = V CC - I C (R C + R E ) = 9.19V
V
= V CC – I C R C = 11.46V
C
V E = V C – V CE = 2.27V
V B = V BE + V E = 2.97V
V BC = V B – V C = 2.97 – 11.46 = - 8.49V
D.
Load line analysis

The two extreme points on the load line of an emitter bias circuit are,

(0, V CC / [ R C + R E ]) on the Y axis, and

( V CC , 0) on the X axis.

5. Voltage divider bias +V CC R C R 1 C 2 C 1 v in
5. Voltage divider bias
+V
CC
R C
R 1
C 2
C 1
v
in
R 2
R E
C 3

v

out

This is the biasing circuit wherein, I CQ and V CEQ are almost independent of

.

The level of I BQ will change with

so as to maintain the values of I CQ and V CEQ almost

same, thus maintaining the stability of Q point.

Two methods of analyzing a voltage divider bias circuit are:

Exact method – can be applied to any voltage divider circuit Approximate method – direct method, saves time and energy, can be applied in most of the circuits.

  • I. Exact method

In this method, the Thevenin equivalent network for the network to the left of the base terminal to be found.

5. Voltage divider bias +V CC R C R 1 C 2 C 1 v in

A. To find Rth:

5. Voltage divider bias +V CC R C R 1 C 2 C 1 v in

From the above circuit,

  • B. To find Eth

R th = R1|

|

R2

= R1 R2 / (R1 + R2)

From the above circuit, B. To find Eth R = R1 | | R2 = R1

From the above circuit,

E th = V R2 = R 2 V CC / (R1 + R2)

From the above circuit, B. To find Eth R = R1 | | R2 = R1

In the above network, applying KVL

( E th – V BE ) = I B [ R th +( I B = ( E th – V BE ) / [ R th +(

+ 1) R E ] + 1) R E ]

  • C. Analysis of Output loop

KVL to the output loop:

V CC = I C R C + V CE + I E R E

Thus,

I E

I C

V CE = V CC – I C (R C + R E )

Note that this is similar to emitter bias circuit.

D. Problem

For the circuit given below, find I C and V CE .

Given the values of R 1 , R 2 , R C , R E and

= 140 and V CC = 18V.

For the purpose of DC analysis, all the capacitors in the amplifier circuit are opened.

Note that this is similar to emitter bias circuit . D. Problem For the circuit given

Solution

Considering exact analysis:

Let us find

  • 1. R th = R1|

|

R2

= R1 R2 / (R1 + R2) = 3.55K

  • 2. E th = V R2 = R2V CC / (R1 + R2)

Then find

  • 3. Then find IB

= 1.64V

I

B

= ( Eth – V BE ) / [ Rth +(

+ 1) R E ]

= 4.37

A

4. Then find

I C =

I B = 0.612mA

  • 5. V CE = V CC – I C (RC + RE) = 12.63V

Then find

II.

Approximate analysis:

The input section of the voltage divider configuration can be represented by the network shown in the next slide.

  • A. Input Network

II. Approximate analysis: The input section of the voltage divider configuration can be represented by the

The emitter resistance R E is seen as (

+1)R E at the input loop.

If this resistance is much higher compared to R 2 , then the current I B is much smaller than

I 2 through R 2 . This means,

Ri >> R2 OR

+1)R E 10R2 OR

(

R E

10R2

This makes I B to be negligible. Thus I 1 through R 1 is almost same as the current I 2 through R 2 . Thus R 1 and R 2 can be considered as in series. Voltage divider can be applied to find the voltage across R 2 ( V B )

V B

  • B. Output Network

= V CC R 2 / ( R 1 + R 2 )

Once V B is determined, V E is calculated as, V E = V B – V BE

After finding V E , I E is calculated as,

I E = V E / R E

I E

I

C

V CE = V CC – I C ( R C + R E )

C. Problem

Given: V CC = 18V, R 1 = 39k

, R 2 = 3.9k

, R C = 4k

, R E = 1.5k

and

=

140. Analyse the circuit using approximate technique. In order to check whether approximate technique can be used, we need to verify the

condition,

 

R E

10R 2

Here,

 

R E

= 210 k

and 10R 2 = 39 k

Thus the condition

Solution

R E 10R 2 satisfied

Thus approximate technique can be applied.

  • 1. Find V B = V CC R 2 / ( R 1 + R 2 ) = 1.64V

  • 2. Find V E = V B – 0.7 = 0.94V

  • 3. Find I E

= V E / R E = 0.63mA = I C

  • 4. Find V CE = V CC – I C (R C + R E ) = 12.55V

Comparison

Exact Analysis

Approximate Analysis

I C = 0.612mA

I C = 0.63mA

V CE = 12.63V

V CE = 12.55V

Both the methods result in the same values for I C and V CE since the condition

R E

10R 2 is satisfied. It can be shown that the results due to exact analysis and approximate analysis have more deviation if the above mentioned condition is not satisfied. For load line analysis of voltage divider network, Ic,max = V CC / ( R C +R E ) when V CE = 0V and V CE max = V CC when I C = 0.

  • 6. DC bias with voltage feedback

A. Input loop Applying KVL to input loop: V = I R + I R +
  • A. Input loop

A. Input loop Applying KVL to input loop: V = I R + I R +

Applying KVL to input loop:

V CC = I C | R C + I B R B + V BE + I E R E

I C |

I C and I C

I E

Substituting for I E as ( I B = ( V CC – V BE ) / [ R B +

  • B. Output loop

+1)I B [ or as ( R C + R E )]

I B ] and solving for I B ,

A. Input loop Applying KVL to input loop: V = I R + I R +

Neglecting the base current, and applying KVL to the output loop results in,

V CE = V CC – I C ( R C + R E )

In this circuit, improved stability is obtained by introducing a feedback path from collector to base. Sensitivity of Q point to changes in beta or temperature variations is normally less than that encountered for the fixed bias or emitter biased configurations.

C. Problem:

Given:

V CC = 10V, R C = 4.7k, R B = 250 Analyze the circuit.

and R E = 1.2k.

= 90.

I B = ( V CC – V BE ) / [ R B +

( R C + R E )]

 

=

11.91

A

I C = (

I B ) = 1.07mA

 

V CE = V CC – I C ( R C + R E )

= 3.69V

In the above circuit, Analyze the circuit if

= 135 ( 50% increase).

With the same procedure as followed in the previous problem, we get

 

I B = 8.89

A

I C = 1.2mA

V CE = 2.92V

50% increase in

resulted in 12.1% increase in I C and 20.9% decrease in V CEQ

Problem 2:

Determine the DC level of I B and V C for the network shown:

Solution: Open all the capacitors for DC analysis. R = 91 k + 110 k I

Solution:

Open all the capacitors for DC analysis.

R B = 91 k

+ 110 k

I B = ( V CC – V BE ) / [ R B +

= 201k ( R C + R E )]

= (18 – 0.7) / [ 201k + 75( 3.3+0.51)]

= 35.5

A

I C =

I B = 2.66mA

V CE = V CC – (I C R C ) = 18 – ( 2.66mA)(3.3k) = 9.22V

D. Load line analysis

The two extreme points of the load line I C,max and V CE, max are found in the same as a voltage divider circuit.

I C,max = V CC / (R C + R E ) – Saturation current V CE, max – Cut off voltage

7. Miscellaneous bias configurations

There are a number of BJT bias configurations that do not match the basic types of biasing that are discussed till now.

  • I. Miscellaneous bias (1)

Analyze the circuit in the next slide. Given

= 120

There are a number of BJT bias configurations that do not match the basic types of

Solution

This circuit is same as DC bias with voltage feedback but with no emitter resistor. Thus the expression for I B is same except for R E term.

I B = (V CC – V BE ) / ( R B +

R C )

= ( 20 – 0.7) / [680k + (120)(4.7k)]

= 15.51

A

I C =

I B = 1.86mA

V CE = V CC – I C R C = 11.26V = V CE V B = V BE = 0.7V V BC = V B – V C = 0.7V – 11.26V = - 10.56V

II.

Miscellaneous bias (2)

Equivalent circuit Input loop Output loop 17

Equivalent circuit

Equivalent circuit Input loop Output loop 17

Input loop

Output loop

Equivalent circuit Input loop Output loop 17
Solution The above circuit is fixed bias circuit. Applying KVL to input loop: V EE =

Solution

The above circuit is fixed bias circuit.

Applying KVL to input loop:

V EE

= V BE

+ I B R B

I B = ( V EE – V BE ) / R B = 83

I C =

I B = 3.735mA

A

V C = -I C R C = - 4.48V V B = - I B R B = - 8.3V

III.

Miscellaneous bias (3)

Determine V CE,Q and I E for the network.

Given

= 90

( Note that the circuit given is common collector mode which can be identified by No resistance connected to the collector output taken at the emitter)

Solution The above circuit is fixed bias circuit. Applying KVL to input loop: V EE =
Input loop Writing KVL to input loop: V = I R + V + ( +1)I

Input loop

Input loop Writing KVL to input loop: V = I R + V + ( +1)I

Writing KVL to input loop:

V EE = I B R B + V BE + (

+1)I B R E

I B = (V EE – V BE ) / [R B + (

+1) R E ]

= ( 20 – 0.7) / [ 240K + (91)(2K)]

= 45.73

A

I C =

I B = 4.12mA

Output loop

Output loop Applying KVL to the output loop: I = ( V EE = V CE

Applying KVL to the output loop:

I E = (

V EE = V CE + I E R E +1) I B = 4.16mA, V EE = 20V

V CE = V EE – I E R E = 11.68V

IV.

Miscellaneous bias (4)

Find V CB and I B for the Common base configuration given:

Given: = 60 Input loop
Given:
= 60
Input loop
Output loop Applying KVL to the output loop: I = ( V EE = V CE

Applying KVL to input loop

I E = ( V EE – V BE ) / R E = 2.75mA I E = I C = 2.75mA

Output loop

I B = I C / = 45.8 A
I B = I C /
= 45.8
A

Applying KVL to output loop:

V CB

V CC = I C R C + V CB = V CC – I C R C = 3.4V

  • V. Miscellaneous bias (5)

Determine VC and VB for the network given below.

Given

= 120

Note that this is voltage divider circuit with split supply. ( +V CC at the collector and – V EE at the emitter)

Applying KVL to input loop I = ( V – V ) / R = 2.75mA

Thevinin equivalent at the input

Thevinin equivalent at the input R = (8.2k)(2.2k) / [ 8.2k+2.2k] = 1.73k I = (V

R th = (8.2k)(2.2k) / [ 8.2k+2.2k] = 1.73k

  • I = (V CC + V EE ) / [R 1 + R 2 ] = ( 20 + 20) / ( 8.2K + 2.2K) = 3.85mA E th = IR 2 – V EE = - 11.53V

Equivalent circuit

Thevinin equivalent at the input R = (8.2k)(2.2k) / [ 8.2k+2.2k] = 1.73k I = (V

Applying KVL:

V EE – E th – V BE – (

+1)I B R E – I B R th = 0

I B = ( V EE – E th – V BE ) / [(

+1) R E + R th ]

= 35.39

A

I C =

I B = 4.25mA

V C = V CC – I C R C = 8.53V V B = - E th – I B R th = - 11.59V

Design Operations:

Designing a circuit requires Understanding of the characteristics of the device The basic equations for the network Understanding of Ohms law, KCL, KVL If the transistor and supplies are specified, the design process will simply determine the required resistors for a particular design. Once the theoretical values of the resistors are determined, the nearest standard commercial values are normally chosen. Operating point needs to be recalculated with the standard values of resistors chosen and generally the deviation expected would be less than or equal to

5%.

Problem:

Given I CQ = 2mA and V CEQ = 10V. Determine R 1 and R C for the network shown:

Applying KVL: V – E – V – ( +1)I R – I R = 0

Solution

To find R 1 :

  • 1. Find V B . And to find V B , find V E because, V B = V E + V BE

  • 2. Thus, V E = I E R E and I E

I C = 2mA

= (2mA)(1.2k) = 2.4V

  • 3. V B =2.4 + 0.7 = 3.1V

  • 4. Also, V B = V CC R 2 /(R 1 + R 2 ) 3.1 = (18)(18k) / R1+18k

Thus, R 1 = 86.52k

To find R C :

Voltage across R C = V CC – ( V CE + I E R E ) = 18 – [ 10 + (2mA)1.2k] = 5.6V R C = 5.6/2mA = 2.8K

Nearest standard values are,

R 1 = 82k

+ 4.7 k

= 86.7 k

where as calculated value is 86.52 k

R C = 2.7k in series with 1k = 2.8k

.

both would result in a very close value to the design level.

Problem 2

The emitter bias circuit has the following specifications: I CQ = 1/2I sat , I sat = 8mA, V C =

18V, V CC = 18V and

= 110. Determine R C , R E and R B .

Solution:

I CQ = 4mA V RC = (V CC – V C ) = 10V R C = V RC / I CQ , = 10/4mA = 2.5k To find R E : I Csat = V CC / (R C + R E ) To find R B : Find I B where, I B = I C / = 36.36 Also, for an emitter bias circuit,

A

I B = (V CC – V BE ) / R B +( Thus, R B = 639.8 k

+1) R E

Standard values: R C = 2.4 k

, R E = 1 k

, R B = 620 k

8mA = 28 / ( 2.5k + R E ) Thus, R E = 1k

8. Transistor switching networks:

Through proper design transistors can be used as switches for computer and control applications. When the input voltage V B is high ( logic 1), the transistor is in saturation ( ON). And the output at its collector = V CE is almost 0V( Logic 0)

  • A. Transistor as a switch

When the base voltage V B is low( logic 0), i.e, 0V, the transistor is cutoff( Off) and I C is 0, drop across R C is 0 and therefore voltage at the collector is V CC .( logic 1) Thus transistor switch operates as an inverter. This circuit does not require any DC bias at the base of the transistor.

  • B. Design

When Vi ( V B ) is 5V, transistor is in saturation and I Csat Just before saturation, I B,max = I C,sat / Thus the base current must be greater than I B,max to make the transistor to work in saturation.

DC

  • C. Analysis

8mA = 28 / ( 2.5k + R ) Thus, R = 1k 8. Transistor switching

When Vi = 5V, the resulting level of I B is

I B = (Vi – 0.7) / R B = ( 5 – 0.7) / 68k

= 63

A

I Csat = V CC / R C = 5/0.82k = 6.1mA

D. Problem

Determine R B and R C for the inverter of figure:

R C I C sat = V CC / 10mA = 10V/ R C
R C
I C sat = V CC /
10mA = 10V/ R C

R C = 1k

I B just at saturation = I C sat / = 10mA / 250

= 40

A

Choose I B > I C sat /

, 60

A

I B = (Vi – 0.7) / R B

60

A = ( 10 – 0.7) / R B

R B = 155k Choose R B = 150k

, standard value,

re calculate I B , we get I B = 62 Thus, R C = 1k and R B = 155k

A which is also >

I C sat /

E. Switching Transistors

Transistor ‘ON’ time = delay time + Rise time

Delay time is the time between the changing state of the input and the beginning of a

response at the output. Rise time is the time from 10% to 90% of the final value.

Transistor ‘OFF’ time = Storage time + Fall time For an ‘ON’ transistor, V BE should be around 0.7V

For the transistor to be in active region, V CE is usually about 25% to 75% of V CC . If V CE = almost V CC , probable faults:

the device is damaged connection in the collector – emitter or base – emitter circuit loop is open.

– One of the most common mistake in the lab is usage of wrong resistor value. Check various voltages with respect to ground. Calculate the current values using voltage readings rather than measuring current by breaking the circuit.

Problem – 1

Check the fault in the circuit given.

E. Switching Transistors Transistor ‘ON’ time = delay time + Rise time Delay time is the

Problem - 2

9. PNP transistors The analysis of PNP transistors follows the same pattern established for NPN transistors.

9. PNP transistors

The analysis of PNP transistors follows the same pattern established for NPN transistors. The only difference between the resulting equations for a network in which an npn transistor has been replaced by a pnp transistor is the sign associated with particular quantities.

PNP transistor in an emitter bias

9. PNP transistors The analysis of PNP transistors follows the same pattern established for NPN transistors.

Applying KVL to Input loop:

V CC = I B R B +V BE +I E R E

Thus, I B = (V CC – V BE ) / [R B + (

+1) R E ]

Applying KVL Output loop:

V CE = - ( V CC – I C R C )

  • 10. Bias stabilization

The stability of a system is a measure of the sensitivity of a network to variations in its parameters. In any amplifier employing a transistor the collector current I C is sensitive to each of the following parameters. increases with increase in temperature. Magnitude of V BE decreases about 2.5mV per degree Celsius increase in temperature. I CO doubles in value for every 10 degree Celsius increase in temperature.

T (degree

Ico (nA)

 

V BE (V)

Celsius)

- 65

0.2

x 10-3

20

0.85

25

0.1

50

0.65

100

20

80

0.48

175

3.3

x 103

120

0.3

A. Stability factors

S (I CO ) =

I C /

I C0

S (V BE ) =

I C /

V BE

S (

) =

I C /

Networks that are quite stable and relatively insensitive to temperature variations have low stability factors.

The higher the stability factor, the more sensitive is the network to variations in that parameter.

  • B. S( I CO )

Analyze S( I CO ) for –

 

emitter bias configuration fixed bias configuration

Voltage divider configuration

For the emitter bias configuration,

S( I CO ) = (

[(

+ 1)

+ R B / R E ]

+ 1) [ 1 + R B / R E ] / + 1) , then

If R B / R E >> (

 

S( I CO ) = (

+ 1)

For R B / R E <<1, S( I CO )

1

 

Thus, emitter bias configuration is quite stable when the ratio R B / R E is as small as possible.

Emitter bias configuration is least stable when R B / R E approaches (

+ 1) .

C.

Fixed bias configuration

 

+ 1) [ 1 + R B / R E ] /

[(

+ 1)

+ R B / R E ]

S( I CO ) = ( = (

+ 1) [R E + R B ] /

[(

+ 1) R E + R B ]

 

By plugging R E = 0, we get

 

S( I CO ) =

+ 1

This indicates poor stability.

 

D.

Voltage divider configuration

 

S( I CO ) = (

+ 1) [ 1 + R B / R E ] /

[(

+ 1)

+ R B / R E ]

Here, replace R B with R th

 

S( I CO ) = (

+ 1) [ 1 + R th / R E ] /

[(

+ 1)

+ R th / R E ]

Thus, voltage divider bias configuration is quite stable when the ratio R th / R E is as small as possible.

  • E. Physical impact

In a fixed bias circuit, I C increases due to increase in I C0 . [I C =

I B + (

+1) I C0 ]

I B is fixed by V CC and R B . Thus level of I C would continue to rise with temperature – a very unstable situation.

In emitter bias circuit, as I C increases, I E increases, V E increases. Increase in V E reduces I B . I B = [V CC – V BE – V E ] / R B . A drop in I B reduces I C .Thus, this configuration is such that there is a reaction to an increase in I C that will tend to oppose the change in bias conditions.

In the DC bias with voltage feedback, as I C increases, voltage across R C increases, thus reducing I B and causing I C to reduce.

The most stable configuration is the voltage – divider network. If the condition R E >>10R 2 , the voltage V B will remain fairly constant for changing levels of I C . V BE = V B – V E , as I C increases, V E increases, since V B is constant, V BE drops making I B to fall, which will try to offset the increases level of I C .

  • F. S(V BE )

S(V BE ) =

I C /

V BE

For an emitter bias circuit, S(V BE ) = -

/ [ R B + (

+ 1)R E ]

If R E =0 in the above equation, we get S(V BE ) for a fixed bias circuit as,

S(V BE ) = -

/ R B .

  • G. For an emitter bias ,

S(V BE ) = -

/ [ R B + (

+ 1)R E ] can be rewritten as,

 

S(V BE ) = - (

/R E )/ [R B /R E + (

+ 1)]

If (

+ 1)>> R B /R E , then

S(V BE ) = - (

/R E )/ (

+ 1)

= - 1/ R E

The larger the R E , lower the S(V BE ) and more stable is the system.

Total effect of all the three parameters on I C can be written as,

I C = S(I CO )

I CO + S(V BE )

V BE + S(

)