•
•
•
•
Invented in 1948 by Bardeen, Brattain and Shockley Contains three adjoining, alternately doped semiconductor regions: Emitter (E), Base (B), and Collector (C) The middle region, base, is very thin Emitter is heavily doped compared to collector. So, emitter and collector are not interchangeable.
A. Three operating regions
•
Linear – region operation:
– 
Base – emitter junction forward biased 
– 
Base – collector junction reverse biased 
•
•
Cutoff – region operation:
–
Base – emitter junction reverse biased
Base – collector junction reverse biased
– Saturation – region operation:
– 
Base – emitter junction forward biased 
– 
Base – collector junction forward biased 
B. Three operating regions of BJT
• 
Cut off: V _{C}_{E} = V _{C}_{C} , I _{C} 
0 

• 
Active or linear : V _{C}_{E} 
V _{C}_{C} /2 , I _{C} 

• 
Saturation: V _{C}_{E} 
0 , I _{C} 
I _{C} _{m}_{a}_{x} 
I _{C} _{m}_{a}_{x} /2
C. QPoint (Static Operation Point)
•
The values of the parameters I _{B} , I _{C} and V _{C}_{E} together are termed as ‘operating point’ or Q ( Quiescent) point of the transistor.
1
• 
The intersection of the dc bias value of I _{B} with the dc load line determines the Q 
• 
point. It is desirable to have the Qpoint centered on the load line. Why? 
• 
When a circuit is designed to have a centered Qpoint, the amplifier is said to be 
• 
midpoint biased. Midpoint biasing allows optimum ac operation of the amplifier. 
2. 
Introduction  Biasing 
The analysis or design of a transistor amplifier requires knowledge of both the dc and ac response of the system.In fact, the amplifier increases the strength of a weak signal by transferring the energy from the applied DC source to the weak input ac signal •
The analysis or design of any electronic amplifier therefore has two components:
• 
The dc portion and 
• 
The ac portion 
During the design stage, the choice of parameters for the required dc levels will
affect the ac response.
A. 
What is biasing circuit? 

• 
Once the desired dc current and voltage levels have been identified, a network must be constructed that will establish the desired values of I _{B} , I _{C} and V _{C}_{E} , Such a network is known as biasing circuit. A biasing network has to preferably make use of one power supply to bias both the junctions of the transistor. 

B. 
Purpose of the DC biasing circuit 

• 
To turn the device “ON” 

• 
To place it in operation in the region of its characteristic where the device operates most linearly, i.e. to set up the initial dc values of I _{B} , I _{C} , and V _{C}_{E} 

C. 
Important basic relationship 

• 
V _{B}_{E} = 0.7V 

• 
I _{E} = ( 
+ 1) I _{B} 
I _{C} 
• 
I _{C} = 
I _{B} 

D. 
Biasing circuits: 

• 
Fixed – bias circuit 

• 
Emitter bias 

• 
Voltage divider bias 

• 
DC bias with voltage feedback 

• 
Miscellaneous bias 
2
A. 
Input loop 

• 
Applying KVL to the input loop: 

• 
V CC = I B R B + V BE From the above equation, deriving for IB, we get, 

I _{B} 
= [V _{C}_{C} – V _{B}_{E} ] / R _{B} 

• 
The selection of R _{B} sets the level of base current for the operating point. 

B. 
Output loop 

• 
Applying KVL for the output loop: 

• 
V CC = I C R C + V CE Thus, 

V CE = V CC – I C R C 

• 
In circuits where emitter is grounded, V CE = V E V BE = V B 

C. 
Problem – Analysis 

Given the fixed bias circuit with V _{C}_{C} = 12V, R _{B} = 240 k Determine the values of operating point. 
, R _{C} = 2.2 k 
and 
= 75. 
Equation for the input loop is:
I _{B}
= [V _{C}_{C} – V _{B}_{E} ] / R _{B} where V _{B}_{E} = 0.7V,
thus substituting the other given values in the equation, we get
I _{B} = 47.08uA
I _{C} =
I _{B} = 3.53mA
3
• 
V _{C}_{E} = V _{C}_{C} – I _{C} R _{C} = 4.23V When the transistor is biased such that I _{B} is very high so as to make I _{C} very high such that I _{C} R _{C} drop is almost V _{C}_{C} and V _{C}_{E} is almost 0, the transistor is said to be in saturation. 

I _{C} sat = V _{C}_{C} / R _{C} 
in a fixed bias circuit. 

D. 
Load line 



• 
The two extreme points on the load line can be calculated and by joining which 

• 
the load line can be drawn. To find extreme points, first, Ic is made 0 in the equation: V _{C}_{E} = V _{C}_{C} – I _{C} R _{C} . This 

• 
gives the coordinates (V _{C}_{C} ,0) on the x axis of the output characteristics. The other extreme point is on the yaxis and can be calculated by making V _{C}_{E} = 0 

• 
in the equation V _{C}_{E} = V _{C}_{C} – I _{C} R _{C} which gives I _{C}_{(} _{m}_{a}_{x}_{)} = V _{C}_{C} / R _{C} thus giving the coordinates of the point as (0, V _{C}_{C} / R _{C} ). The two extreme points so obtained are joined to form the load line. 

• 
The load line intersects the output characteristics at various points corresponding to different I _{B} s. The actual operating point is established for the given I _{B} . 

E. 
Q point variation 
As I _{B} is varied, the Q point shifts accordingly on the load line either up or down depending on I _{B} increased or decreased respectively.
As R _{C} is varied, the Q point shifts to left or right along the same I _{B} line since the
slope of the line varies. As R _{C} increases, slope reduces ( slope is
1/R _{C} ) which
results in shift of Q point to the left meaning no variation in I _{C} and reduction in V _{C}_{E} .
Thus if the output characteristics is known, the analysis of the given fixed bias circuit or designing a fixed bias circuit is possible using load line analysis as mentioned above.
4
Solving for I _{B} :
V _{C}_{C} = I _{B} R _{B} + V _{B}_{E} + ( V _{C}_{C} – V _{B}_{E} = I _{B} (R _{B} + (
+1)I _{B} R _{E} +1) R _{E} )
5
I _{B} = (V _{C}_{C} – V _{B}_{E} ) /[(R _{B} + ( The expression for I _{B} in a fixed bias circuit was, I _{B} = (V _{C}_{C} – V _{B}_{E} ) /R _{B}
+1) R _{E} )]
•
R _{E}_{I} in the above circuit is (
+1)R _{E} which means that, the emitter resistance that
is common to both the loops appears as such a high resistance in the input loop.
•
Thus Ri = (
+1)R _{E} ( more about this when we take up ac analysis)
Collector – emitter loop
Applying KVL,
V _{C}_{C} = I _{C} R _{C} + V _{C}_{E} + I _{E} R _{E}
I _{C} is almost same as I _{E}
Thus,
V _{C}_{C} = I _{C} R _{C} + V _{C}_{E} + I _{C} R _{E} = I _{C} (R _{C} + R _{E} ) +V _{C}_{E} V _{C}_{E} = V _{C}_{C}  I _{C} (R _{C} + R _{E} ) Since emitter is not connected directly to ground, it is at a potential V _{E} , given by,
V _{E} = I _{E} R _{E} V _{C} = V _{C}_{E} + V _{E} OR V _{C} = V _{C}_{C} – I _{C} R _{C}
6
Also, V _{B} = V _{C}_{C} – I _{B} R _{B} OR V _{B} = V _{B}_{E} + V _{E}
The two extreme points on the load line of an emitter bias circuit are,
(0, V _{C}_{C} / [ R _{C} + R _{E} ]) on the Y axis, and
( V _{C}_{C} , 0) on the X axis.
7
^{v}
out
This is the biasing circuit wherein, I _{C}_{Q} and V _{C}_{E}_{Q} are almost independent of
.
The level of I _{B}_{Q} will change with
so as to maintain the values of I _{C}_{Q} and V _{C}_{E}_{Q} almost
same, thus maintaining the stability of Q point.
Two methods of analyzing a voltage divider bias circuit are:
Exact method – can be applied to any voltage divider circuit Approximate method – direct method, saves time and energy, can be applied in most of the circuits.
In this method, the Thevenin equivalent network for the network to the left of the base terminal to be found.
8
From the above circuit,
R _{t}_{h} = R1

R2
= R1 R2 / (R1 + R2)
From the above circuit,
E _{t}_{h} = V _{R}_{2} = R _{2} V _{C}_{C} / (R1 + R2)
In the above network, applying KVL
( E _{t}_{h} – V _{B}_{E} ) = I _{B} [ R _{t}_{h} +( I _{B} = ( E _{t}_{h} – V _{B}_{E} ) / [ R _{t}_{h} +(
+ 1) R _{E} ] + 1) R _{E} ]
KVL to the output loop:
V _{C}_{C} = I _{C} R _{C} + V _{C}_{E} + I _{E} R _{E}
Thus,
I _{E}
I _{C}
V _{C}_{E} = V _{C}_{C} – I _{C} (R _{C} + R _{E} )
9
Note that this is similar to emitter bias circuit.
For the circuit given below, find I _{C} and V _{C}_{E} .
Given the values of R _{1} , R _{2} , R _{C} , R _{E} and
= 140 and V _{C}_{C} = 18V.
For the purpose of DC analysis, all the capacitors in the amplifier circuit are opened.
Solution
Considering exact analysis:
Let us find
1. R _{t}_{h} = R1

R2
= R1 R2 / (R1 + R2) = 3.55K
2. E _{t}_{h} = V _{R}_{2} = R2V _{C}_{C} / (R1 + R2)
Then find
3. Then find IB
= 1.64V
I
_{B}
= ( Eth – V _{B}_{E} ) / [ Rth +(
+ 1) R _{E} ]
= 4.37
A
4. Then find
I _{C} =
I _{B} = 0.612mA
5. V _{C}_{E} = V _{C}_{C} – I _{C} (RC + RE) = 12.63V
Then find
10
The input section of the voltage divider configuration can be represented by the network shown in the next slide.
The emitter resistance R _{E} is seen as (
+1)R _{E} at the input loop.
If this resistance is much higher compared to R _{2} , then the current I _{B} is much smaller than
I _{2} through R _{2} . This means,
Ri >> R2 OR
+1)R _{E} ≥ 10R2 OR
(
R _{E} ≥
10R2
This makes I _{B} to be negligible. Thus I _{1} through R _{1} is almost same as the current I _{2} through R _{2} . Thus R _{1} and R _{2} can be considered as in series. Voltage divider can be applied to find the voltage across R _{2} ( V _{B} )
V _{B}
= V _{C}_{C} R _{2} / ( R _{1} + R _{2} )
Once V _{B} is determined, V _{E} is calculated as, V _{E} = V _{B} – V _{B}_{E}
After finding V _{E} , I _{E} is calculated as,
I _{E} = V _{E} / R _{E} 

I _{E} 
I 
_{C} 
V _{C}_{E} = V _{C}_{C} – I _{C} ( R _{C} + R _{E} )
11
Given: V _{C}_{C} = 18V, R _{1} = 39k
, R _{2} = 3.9k
, R _{C} = 4k
, R _{E} = 1.5k
and
=
140. Analyse the circuit using approximate technique. In order to check whether approximate technique can be used, we need to verify the
condition, 

R _{E} ≥ 
10R _{2} 

Here, 

R _{E} 
= 210 k 
and 10R _{2} = 39 k 
Thus the condition
Solution
R _{E} ≥ 10R _{2} satisfied
•
Thus approximate technique can be applied.
1. Find V _{B} = V _{C}_{C} R _{2} / ( R _{1} + R _{2} ) = 1.64V
2. Find V _{E} = V _{B} – 0.7 = 0.94V
3. Find I _{E}
= V _{E} / R _{E} = 0.63mA = I _{C}
4. Find V _{C}_{E} = V _{C}_{C} – I _{C} (R _{C} + R _{E} ) = 12.55V
Comparison
Exact Analysis 
Approximate Analysis 
I _{C} = 0.612mA 
I _{C} = 0.63mA 
V _{C}_{E} = 12.63V 
V _{C}_{E} = 12.55V 
Both the methods result in the same values for I _{C} and V _{C}_{E} since the condition
R _{E} ≥
10R _{2} is satisfied. It can be shown that the results due to exact analysis and approximate analysis have more deviation if the above mentioned condition is not satisfied. For load line analysis of voltage divider network, Ic,max = V _{C}_{C} / ( R _{C} +R _{E} ) when V _{C}_{E} = 0V and V _{C}_{E} _{m}_{a}_{x} = V _{C}_{C} when I _{C} = 0.
12
Applying KVL to input loop:
V _{C}_{C} = I _{C} ^{} R _{C} + I _{B} R _{B} + V _{B}_{E} + I _{E} R _{E}
I _{C} ^{}
I _{C} and I _{C}
I _{E}
Substituting for I _{E} as ( I _{B} = ( V _{C}_{C} – V _{B}_{E} ) / [ R _{B} +
+1)I _{B} [ or as ( R _{C} + R _{E} )]
I _{B} ] and solving for I _{B} ,
13
Neglecting the base current, and applying KVL to the output loop results in,
V _{C}_{E} = V _{C}_{C} – I _{C} ( R _{C} + R _{E} )
In this circuit, improved stability is obtained by introducing a feedback path from collector to base. Sensitivity of Q point to changes in beta or temperature variations is normally less than that encountered for the fixed bias or emitter biased configurations.
Given:
V _{C}_{C} = 10V, R _{C} = 4.7k, R _{B} = 250 Analyze the circuit.
and R _{E} = 1.2k.
= 90.
I _{B} = ( V _{C}_{C} – V _{B}_{E} ) / [ R _{B} +
( R _{C} + R _{E} )]
= 
11.91 
A 

I _{C} = ( 
I _{B} ) = 1.07mA 

V _{C}_{E} = V _{C}_{C} – I _{C} ( R _{C} + R _{E} ) 
= 3.69V 

In the above circuit, Analyze the circuit if 
= 135 ( 50% increase). 

With the same procedure as followed in the previous problem, we get 


I _{B} = 8.89 
A 


I _{C} = 1.2mA 


V _{C}_{E} = 2.92V 

50% increase in 
resulted in 12.1% increase in I _{C} and 20.9% decrease in V _{C}_{E}_{Q} 

Problem 2: 
Determine the DC level of I _{B} and V _{C} for the network shown:
14
Solution:
Open all the capacitors for DC analysis.
R _{B} = 91 k
+ 110 k
I _{B} = ( V _{C}_{C} – V _{B}_{E} ) / [ R _{B} +
= 201k ( R _{C} + R _{E} )]
= (18 – 0.7) / [ 201k + 75( 3.3+0.51)]
= 35.5
A
I _{C} =
I _{B} = 2.66mA
V _{C}_{E} = V _{C}_{C} – (I _{C} R _{C} ) = 18 – ( 2.66mA)(3.3k) = 9.22V
The two extreme points of the load line I _{C}_{,}_{m}_{a}_{x} and V _{C}_{E}_{,} _{m}_{a}_{x} are found in the same as a voltage divider circuit.
I _{C}_{,}_{m}_{a}_{x} = V _{C}_{C} / (R _{C} + R _{E} ) – Saturation current V _{C}_{E}_{,} _{m}_{a}_{x} – Cut off voltage
15
There are a number of BJT bias configurations that do not match the basic types of biasing that are discussed till now.
I. Miscellaneous bias (1)
Analyze the circuit in the next slide. Given
= 120
Solution
This circuit is same as DC bias with voltage feedback but with no emitter resistor. Thus the expression for I _{B} is same except for R _{E} term.
I _{B} = (V _{C}_{C} – V _{B}_{E} ) / ( R _{B} +
R _{C} )
= ( 20 – 0.7) / [680k + (120)(4.7k)]
= 15.51
A
I _{C} =
I _{B} = 1.86mA
V _{C}_{E} = V _{C}_{C} – I _{C} R _{C} = 11.26V = V _{C}_{E} V _{B} = V _{B}_{E} = 0.7V V _{B}_{C} = V _{B} – V _{C} = 0.7V – 11.26V =  10.56V
II.
Miscellaneous bias (2)
16
Equivalent circuit
Input loop
Output loop
17
Solution
The above circuit is fixed bias circuit.
Applying KVL to input loop:
V EE
= V BE
+ I B R B
I _{B} = ( V _{E}_{E} – V _{B}_{E} ) / R _{B} = 83
I _{C} =
I _{B} = 3.735mA
A
V _{C} = I _{C} R _{C} =  4.48V V _{B} =  I _{B} R _{B} =  8.3V
III. 
Miscellaneous bias (3) 
Determine V _{C}_{E}_{,}_{Q} and I _{E} for the network. 

Given 
= 90 
( Note that the circuit given is common collector mode which can be identified by No resistance connected to the collector output taken at the emitter)
18
Input loop
Writing KVL to input loop:
V _{E}_{E} = I _{B} R _{B} + V _{B}_{E} + (
+1)I _{B} R _{E}
I _{B} = (V _{E}_{E} – V _{B}_{E} ) / [R _{B} + (
+1) R _{E} ]
= ( 20 – 0.7) / [ 240K + (91)(2K)]
= 45.73
A
I _{C} =
I _{B} = 4.12mA
19
Output loop
Applying KVL to the output loop:
I _{E} = (
V EE = V CE + I E R E +1) I _{B} = 4.16mA, V _{E}_{E} = 20V
V _{C}_{E} = V _{E}_{E} – I _{E} R _{E} = 11.68V
IV.
Miscellaneous bias (4)
Find V _{C}_{B} and I _{B} for the Common base configuration given:
20
Applying KVL to input loop
I _{E} = ( V _{E}_{E} – V _{B}_{E} ) / R _{E} = 2.75mA I _{E} = I _{C} = 2.75mA
Output loop
Applying KVL to output loop:
V _{C}_{B}
V CC = I C R C + V CB = V _{C}_{C} – I _{C} R _{C} = 3.4V
V. Miscellaneous bias (5)
Determine VC and VB for the network given below.
Given
= 120
Note that this is voltage divider circuit with split supply. ( +V _{C}_{C} at the collector and – V _{E}_{E} at the emitter)
21
Thevinin equivalent at the input
R _{t}_{h} = (8.2k)(2.2k) / [ 8.2k+2.2k] = 1.73k
I = (V _{C}_{C} + V _{E}_{E} ) / [R _{1} + R _{2} ] = ( 20 + 20) / ( 8.2K + 2.2K) = 3.85mA E _{t}_{h} = IR _{2} – V _{E}_{E} =  11.53V
Equivalent circuit
22
Applying KVL:
V _{E}_{E} – E _{t}_{h} – V _{B}_{E} – (
+1)I _{B} R _{E} – I _{B} R _{t}_{h} = 0
I _{B} = ( V _{E}_{E} – E _{t}_{h} – V _{B}_{E} ) / [(
+1) R _{E} + R _{t}_{h} ]
= 35.39
A
I _{C} =
I _{B} = 4.25mA
V _{C} = V _{C}_{C} – I _{C} R _{C} = 8.53V V _{B} =  E _{t}_{h} – I _{B} R _{t}_{h} =  11.59V
Design Operations:
Designing a circuit requires Understanding of the characteristics of the device The basic equations for the network Understanding of Ohms law, KCL, KVL If the transistor and supplies are specified, the design process will simply determine the required resistors for a particular design. Once the theoretical values of the resistors are determined, the nearest standard commercial values are normally chosen. Operating point needs to be recalculated with the standard values of resistors chosen and generally the deviation expected would be less than or equal to
5%.
Problem:
•
Given I _{C}_{Q} = 2mA and V _{C}_{E}_{Q} = 10V. Determine R _{1} and R _{C} for the network shown:
Solution
23
To find R _{1} :
1. Find V _{B} . And to find V _{B} , find V _{E} because, V _{B} = V _{E} + V _{B}_{E}
2. Thus, V _{E} = I _{E} R _{E} and I _{E}
I _{C} = 2mA
= (2mA)(1.2k) = 2.4V
3. V _{B} =2.4 + 0.7 = 3.1V
4. Also, V _{B} = V _{C}_{C} R _{2} /(R _{1} + R _{2} ) 3.1 = (18)(18k) / R1+18k
Thus, R _{1} = 86.52k
To find R _{C} :
Voltage across R _{C} = V _{C}_{C} – ( V _{C}_{E} + I _{E} R _{E} ) = 18 – [ 10 + (2mA)1.2k] = 5.6V R _{C} = 5.6/2mA = 2.8K
Nearest standard values are,
R _{1} = 82k
+ 4.7 k
= 86.7 k
where as calculated value is 86.52 k
R _{C} = 2.7k in series with 1k = 2.8k
.
both would result in a very close value to the design level.
Problem 2
The emitter bias circuit has the following specifications: I _{C}_{Q} = 1/2I _{s}_{a}_{t} , I _{s}_{a}_{t} = 8mA, V _{C} =
18V, V _{C}_{C} = 18V and
= 110. Determine R _{C} , R _{E} and R _{B} .
Solution:
I _{C}_{Q} = 4mA V _{R}_{C} = (V _{C}_{C} – V _{C} ) = 10V R _{C} = V _{R}_{C} / I _{C}_{Q} , = 10/4mA = 2.5k To find R _{E} : I _{C}_{s}_{a}_{t} = V _{C}_{C} / (R _{C} + R _{E} ) To find R _{B} : Find I _{B} where, I _{B} = I _{C} / = 36.36 Also, for an emitter bias circuit, 
A 

I _{B} = (V _{C}_{C} – V _{B}_{E} ) / R _{B} +( Thus, R _{B} = 639.8 k +1) R _{E} 

Standard values: R _{C} = 2.4 k 
, R _{E} = 1 k 
, R _{B} = 620 k 
24
8mA = 28 / ( 2.5k + R _{E} ) Thus, R _{E} = 1k
Through proper design transistors can be used as switches for computer and control applications. When the input voltage V _{B} is high ( logic 1), the transistor is in saturation ( ON). And the output at its collector = V _{C}_{E} is almost 0V( Logic 0)
When the base voltage V _{B} is low( logic 0), i.e, 0V, the transistor is cutoff( Off) and I _{C} is 0, drop across R _{C} is 0 and therefore voltage at the collector is V _{C}_{C} .( logic 1) Thus transistor switch operates as an inverter. This circuit does not require any DC bias at the base of the transistor.
When Vi ( V _{B} ) is 5V, transistor is in saturation and I _{C}_{s}_{a}_{t} Just before saturation, I _{B}_{,}_{m}_{a}_{x} = I _{C}_{,}_{s}_{a}_{t} / Thus the base current must be greater than I _{B}_{,}_{m}_{a}_{x} to make the transistor to work in saturation.
_{D}_{C}
25
When Vi = 5V, the resulting level of I _{B} is
I _{B} = (Vi – 0.7) / R _{B} = ( 5 – 0.7) / 68k
= 63
A
I _{C}_{s}_{a}_{t} = V _{C}_{C} / R _{C} = 5/0.82k = 6.1mA
Determine R _{B} and R _{C} for the inverter of figure:
R _{C} = 1k
I _{B} just at saturation = I _{C} _{s}_{a}_{t} / = 10mA / 250
= 40
A
Choose I _{B} > I _{C} _{s}_{a}_{t} /
, 60
A
I _{B} = (Vi – 0.7) / R _{B}
60
A = ( 10 – 0.7) / R _{B}
R _{B} = 155k Choose R _{B} = 150k
, standard value,
re calculate I _{B} , we get I _{B} = 62 Thus, R _{C} = 1k and R _{B} = 155k
A which is also >
I _{C} _{s}_{a}_{t} /
26
Transistor ‘ON’ time = delay time + Rise time
Delay time is the time between the changing state of the input and the beginning of a
response at the output. Rise time is the time from 10% to 90% of the final value.
Transistor ‘OFF’ time = Storage time + Fall time For an ‘ON’ transistor, V _{B}_{E} should be around 0.7V
For the transistor to be in active region, V _{C}_{E} is usually about 25% to 75% of V _{C}_{C} . If V _{C}_{E} = almost V _{C}_{C} , probable faults:
the device is damaged connection in the collector – emitter or base – emitter circuit loop is open.
–
– One of the most common mistake in the lab is usage of wrong resistor value. Check various voltages with respect to ground. Calculate the current values using voltage readings rather than measuring current by breaking the circuit.
Problem – 1
Check the fault in the circuit given.
Problem  2
27
The analysis of PNP transistors follows the same pattern established for NPN transistors. The only difference between the resulting equations for a network in which an npn transistor has been replaced by a pnp transistor is the sign associated with particular quantities.
PNP transistor in an emitter bias
Applying KVL to Input loop:
28
V _{C}_{C} = I _{B} R _{B} +V _{B}_{E} +I _{E} R _{E}
Thus, I _{B} = (V _{C}_{C} – V _{B}_{E} ) / [R _{B} + (
+1) R _{E} ]
Applying KVL Output loop:
V _{C}_{E} =  ( V _{C}_{C} – I _{C} R _{C} )
The stability of a system is a measure of the sensitivity of a network to variations in its parameters. In any amplifier employing a transistor the collector current I _{C} is sensitive to each of the following parameters. increases with increase in temperature. Magnitude of V _{B}_{E} decreases about 2.5mV per degree Celsius increase in temperature. I _{C}_{O} doubles in value for every 10 degree Celsius increase in temperature.
T (degree 
Ico (nA) 
V _{B}_{E} (V) 

Celsius) 

 65 
0.2 
x 103 
20 
0.85 
25 
0.1 
50 
0.65 

100 
20 
80 
0.48 

175 
3.3 
x 103 
120 
0.3 
S (I _{C}_{O} ) =
I _{C} /
I _{C}_{0}
S (V _{B}_{E} ) =
I _{C} /
V _{B}_{E}
S (
) =
I _{C} /
Networks that are quite stable and relatively insensitive to temperature variations have low stability factors.
29
The higher the stability factor, the more sensitive is the network to variations in that parameter.
• Analyze S( I _{C}_{O} ) for – 

– 
emitter bias configuration fixed bias configuration 

– 
Voltage divider configuration 
For the emitter bias configuration,
S( I _{C}_{O} ) = ( 
[( 
+ 1) 
+ R _{B} / R _{E} ] 

+ 1) [ 1 + R _{B} / R _{E} ] / + 1) , then If R _{B} / R _{E} >> ( 

S( I _{C}_{O} ) = ( 
+ 1) 

For R _{B} / R _{E} <<1, S( I _{C}_{O} ) 1 

Thus, emitter bias configuration is quite stable when the ratio R _{B} / R _{E} is as small as possible. 

Emitter bias configuration is least stable when R _{B} / R _{E} approaches ( + 1) . 

C. 
Fixed bias configuration 

+ 1) [ 1 + R _{B} / R _{E} ] / 
[( 
+ 1) 
+ R _{B} / R _{E} ] 

S( I _{C}_{O} ) = ( = ( + 1) [R _{E} + R _{B} ] / 
[( 
+ 1) R _{E} + R _{B} ] 

By plugging R _{E} = 0, we get 

S( I _{C}_{O} ) = 
+ 1 

This indicates poor stability. 

D. 
Voltage divider configuration 
S( I _{C}_{O} ) = ( 
+ 1) [ 1 + R _{B} / R _{E} ] / 
[( 
+ 1) 
+ R _{B} / R _{E} ] 
Here, replace R _{B} with R _{t}_{h} 

S( I _{C}_{O} ) = ( 
+ 1) [ 1 + R _{t}_{h} / R _{E} ] / 
[( 
+ 1) 
+ R _{t}_{h} / R _{E} ] 
Thus, voltage divider bias configuration is quite stable when the ratio R _{t}_{h} / R _{E} is as small as possible.
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In a fixed bias circuit, I _{C} increases due to increase in I _{C}_{0} . [I _{C} =
I _{B} + (
+1) I _{C}_{0} ]
I _{B} is fixed by V _{C}_{C} and R _{B} . Thus level of I _{C} would continue to rise with temperature – a very unstable situation.
In emitter bias circuit, as I _{C} increases, I _{E} increases, V _{E} increases. Increase in V _{E} reduces I _{B} . I _{B} = [V _{C}_{C} – V _{B}_{E} – V _{E} ] / R _{B} . A drop in I _{B} reduces I _{C} .Thus, this configuration is such that there is a reaction to an increase in I _{C} that will tend to oppose the change in bias conditions.
In the DC bias with voltage feedback, as I _{C} increases, voltage across R _{C} increases, thus reducing I _{B} and causing I _{C} to reduce.
The most stable configuration is the voltage – divider network. If the condition R _{E} >>10R _{2} , the voltage V _{B} will remain fairly constant for changing levels of I _{C} . V _{B}_{E} = V _{B} – V _{E} , as I _{C} increases, V _{E} increases, since V _{B} is constant, V _{B}_{E} drops making I _{B} to fall, which will try to offset the increases level of I _{C} .
S(V _{B}_{E} ) =
I _{C} /
V _{B}_{E}
For an emitter bias circuit, S(V _{B}_{E} ) = 
/ [ R _{B} + (
+ 1)R _{E} ]
If R _{E} =0 in the above equation, we get S(V _{B}_{E} ) for a fixed bias circuit as,
S(V _{B}_{E} ) = 
/ R _{B} .
S(V _{B}_{E} ) =  
/ [ R _{B} + ( + 1)R _{E} ] can be rewritten as, 

S(V _{B}_{E} ) =  ( 
/R _{E} )/ [R _{B} /R _{E} + ( 
+ 1)] 

If ( + 1)>> R _{B} /R _{E} , then 

S(V _{B}_{E} ) =  ( 
/R _{E} )/ ( 
+ 1) 
=  1/ R _{E}
The larger the R _{E} , lower the S(V _{B}_{E} ) and more stable is the system.
Total effect of all the three parameters on I _{C} can be written as,
I _{C} = S(I _{C}_{O} )
I _{C}_{O} + S(V _{B}_{E} )
V _{B}_{E} + S(
)
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