--------------------------------------------------------------1. (a) Design a 4 input CMOS AND-OR-INVERT gate.

Draw the logic diagram and explain the operation with the help of function table. (8M) (b) Analyze the fall time of CMOS inverter output with RL=1KM, VL=2.5v and CL=100PF assume VL as stable state voltage. (8M) 1. (b) Explain how a CMOS device is destroyed. (8M) 1. (a)Draw the resistive model of a CMOS inverter and explain its behavior for low and HIGH inpu (b) Explain the following terms with reference to CMOS logic (8M) i) Logic levels ii) D.C noise margin iii) Power supply rails iv) Propagation delay (8M) 1. (a)Design a CMOS transistor circuit with the functional behavior f(x)= (A + B)(C + D) (8M) (b)Distinguish between static and dynamic power dissipation of a CMOS circuit. Derive the expression for dynamic power dissipation (8M) 1. (a) Design CMOS 4-input AND-OR-INVERT gate. Draw the logic diagram and function table. (b) Draw the resistive model of a CMOS inverter and explain its behavior for LOW and HIGH outputs. [8+8] 1. (a) Explain how to estimate sinking current for low output and sourcing current for high output of CMOS gate. (b) Analyze the fall time of CMOS inverter output with RL = 100, VL = 2.5V and CL = 10PF. Assume VL as stable state voltage. [8+8] 1. (a) Design a 4-input CMOS OR-AND-INVERT gate. Explain the circuit with the help of logic diagram and function table? (b) Explain the following terms with reference to CMOS logic. i. Logic 0 and Logic 1 ii. Noise margin iii. Power supply rails iv. Propagation delay [10+6] 1. (a) Design a CMOS transistor circuit that has the functional behavior as f(x) = (a + c). (b + c) Also draw the relevant circuit diagram (b) Design CMOS 4-input OR-AND-INVERT gate. Explain the circuit with the help of logic diagram and function table? [10+6]

-----------------------------------------------------------------2. (a) Draw the circuit diagram of basic TTL NAND gate and explain the three parts with the help of functional operation. (8M) (b) Explain sinking current and sourcing current of TTL output. Which of the above parameters decide the fan-out and how. (8M) 2. (a) Compare CMOS, TTL and ECT with reference to logic levels, DC noise margin, propagation delay and fan out. (8M)

(b) What is interfacing? Explain interfacing between low voltage TTL and low voltage CMOS logic. (8M) 2 (a) List out different categories of characteristics in a TTL data sheet. Discuss electrical and switching characteristics of 74LS00. (8M) (b) Design a transistor circuit of 2 input ECL NOR gate. Explain the operation with the help of function table. (8M) 2. (a) Design a transistor circuit of 2 input ECL, NOR gate. Explain the operation with the help of function table. (10M) (b)Mention the DC noise margin levels of ECL 10K family. (6M) 2. (a) What is the necessity of separate interfacing circuit to connect CMOS gate to TTL gate? Draw the interface circuit and explain the operation. (b) Design a TTL three-state NAND gate and explain the operation with the help of function table. [8+8] 2. (a) Design a TTL three-state NAND gate and explain the operation with the help of function table. (b) Explain the following terms with reference to TTL gate. i. Voltage levels for logic 1 & logic 0 ii. DC Noise margin iii. Low-state unit load iv. High-state fan-out [8+8] 2. (a) Draw the circuit diagram of basic TTL NAND gate and explain the three parts with the help of functional operation. (b) List out TTL families and compare them with reference to propagation delay, power consumption, speed-power product and low level input current. [8+8] 2. (a) Design a transistor circuit of 2-input ECL NOR gate. Explain the operation with the help of function table. (b) Compare CMOS, TTL and ECL with reference to logic levels, DC Noise margin, propagation delay and fan-out. [8+8]

----------------------------------------------------------------------3. Explain with example the syntax and the function of the following VHDL statements. (a) Process statement (b) If, else and else if statements (c) Case statements (d) Loop statement (16M) 3. (a) Write a data flow VHDL program for the prime number detector of 4 bit input and explain the program using logic circuit. (8M) (b) Explain implicit and explicit visibility of a library in VHDL. (8M) 3 (a) Write a VHDL Entity and Architecture for a 3-bit synchronous counter using Flip-flops. (8M) (b) Explain the use of packages. Give the syntax and structure of a package in VHDL (8M) 3. Explain the following with examples pertaining to VHDL (a) Library (b) type declaration (c) Entity (d) Architecture. (16M) 3. (a) Write a VHDL Entity and Architecture for the following function. F(x) = (a + b) (c _ d)

Also draw the relevant logic diagram. (b) Write a VHDL Entity and Architecture for a 3-bit ripple counter using FlipFlops? [8+8] 3. (a) Discuss the steps in VHDL design flow. (b) Write a VHDL Entity and Architecture for the following function. F(x) = (a+b)(c+d)(e+f) Also draw the relevant logic diagram. [8+8] 3. (a) What is importance of Entity and Architecture in VHDL? Explain with suitable examples. (b) What are the different data objects supported by VHDL? Explain scalar types with suitable examples. [8+8] 3. (a) Write a VHDL Entity and Architecture for the following function? F(x) = a _ b _ c Also draw the relevant logic diagram. (b) Explain the use of Packages Give the syntax and structure of a package in VHDL [8+8]

---------------------------------------------------------------------------4. Design a logic circuit and write a data flow style VHDL program for the following function a) F(Y)=_A,B,C,D(0,2,4,5,8,11,14) +d(7,10,12) b) F(P)= _A,B,C,D(0,1,3,4,5,7,8,10,11,13,15)+d(14). 4. (a)What is the importance of time dimension in VHDL and explain its function. (8M) (b) Explain the behavioral design model of VHDL. 4 Design the logic circuit and write a data flow style VHDL program for the following functions. a) F(X)=_A,B,C,D(1,7,9,13,15) b) F(Y)=_A,B,C,D(1,4,5,7,12,14,15)+d(3,11) 4. Design a logic circuit to detect prime number of a 5- bit input. Write the structural VHDL program for the same. 4. (a) Write a process based VHDL program for the prime-number detector of 4-bit input and explain the flow using logic circuit. (b) Explain data-flow design elements of VHDL. 4. (a) Design a logic circuit to detect prime number of a 4-bit input? Write the VHDL program for the above design? (b) Design the logic circuit and write a data-flow style VHDL program for the following function? F(A,B,C,D)= (1, 5, 6, 7, 9, 13) + d (4, 15) 4. Design a logic circuit to detect prime number of a 5-bit input. Write the structural VHDL program for the same. 4. (a) Explain data-flow design elements of VHDL. (b) Design the logic circuit and write a data-flow style VHDL program for the following function. [8+8] F (X) = _A,B,C,D (1, 4, , 5, 7, 12, 14, 15) + d (3, 11)

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