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Laboratory Work in Analog LSI Circuits.

Laboratory #3, Spring 2000.

Analog LSI Circuits Laboratory Work 3 Cadence Layout Tool

J. Jacob Wikner, jacob@wikner.com

27/1 - 2000

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Laboratory Work in Analog LSI Circuits.

Laboratory #3, Spring 2000.

Refresh Your Knowledge


Refresh the basic principles of CMOS layout. Design rules, concept of using layers, etc. You can nd some chapters about this in Johns&Martin but also in Tan, Allen&Holberg, Rabaey, etc.

Start the Tools


As previously, start cadence and use the same design library as you have done throughout the labs. Note, that there is a new cadence version (4.4.5) and you may have to modify some of your startup scripts and remove the calls to version 4.4.3. First, we design a CMOS common-source amplier. From the rst lab you should already have a schematic view of the circuit. Modify the sizes of the transistors in this view. The PMOS transistor should be 120 um / 1 um and the NMOS transistor 40 um / 1 um. To simplify for the LVS tool - remove all variables in your design. Now, we start with the layout tool. In the library manager, click on your common source cell. Choose File > New > Cellview and let the view name in the pop-up menu be layout. Click OK and Cadence Virtuoso Layout Tool starts. Two windows open. One is the layer selection window (LSW) and the other is the design entry window.

Get-to-know the Layout Tool


Summary: We design some building blocks using the layout editor. For this, we need to understand the concepts of the tool and the process. We run design rule checks (DRC) to check for desing errors. The netlist is extracted from the layout view and compared to the one entered in the schematic view. For this we use the layout vs. schematic tool (LVS). We nd if we have done a proper layout in terms of connectivity. We highlight some important analog layout issues and we use the extraction tool to investigate the parasitic capacitances, etc.

J. Jacob Wikner, jacob@wikner.com

27/1 - 2000

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Laboratory Work in Analog LSI Circuits.

Laboratory #3, Spring 2000.

The Layer Selection Window Obviously, from the LSW you select in which physical layer you want to add a component to the design. For a metal wire, we select for example the MET1 dg layer for the metal layer closest to the silicon surface. With the left mouse button you select the layer, with the right button you toggle the layer between selectable and non-selectable, and with the middle button you toggle between visible and invisible. Note, that we will use the dg and pn layers. The nt layer is reserved for the extracted view. In the LSW we have also two ticks, one for Inst and one for Pin. These can be toggled to make the instances and pins (terminals) selectable or non-selectable. The buttons AV, NV, AS, and NS makes All/No layers Visible/Selectable.

The Virtuoso Layout Editor The layout editor is similar to the schematic editor in terms of interface. However, there are several short-cut keys that are different. Otherwise, there are multiple ways (mouse, menu, quick access bar, etc.) to execute a command. Some useful command are Short-cut Ctrl + r Shift + f Ctrl + f f Right mouse button w Shift + z g F4 k Operation Redraw Displays all levels Displays only the top level Fits the design to the window Hold down and draw a box to zoom this area. Toggles between last few zoom areas Zoom out Toggles the gravity Toggles selectable object edges Ruler for distance measuring

Otherwise, the editor has a rather straight-forward interface. (Dont forget the Escape button).
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J. Jacob Wikner, jacob@wikner.com

27/1 - 2000

Laboratory Work in Analog LSI Circuits.

Laboratory #3, Spring 2000.

The First Design


Now, we rst add two transistors to our design. Use the i button to add an instance. Choose from PRIMLIB the layout view of the cell nmos4. Let the widths be 40 um and the length 1 um. Place the transistor by simply clicking in the window. (Before you place it you are also able to rotate it using the right mouse button). Use f to see the whole design and use Shift + f to see all layers. Identify the different layers and use the LSW to nd out how you can hide layers. Use the k button to use the ruler to measure distances. With Shift + k you remove the rulers. Add a PMOS transistor in the same way, but with the widths of 100 um instead. Place it at a safe distance, say 10 um from the NMOS transistor. By clicking any one of the objects, it is selected. With the q button you are able to modify its properties. Using Shift and the left mouse button you can select several objects. The substrate or bulk connections are added by using the o button. From the different contacts you can
J. Jacob Wikner, jacob@wikner.com

choose the ND_C contact to be placed near the PMOS transistor. The PD_C contact is to be placed near the NMOS transistor. Modify their properties (q) and choose for example as many number of columns needed to make the contacts as wide as the respective transistors. For the PMOS transistor use a contact that is 111 columns wide and for the NMOS it could be 44 or 45. In the gure below a partial plot of the layout is shown. The NTUB layer (crossed light-brown layer) N-diff contact
S
G

NTUB

PMOS

NMOS

P-diff contact

27/1 - 2000

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Laboratory Work in Analog LSI Circuits.

Laboratory #3, Spring 2000.

indicates the N-doped area around the PMOS transistor. We nd that the N-diff contact is overlapping both the N-doped area and the P-doped substrate. Therefore, we have to increase the NTUB area so that it covers the contact as well. This is done by rst selecting the NTUB dg layer in LSW with the left mouse button. Use r to create a rectangle and cover the contact. The NTUB must cover the diffusion of the contact with at least a 0.2 um margin. You can change the size of the rectangle by clicking its edges. If you are not able to do this, toggle this option with F4 and try again. You can move a (selected) object by either pressing m or keeping the left mouse button pressed. Run the design rule checker (DRC) to check the design for errors. Use Verify > DRC... Set the switches to be no_FIMP no_erc. Click OK. Do you have any errors? If you have, you nd a blinking layer in your design and messages displayed in the CIW. To get further information on the errors, choose Verify > Markers > Find... Tick Zoom to markers and apply. A pop-up window explains the errors (sometimes very poor error messages blame AMS). Fix the errors.

If you have not already noticed it, Virtuoso is a polygon-based layout tool. It does not contain the electrical information as the vector-based GDT (Mentor Graphics) does. As soon as two objects of same layer are overlapping or adjacent, they will also be interpreted as connected by the netlist extractor. Now, we connect the bulks to the sources of the transistors. First click the MET1 dg layer in the LSW for the lowest metal layer. Use p to add a path (wire). By double-clicking the middle mouse button the properties of the path can be modied. First, the path is only 0.4 um wide. To make the interconnect wire for the PMOS as wide as the contact, we would need 99.6 um (use the ruler k). If you zoom to the middle of the substrate contact you also nd a small mark indicating the centrum of the contact. Here you can start the path and let it end somewhere on the PMOS contact. For the NMOS transistor we would need a 39.4 um wide wire to cover the contacts. One could use a rectangle r instead to simplify some of the moves.

J. Jacob Wikner, jacob@wikner.com

27/1 - 2000

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Laboratory Work in Analog LSI Circuits.

Laboratory #3, Spring 2000.

The outputs (drains) of the transistors can now be interconnected. This is done in the same way with metal 1. However, the width must not be to wide. Center the transistors (and the contacts) and interconnect with a wire as wide as the drain contact of the NMOS transistor. This is all the interconnection for now. We have to add pins (or terminals) to the design in order to give nets names. Note that the pins do not have the same function as terminals in GDT. Pins are only used by the netlist extractor. First, we will only add a pair of Metal-to-Poly contacts on the gates of the transistors. Choose o and use the P1_C contact. Let the number of columns be 4 and rows 1. Put the contacts adjacent to the gate as shown in the gure below. For the pins, choose Ctrl + p and sym pin. Let the terminal names be AVDD AGND Bias In Out. Tick Display Pin Name and by choosing Display Pin Name Option... set the height of the text to 0.2. Let the Pin Type be given by the layer you are using for the specic terminal/pin. We have added contacts on all of our nodes and therefore we can also access them with the metal 1 layer and hence choose MET1_T. Place the pins in the order specied by the
J. Jacob Wikner, jacob@wikner.com

terminal names. Let the PMOS transistor be the bias transistor. Be sure you put them on the metal. Check the design for errors (Verify > DRC...). Use the switch no_FIMP. From this design we now want to extract the electrical properties, hence the netlist. Use Verify > Extract... and OK. Check if you have any errors reported in the CIW. Go to the Library Manager and you will now for your common source stage nd a cell view called extracted as well. Open it. Display all levels (f and Shift + f)
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27/1 - 2000

Laboratory Work in Analog LSI Circuits.

Laboratory #3, Spring 2000.

and you will nd that the layers look slightly different. The extractor uses layers with the extension nt (look in the LSW). Zoom at the one of the edges of the transistors and you will nd that the extractor has identied a transistor.It also identies the terminal names, etc.

Options. Run. Eventually a pop-up window tells you if the run has succeeded or failed. Either way you can use the Monitor button in the LVS form, tick the current process and choose Command > Show Run Log. If the Run has failed, you may have an error like: Global error: (common-source schematic) in library rst_test has been changed since it was last extracted. This is probably one of the most stupid errors in history of man, thanks to the cadence programmers. However, it can be handled simply by once again saving the specied cell view. Rerun the LVS after that. If the Run has succeeded you will nd a brief report in the run log. It may however be insufcient and therfore open the result le by clicking Output in the LVS form. Now, you may nd that the LVS reports that the terminals in the respective views are not corresponding to eachother, since the names are differing. The most important thing to check is if the number of instances, nets, and devices is equal in both schematic and layout view. Also check that no nets are unmatched.

This extracted view can be compared to the schematic view. Actually, what we do is that we compare the two netlists generated by the tools. Start the layout vs. schematic tool. Verify > LVS... Make sure that the correct libraries, cells and views (schematic and extracted) are entered in the form. Untick all of the LVS
J. Jacob Wikner, jacob@wikner.com

27/1 - 2000

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Laboratory Work in Analog LSI Circuits.

Laboratory #3, Spring 2000.

To make the netlists match exactly, you have to change the terminal names to be equal in both views. (It is most often simpler to change in the schematic view, then you do not have to rerun the extraction, etc.) When you extract the netlist from the layout, you have a number of switches to choose from. Using cap and cap_all you will also extract the parasitic capacitances from the layout. You can open the LVS and select to generate the netlist for the extracted view containing the parasitics. This netlist can with some modications to the AMS process be used in the Spectre simulator in Analog Artist. Unfortunately, in this process, AMS does not support any extraction of wire resistance, etc., only capacitances. As you hopefully have noticed, the layout of the common-source stage is rather stupid since the transistors are large. A wide transistor can be constructed by using a number of smaller transistors in parallel. In the AMS process this is supported more or less automatically. Go back to the layout view and close all other windows.

Click on the NMOS transistor and modify its properties (q). Choose Parameter. Change the MOS transistor shape to interdigit (interdigitized). Let width be 40 u and the number of gates 4. Note that you can tick Substrate contact and cadence adds the bulk connections automatically. Do the same for the PMOS. Let the width be 100 u and the number of gates 10. We are going to add dummy transistors at the edges of the transistors for improved matching of the edge subtransistors. They should be 10 um / 1 um. This can be done in two ways. One is to add four transistors with these dimensions to the existing transistors. Then the drains and sources need to be connected. The second way is to change the size of the original transistors to be 60 um and 6 gates for the NMOS and 120 um and 12 gates for the PMOS. AMS lets us choose to not interconnect the gates, drains, and sources. It can be done manually afterwards. We choose to do it the second way, since then we have automatically added the substrate contacts as well. Let the drain and source of the dummies be shortconnected with the supply (AGND for NMOS, AVDD for PMOS). Let their gates be left unconnected.
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J. Jacob Wikner, jacob@wikner.com

27/1 - 2000

Laboratory Work in Analog LSI Circuits.

Laboratory #3, Spring 2000.

Connect all the sources to the respective supply by using the path command p. Only use one side of the transistors. Double-click the middle mouse button and a pop-up menu toggles. You can now specify the wire width to be 0.6 um. Do the same for all drains on the other side and interconnect them to become the output of the common source stage. You will nd that it is more metal wire on either the supply or the output node. The best thing is to let less metal area be connected to the output since you reduce the parasitic capacitance. If you want to modify a bend or similar on the path, you have to point the center of the path. Then you can move this, delete, or whatever. Be sure that you place the wires on a correct distance according to the design rules. (You can run the Verify > DRC with the switches no_FIMP and no_erc to check). Place metal-to-poly contacts on the gates (only one side). You may have to add a path of poly to bridge the metal 1 supply/output wires. Interconnect the gates with metal 1, 10 for the PMOS to become the Bias input and 4 for the NMOS to become the signal input, In.
J. Jacob Wikner, jacob@wikner.com

Check for errors in your design. An example of layout is shown in the gure on next side, but the transistors can naturally also be rotated 90 degrees for a more rectangular layout. Before you extract the design, you have to consider the dummies. These have to be added to the schematic view as well. Add two PMOS and two NMOS with the 10 um width and 1 um length. Interconnect their drain, source, and bulk with their respective supply. Use a no connection pin on the gates, noConn from the basic library. See the gure on the next side. Note that you in the schematic entry do not have to specify if the transistors are interdigitized, etc. This will not effect the LVS, but it may effect the simulations, since the capacitances associated with the transistors are dependent on the layout style. Extract and run the LVS as was presented previously. Check if you have any errors. To keep the threshold voltage very stable for all subtransistors in the complete transistor, one could add more substrate contacts and basically fence the com9 (16)

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Laboratory Work in Analog LSI Circuits.

Laboratory #3, Spring 2000.

Bias AVDD

PMOS

du

s mmie

Output

du

mm

ies

NMOS

substrate contacts

dummies

AGND Input

J. Jacob Wikner, jacob@wikner.com

27/1 - 2000

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Laboratory Work in Analog LSI Circuits.

Laboratory #3, Spring 2000.

plete transistor in. This will make it possible to attach the supplies from any direction, but it requires that we move to a higher metal layer for the signal wires. It can however be advantegous since the higher metal layers have less resistance/square and less parasitic capacitance to the substrate. However, it may have larger fringing capacitance and also the vias from metal 1 to 2 are resistive and add parasitics. The vias are called VIA_1 for metal 1 to 2 and VIA_2 for metal 2 to 3. All vias may be stacked on eachother. To add this substrate contact ring, we can either choose to place 4 contacts and interconnect them with metal 1 paths, etc. But, fortunately, once again AMS has made it simple for us. In the library PRIMLIB you nd the cells NSUB_PATH and PSUB_PATH. They let you draw a polygon which is transformed into a substrate contact path. In the gure on the side, we show a layout using contacts only (ND_C and PD_C). We have now implemented a common-source consisting of a PMOS and an NMOS. We have used a layout technique (unit elements) to improve local matching of the transistors. We have used substrate rings to guarantee a stable threshold voltage and a guard of the trans-

istors. Now, we will match two transistors with eachother, i.e., global matching.

J. Jacob Wikner, jacob@wikner.com

27/1 - 2000

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Laboratory Work in Analog LSI Circuits.

Laboratory #3, Spring 2000.

Differential Pair
First, create a cellview in your design library. Let it be called diff-pair (or similar) and rst create the schematic view. Add (i) two NMOS transistors of size 120 um / 1 um (nmos4 from PRIMLIB). Interconnect their sources and call this node Common using an input/output pin (p). Connect the bulks to AGND, the gates to Vpos and Vneg, and the drains to Ineg and Ipos.

Instead we are going to use unit elements. In this case use 10 sub-transistors at each 12 um width. For the complete differential pair we would need 20 sub-transistors and a number of dummy transistors. First, add a transistor (i) that is 264 um / 1 um and interdigitized with 22 gates. Do not connect the gates, source, and drain. Do not add the substrate contacts. We can now apply a interdigitized structure to match the two transistors. The outer transistors are the dummies and ignore them for the moment. Since the transistors have a common source connection it is simple to create the matched pair. Identify and intraconnect pairs of adjacent gates, see the gure on the next side. There should be 10 pairs of gates (do not use the dummies). Assume that you connect Vpos to a pair, the transistor contact in-between these gates is the Ineg output and the contacts outside are the common source. Every second pair of gates should then also be interconnected with eachother as well as the common node and the current outputs.

Create the symbol cellview as well. (Design > Create Cellview > From Cellview ...) Create a layout view for the same cell. The rst and naive approach is to place two long transistors close to eachother as we rst did in the previous example.
J. Jacob Wikner, jacob@wikner.com

27/1 - 2000

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Laboratory Work in Analog LSI Circuits.

Laboratory #3, Spring 2000.

Dummy Common Vpos Ineg Common Ipos Vneg Common Vpos Ineg Common A hint is to use the copy command (c). First select an object and then copy. By double-clicking the middle mouse button you get a pop-up menu where you can ll in multiple copies. By clicking the right mouse button you can rotate the objects you are about to copy.

Another tip is to use the de-select commands, d and Shift + d. This is useful when handling several objects. A third tip is to watch the specication on coordinates at the top of the design window. If you select an object and then move it, you will nd the relative distance, etc. For the gates, add poly-to-metal contacts and interconnect them with metal rather than poly. (This may dependent on how large the distances are). Also add metal 1 to 2 vias on top of the poly-to-metal contacts. For the outputs (Ipos and Ineg) assign one side for each node. (Right for Ineg in the example gure). Use metal 1 and be prepared to add vias to change to metal 2. For the common node access it from both sides. Note, that it is rather narrow and you have to use two metal layers for either the output nodes or the common node. For good matching do not cover the transistor gates with metal Not even higher metal layers! Continuously run the DRC to check your design.

J. Jacob Wikner, jacob@wikner.com

27/1 - 2000

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Laboratory Work in Analog LSI Circuits.

Laboratory #3, Spring 2000.

Via Common Vpos Ineg

Add a substrate box around the transistors. Note that it should be connected to the analog ground; add a symbolic pin named AGND. Interconnect all wires outside the substrate ring. Use for example a wide metal 1 wire for the Common node and metal 2 wires for the other nodes. The width of the wires should be given by specications on parasitic resistance, capacitance, the size of the currents oating through them, etc. To illustrate the nal result see the gure on the next side. (Although the wires should perhaps be routed somewhat differently when the differential pair is put in a context, e.g., amplier, etc.) Sensitive wires can also be guarded by encapsulating them by ground wires. Now, we have left the dummies unshorted. Connect the gates and the drains to ground. From the gure below we see that the transistors are still more of a rectangular structure. To minimize the area it is however preferred to (still depends on the

Ipos

J. Jacob Wikner, jacob@wikner.com

Via

Via

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Laboratory Work in Analog LSI Circuits.

Laboratory #3, Spring 2000.

Vpos

AGND

Vneg

context and the whole layout) make the transistor layout as quadratic as possible. Therefore, divide the transistors into two blocks and do a common-centroid layout. This means that you should interdigitize the transistors in two dimensions, in both the x- and y-directions. See Johns & Martin for more information. Note, that a common-centroid transistor pair is more easily laid out if the number of sub-transistors is given by a power of 2. You may therefore either divide the transistors into 16 gates (each 7.5 um) or 8 gates (each 15 um). In the gure on the next page we show an example of a common-centroid transistor pair. The width of each sub-transistor is 15 um. (From the gure, try to understand how it is understood that the transistors are interdigitized in two dimensions). Finally, do a simple PMOS current mirror, where both transistors are 90 um / 1 um. The mirror should be guarded by substrate contacts. Create schematic and

Ipos Common

Ineg

J. Jacob Wikner, jacob@wikner.com

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Laboratory Work in Analog LSI Circuits.

Laboratory #3, Spring 2000.

symbol views. The circuit should be veried with LVS. In the next lab, we shall begin to interconnect the different blocks in a fully-differential operational transconductor. Since it is differential, the requirements on the matching of the transistors are high. Common Vpos

Ipos

Ineg

AGND

Vneg

Common

J. Jacob Wikner, jacob@wikner.com

27/1 - 2000

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