Release Notes For ModelSim SE 6.4c Dec 08 2008 Copyright 1991-2008 Mentor Graphics Corporation All rights reserved.

This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this document may duplicate this document in whole or in part for internal business purposes only, provided that this entire notice appears in all copies. In duplicating any part of this document the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information. TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Mentor Graphics Corporation or other third parties. No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the respective third-party owner. The use herein of a third-party Mark is not an attempt to indicate Mentor Graphics as a source of a product, but is intended to indicate a product from, or associated with, a particular third party. The following are trademarks of of Mentor Graphics Corporation: Questa, ModelSim, JobSpy, and Signal Spy. A current list of Mentor Graphics trademarks may be viewed at www.mentor.com/terms_conditions/trademarks.cfm. End-User License Agreement: You can print a copy of the End-User License Agreement from: www.mentor.com/terms_conditions/enduser.cfm. ______________________________________________________________________ Product Installation and Licensing Information For brief instructions about product installation please visit the "install_notes" file in www.model.com. The install_notes file can be viewed at: [1]http://www.model.com/downloads/default.asp For detailed information about product installation, supported platforms, and licensing, see the ModelSim Installation & Licensing Guide. The manual can be downloaded from: [2]http://www.model.com/support/default.asp How to Get Support For information on how to obtain technical support visit a support page at: [3]http://www.model.com/support/default.asp [4]http://supportnet.mentor.com/ Release Notes Archives For release notes of previous versions visit the release notes archive at: [5]http://www.model.com/support/default.asp or find them in the installed modeltech tree in <path to modeltech installation>/docs/rlsnotes ______________________________________________________________________ Index to Release Notes [6]Key Information [7]User Interface Defects Repaired in 6.4c

[8]Verilog Defects Repaired in 6.4c [9]PLI Defects Repaired in 6.4c [10]VHDL Defects Repaired in 6.4c [11]FLI Defects Repaired in 6.4c [12]VITAL Defects Repaired in 6.4c [13]SystemC Defects Repaired in 6.4c [14]Assertion Defects Repaired in 6.4c [15]Mixed Language Defects Repaired in 6.4c [16]Coverage Defects Repaired in 6.4c [17]General Defects Repaired in 6.4c [18]Mentor Graphics DRs Repaired in 6.4c [19]Known Defects in 6.4c [20]Product Changes to 6.4c [21]New Features Added to 6.4c ______________________________________________________________________ Key Information * PLATFORM AND COMPILER SUPPORT Windows Vista is supported in the 6.4 release. The support includes the following platforms: + 32-bit Windows Vista. SystemC is supported on this platform with gcc-4.2.1-mingw32. + 64-bit Windows Vista is not supported in this release. SystemC has dependencies on C++ compiler versions. In release 6.5, the Solaris and Windows MinGW versions of gcc 3 compilers will be replaced with version 4. This means that gcc-3.3.1-mingw32 and gcc-3.3-sunos5[8 9 10] will not be supported or distributed as of release 6.5. Only the following versions will be supported in 6.5: + gcc-4.1.2-suse9 + gcc-4.0.2-rhe21 + gcc-4.1.2-linux_x86_64 + gcc-4.0.2-linux_x86_64 + gcc-4.1.2-sunos58 + gcc-4.1.2-sunos59 + gcc-4.1.2-sunos510 + gcc-4.1.2-sunos510x86 + gcc-4.2.1-mingw32 In order to facilitate an easy transition for users, both gcc 3 and gcc 4 will be supported and distributed in release 6.4 for Solaris and Windows. Gcc 4.2.1 is a must to run on Windows Vista. The following compiler versions are supported in 6.4: + gcc-4.1.2-suse9 + gcc-4.0.2-rhe21 + gcc-4.1.2-linux_x86_64 + gcc-4.0.2-linux_x86_64 + gcc-4.1.2-sunos58

+ gcc-3.3-sunos58 + gcc-4.1.2-sunos59 + gcc-3.3-sunos59 + gcc-4.1.2-sunos510 + gcc-3.3-sunos510 + gcc-4.1.2-sunos510x86 + gcc-3.3-sunos510x86 + gcc-4.2.1-mingw32 + gcc-3.3.1-mingw32 Support will be discontinued for the following operating systems in the 6.5 release. + Windows 2000 + Linux Itanium Support was discontinued for the following operating systems in the 6.4 release. + RedHat 7.2 + RedHat 7.3 + RedHat 8.0 + RedHat Linux Enterprise 2.1 If you attempt to run vsim on any of these platforms or on the Linux 2.4 kernel the following error message will be displayed: $ vsim <install_dir>/bin/../linux/vish: /lib/i686/libc.so.6: version `GLIBC_2.3' not found (required by <install_dir>/bin/../linux/vish Or when you load a design you will get: $ vsim top <install_dir>/linux/vsimk: /lib/i686/libpthread.so.0: version `GLIBC_2.3.2' not found (required by <install_dir>/linux/vsimk) For a complete list of supported platforms and SystemC compilers see the Installation and Licensing Guide under the section Supported Platforms. * PRODUCT SUPPORT The profiling feature is now supported on the linux_x86_64 platform. The LE product does not support VHDL. However, it does support Verilog and SystemC. This release includes a new dongle driver installer for Windows. The new dongle driver versions that will be installed are as follows: + Aladdin (FLEXID=9-) driver version 4.96 + Dallas (FLEXID=8-) driver version 3.2.1.11 + Sentinel (FLEXID=6-)/(FLEXID=7-) driver version 5.41 The new dongle driver installer will install these drivers only if they are newer than the currently installed dongle drivers on your Windows system. COMPILATION COMPATIBILITY You must recompile or refresh your models if you are moving forward from 6.3x or earlier release versions. See "Regenerating your design libraries" in the User's Manual for more information on refreshing your models. Optimized designs created explicitly with vopt in 6.3a through 6.3c will not be compatible with 6.3d, and will give a "version is out of date" error if versions are mixed. Optimized designs created explicitly with vopt in 6.3 need to be regenerated for the 6.3a release by re-running vopt. The format of the library contents file (_info file) has been changed for the purpose of improved compiler performance. The new format is not backwards compatible with previous releases. Consequently, any attempt to refresh or recompile a 6.3 library with an older release will result in an error similar to the following: ** Error: (vcom-42) Unsupported ModelSim library format for "./work".

(Format: 3). Converting the library back to an older release requires that you remove the library and rebuild it from scratch. Or, if you are converting back to a 6.2 release only, then you can convert the library format to the 6.2 format and then freely refresh back and forth between 6.2 and 6.3 releases. Use the 6.3 version of vlib to convert the format to the 6.2 version using the -format option. For example: vlib -format 1 work The format version for pre-6.3 releases is 1, while the format version for 6.3 is 3. Format version 2 is related to libraries created with the -archive option and should be avoided when specifying the vlib -format option. In some complex circumstances the code generated for SystemVerilog packages with vlog versions 6.2 through 6.2d caused compilation or simulation problems. If the design imports a SystemVerilog package that was compiled with a previous version and which contains potentially incorrect code, the user will be required to refresh or recompile the package. If a VHDL model contains signal declarations using signal kinds BUS or REGISTER or port declarations using kind BUS then that model may produce misleading error messages if it was compiled with a 6.2b or earlier compiler. If such a model is simulated with the current simulator, the following incorrect error message is produced in certain cases: # ** Fatal: (vsim-3992) Illegal assignment of null waveform in a subprogram to a non-guarded actual 'mux_out'. To avoid this misleading error messages recompile the model with the current compiler. The vcom compiler default language has been changed from VHDL-1987 to VHDL-2002. To choose a specific language version: * select the appropriate version from the compiler options menu in the GUI, * invoke vcom using switches -87, -93, or -2002, or * set the VHDL93 variable in the [vcom] section of modelsim.ini. Appropriate values for VHDL93 are: + 0, 87, or 1987 for VHDL-1987; + 1, 93, or 1993 for VHDL-1993; + 2, 02, or 2002 for VHDL-2002. LICENSING The 6.4 release uses the following licensing versions: FLEXnet v10.8.5; Mentor Graphics Licensing MSL v2007.3 with MGLS v8.5_0.5 and PCLS 2007.291. For this release of the product, the FLEXnet licensing software being used is version 10.8.5. For floating licenses it will be necessary to verify that the vendor daemon (i.e., mgcld) and the license server (i.e., lmgrd) have FLEXnet versions equal to or greater than 10.8.5. The vendor daemons and lmgrd that are shipped with this release will be FLEXnet version 10.8.5. If the current FLEXnet version of your vendor daemon and lmgrd are less than 10.8.5 then it will be necessary to stop your license server and restart it using the vendor daemon and lmgrd contained in this release. If you use node locked licenses you don't need to do anything. Use the following license versions: * FLEXnet v10.8.5 * MSL v2007.3 * MGLS v8.5_0.5 * PCLS 2007.291

GENERAL INFORMATION Support for PDF files on the Solaris x86 platform is limited. Adobe has not shipped a PDF reader for Solaris x86 since version 4.05 and no longer supports that version. Some third-party readers are available, including GNOME PDF and xPDF which ships with the Solaris x86 companion DVD. If you still cannot access a PDF version of a document, you can go to SupportNet using a non-Solaris x86 UNIX-based system, a Linux-based system, or a Windows-based system to view Mentor Graphics PDF documentation. The vlog, vcom and vopt command line options are now case sensitive which makes them consistent with the vsim command line options. The default time unit for SystemC can be set using the "ScTimeUnit" variable in the modelsim.ini file. By default ScTimeUnit is set to 1 ns. The default time unit in SystemC can also be set using the sc_set_default_time_unit() function before any time based object like sc_clock or sc_time is created. Starting in the 6.1 release, the vsim -dpiexportobj option has changed behavior. This primarily affects Windows and AIX platforms. The changes are listed below: * An extension is now automatically added to the object filename. * There is no longer a need to add "-c -do 'quit -f'" to the vsim -dpiexportobj command line. The examples/systemverilog/dpi/simple_calls runtest.bat files have been modified to show the correct flow. Beginning in the 5.8 release, SDF files compressed in the Unix compress format (.Z) are no longer supported, but the GNU zip format (.gz)is supported. Therefore, we only read in compressed SDF files that are created with the GNU zip (gzip) extension. A file is not require to have a .gz extension, but it will error on files that have a .Z extension. Beginning with the 5.6 release (on Windows platforms only), attempts to link in libvsim.lib or tk83.lib using the Microsoft Visual C++ linker version 5.0 will fail with a message similar to: "Invalid file or disk full: cannot seek to 0xaa77b00". Microsoft Visual C++ version 6.0 does not have this problem. Acrobat reader version 4.0 or greater must be used to read any .pdf file contained in version 5.5c or greater. The following browsers are unsupported for the HTML documentation: * Netscape versions 4.x and 6.x * Opera versions 6.x and 7.x We regret we cannot support these browsers for use with the HTML documentation. We recommend upgrading to a new browser: Sun Solaris: Upgrade to Mozilla: * http://www.mozilla.org/ * http://wwws.sun.com/software/solaris/browser/index.html Linux: Upgrade to Mozilla: * http://www.mozilla.org/ Windows: Upgrade to Netscape 7.2 or newer, Internet Explorer, or Mozilla: * http://browser.netscape.com/ns8/download/default.jsp * http://www.microsoft.com/windows/ie/default.mspx/ * http://www.mozilla.org/ ______________________________________________________________________

User Interface Defects Repaired in 6.4c * In some windows the Find dialog short cut did not work when the window is undocked. * The children of an expanded SystemVerilog unpacked array of 2-state elements did not display correctly in the Wave window. * WLF scanning with transactions could report false values for some non-transaction items. This was visible in the Wave window or with 'examine -time ...', for example. This would occur after the end of the scanned data or in places where logging was disabled for the item. The value should have been reported as "No_Data". In addition, this fix includes changes so that transaction stream and attribute values are "No_Data" after the end of the WLF data. * The compile status for project files was not showing. This issue is now fixed. * The add_menu procedure failed when used in a scenario like this: "set w [toplevel .paper]; add_menu $w File". * The trailing characters of long signal names were sometimes truncated in the Wave window. * Context-menu item "Save Files..." restored to "Files" pane... emits a sorted duplicate-free list of all the files used in the design (based on "write report"). * Long environment pathnames (i.e. contexts) shown in the GUI's footer area were difficult to see because they were left justified. This has been fixed to make sure the leaf portion of the path is always visible. The full path can be seen by hovering the mouse pointer over the footer, which displays the path in a tooltip. ______________________________________________________________________ Verilog Defects Repaired in 6.4c * The compiler crashed generating code for a bitwise infix expression having a hierarchical reference as one operand and a comparision operator that folds to a constant as the other operand. * There were differences between the iopath selection for notifier generated X outputs from optimized gate-level cells when +delayed_timing_checks is in use. * An out-of-bounds index into an array of vector nets resulted in a simulator elaboration crash rather than an error message. * An event control on an indexed hierarchical reference within a task declared in a class resulted in the following false error from the compiler if the index referenced a class member variable: ** Error: testfile(5): Illegal assignment expression in event control. * SDF annotation crashed when used with +delayed_timing_checks. * Using ## in a nested module where the default clocking block is declared in the parent module incorrectly reported error that the default clocking block was not found. * vopt produced an internal error when optimizing a module containing a part select or bit select of a port where the port size did not match the port size of the parent module. * Calls involving STDOUT and STDERR in $fflush might have resulted the error message: # ** Error: (vsim-PLI-3085) t.v(4): $fflush : Argument 1 is an unknown file descriptor. * Calling process::kill() for an always block process failed to stop the always block from executing in some cases. * When an automatic variable was only used as an array index inside a fork..join block in an automatic task or function, an incorrect array index was calculated in some cases. * vopt no longer crashes when referencing a non-existant task imported from a virtual interface.

* When $setuphold/$recrem timing checks occurring without explicit delay net specifications and +delayed_timing_checks is used, the delay net solution may not solve correctly. ______________________________________________________________________ PLI Defects Repaired in 6.4c * Some problems with the -learn option have been fixed. These include fixes for intermittent crashes with vpi_put_value()and signalspy learning under certain conditions; and a fix for an infinite loop for some VHDL escaped identifiers. ______________________________________________________________________ VHDL Defects Repaired in 6.4c * vopt would incorrectly not re-optimize a design unit if one of it's instances changed. For this to happen the lower instance needed to be instantiated within a block, for generate, or if generate scope. * Alias to composite signal parameter could cause the simulator to crash when the parameter's subprogram is called. * An elaboration time crash could occur when using block ports. The block port must be a vector that is constrained by a generic on the block and the port must be initialized with a constant literal. * If a configuration is used to bind an instantiation with a port map which uses signals declared in the generate declaration region sometimes a crash is observed. This has now been fixed. * If a constrained port declaration had different bounds than the actual connected to the port, the actual's array bounds would be incorrectly used by the GUI as the port's array bound. ______________________________________________________________________ FLI Defects Repaired in 6.4c ______________________________________________________________________ VITAL Defects Repaired in 6.4c ______________________________________________________________________ SystemC Defects Repaired in 6.4c * A sc_fifo of a class containing only a sc_uint would lead to a crash if N is not a power of 2. This is fixed. ______________________________________________________________________ Assertion Defects Repaired in 6.4c ______________________________________________________________________ Mixed Language Defects Repaired in 6.4c * If vsim issued an error while elaborating a SystemVerilog bind statement with a VHDL target, restarting the simulation using the restart command would make vsim crash. This has been fixed. * When SystemC control_foreign_signal/observe_foreign_signal was invoked with a non-existant HDL signal, the error message issued would not stop simulation, or produce non-zero code after elaboration. Even raising the severity level of the error message to fatal would not stop simulation. This has been fixed, and now this error message has been converted to a warning message. Raising the severity of this message to error/fatal will now make the simulation stop. * Using net-type (wire ) of a multi-dimensional array at the SystemVerilog-VHDL mixed-language boundary would sometimes result in an incorrect type-mismatch error in vsim. This has been fixed. * vgencomp would not generate correct datatypes for ports of SystemC type double and float in the generated component declaration. This has been fixed.

* Type-compatibility checks for unions would be skipped at the SystemC-SystemVerilog mixed-language boundary when a SystemVerilog array of unions is connected element-by-element to a SystemC array of signals of type union. This has been fixed. * When a SystemVerilog bind construct is used to bind output ports of the Verilog module to an input port of the VHDL target, vopt would issue an incorrect error message while vsim would simulate the design producing correct results with -novopt. This has been fixed, and now vopt does not generate the incorrect error message. * scgenmod would generate an internal error when invoked on SystemVerilog interfaces. This has been fixed. * Binding to Verilog targets, using the SystemVerilog bind construct, would make vsim crash when vopt was invoked with the +acc=p option and the port-map contained a hierarchical reference as the actual expression. The same testcase would produce correct simulation results when vsim was invoked with -novopt command-line option. This has been fixed. ______________________________________________________________________ Coverage Defects Repaired in 6.4c * The toggle add -exclude command resulted in an irrelevant error message if the signal in question is not a vector. The fix checks whether the signal passed to the command is a vector and shows a meaningful error message in case of a scalar signal passed. * Aggregate evaluation during FSM extraction would sometimes result in a crash in vopt. This has now been fixed. * Toggle with escaped names were not expandable in the Toggles tab in the Missed Coverage window. * The following checkbuttons are added in the Advanced Options dialog of the Coverage Text Report to turn off printing coverpoint and cross summary lines. + No Coverpoint Summary + No Cross Summary * Fixed Tcl error in transcript when a design is loaded in GUI without coverage from a loaded vsim with coverage where the Source window is displayed. ______________________________________________________________________ General Defects Repaired in 6.4c * A crash would occur if the user attempted a second restart after the first restart failed during elaboration. * Sometimes after a restart, zoom full in the Wave window would not work until the window was resized or otherwise refreshed. * The vlib -format 1 <library> command could not be used to convert a library format backwards for use with a pre-6.3d release. This has been fixed, provided that the library format is first converted and then "refreshed" with the -refresh option of the compiler using the current release, and then refreshed again with the older release. ______________________________________________________________________ Mentor Graphics DRs Repaired in 6.4c * dts0100378184 - Problems with ctrl-f "Find". * dts0100493545 - Assertion options need disabling in viewcov mode. * dts0100514333 - Zoom full button (for wave pane or window) does not work after a reload. * dts0100523934 - The specified object could not be found in the design, message does not trigger error/fatal. * dts0100526454 - Crash using incremental compile and restart in vopt mode. * dts0100526570 - Issue with null dereference with 6.4.

* dts0100528917 - 'vlib -format' operation doesn't appear to function. * dts0100536014 - VHDL generate/procedure/alias results in a segfault. * dts0100536814 - Vsim error depending on the order of declaration of an interface. * dts0100541639 - When using projects: Under "Status" field in "Projects" tab, cannot see the regular status icons (X or ? or tick). * dts0100543247 - vopt crash in aggregate evaluation during FSM extraction. * dts0100543528 - Truncated signal paths in the Wave window. ______________________________________________________________________ Known Defects in 6.4c * On Windows platform, If Destructor breakpoint on SystemC object is set via command "bp -c < function_name >", Debugger sometimes does not stop at the breakpoint. * On Windows platform, if breakpoint is set on a SystemC object destructor, Debugger sometimes crashes while quitting simulation. This crash can be avoided by setting env variable SC_NO_LIB_UNLOAD, which will prevent unloading of the shared library. * The viewcov mode version of "coverage clear" has a known difference in behavior compared to the vsim mode version. In the viewcov mode version, clearing coverage data in a design unit instance does not affect the coverage data for that design unit, itself. Also, if you clear coverage data in a design unit, all instances of that design unit are not affected by that operation. In vsim mode, the data is more tightly linked such that one operation affects the other. In viewcov mode, if you want to have correct data correlation between instances and design units, then you need to clear both instances and design units. * The simulator will hang if it tries to create a WLF file while running on a Linux 64-bit operating system from a working directory which does not support large files. One common instance of this is executing an add wave command, when the working directory was created under an older 32-bit Linux OS. This is a Linux operating system bug and cannot be fixed by the simulator. A workaround for release 6.3 and above is to execute the simulator with command line option -wlfnolock. * The stack unwinder on the linux_x86_64 OS is unreliable. The unwinder is the fundamental facility provided by the OS for sampling where program execution is at. The unwinder is necessary for gathering performance data. This is a known issue with this specific OS and is why performance data will be incorrect or non-existent on this platform. * Users should be mindful of enabling both performance profiling and memory profiling at the same time. Memory profiling requires much overhead process, and it can skew the results of the performance profiling data. * On certain (RedHat) Linux Operating System versions the "-restore" feature occasionally fails. This is due to the memory allocation security (anti-hacking) feature of Linux. RedHat Enterprise release v.3 update3 was the first version to have this security feature. In these Linux releases two consecutive program invocations do not get the same memory allocation foot-print. For the "-restore" feature the simulator relies on having the same memory allocation foot-print. Users are advised to re-try this feature a few times as on average 3 out of 5 attempts are successful. In recent Linux versions, an override for this anti-hacking feature is provided. Please use it at your own discretion. * In code coverage, there is no way to exclude a condition or expression table row for the case of more than one table on a line and the table in question is not the first table on the line. * Support of debugging C code during a quit command was disabled on

Windows. The corresponding C Debug command cdbg stop_on_quit was also disabled on Windows. * Specparams can be learned during the learn flow, but cannot be found on consumption. The workaround is to use full +acc deoptimization. * On Red Hat Enterprise Linux release 5 platform, If SIGSEGV signal occurs during the simulation and if CDEBUG is on, C-debugger traps the signal, and when continued, vsim gets terminated right away, instead of exiting with proper error status. * vlog will now print an "unsupported" error message for nested design-units, as this feature is not fully supported in 6.3. This error may be suppressed using the -suppress 2230 command-line options. * For viewing events in Expanded Time in the List window, use the "configure list" command with the "-delta events" option. "events" is added to the "all", "collapse", and "none" options for the "-delta" argument. These options control the details shown in the List window and in writing list files. This was documented incorrectly in the "Expanded Time Viewing in the List Window" section of the "Waveform Analysis" chapter of the User's Manual. The "write list -events" command serves a different purpose (which has not changed) and is NOT used to control Expanded Time viewing in List window. * The "examine", "searchlog", and "seetime" commands have NOT been enhanced for use with Expanded Time. This was documented incorrectly in the "Expanded Time Viewing with examine and Other Commands" section of the "Waveform Analysis" chapter of the User's Manual. * If you have code coverage on in VHDL and get the following sort of warning: # Loading mypackage(body) # Internal Warning in process_sub: failed to find local inlined subprogram called in pkg # (mypackage ); flags 7 filenum 0 lineno 241 tokno 2 # Disabling code coverage for this inlined subprogram Then add the -noFunctionInline option to vcom for that package, or reorder the subprograms in the package body to be defined before they are used. * Code coverage is now giving results for SystemVerilog nested modules, interfaces and program blocks. One remaining issue is that if a nested module has more than one instance, only one of the instances will show code coverage data, and the data therein will be the sum of all the instances of that module. This will be improved in a later release. * Using the profiler on Solaris 8 can result in the error, "Setitimer: Permission denied." To prevent this error, set the environment variable MTI_THREAD_DISABLE to 1. ______________________________________________________________________ Product Changes to 6.4c * The priority of +initreg/+initmem options is adjusted from the previous versions. Now, the +initreg/+initmem options specified to vopt with design unit or instance name have the highest priority. After that, these options applied to vlog have the next priority and the vopt +initreg/+initmem options have the last priority. In earlier versions, the +initreg/+initmem options specified to vlog command had higher priority than design unit or instance specific +initreg/+initmem vopt options. * To improve usability, the Run toolbar has been changed: a Break button has been added. * The text-based windows (Transcript, Notepad and Source) now have an "inline" search bar (instead of a dialog box) which supports incremental searching. The previous behavior can be restored using the "Main/InlineTextSearch" option. * Several fatal elaboration errors will now print the line # where the

error occurred. * The new enhanced support of analog format within the Wave window includes a change to the output created by "write format wave". In pre-6.4 the output for the "add wave" commands would include "-offset" and "-scale". Starting in 6.4 the output will instead use "-min" and "-max". * When vpi_iterate and vpi_scan are used on an array of instances, the individual elements will now be returned left-to-right, where they formerly were returned low-to-high. For example if they are applied to "mymodule u1[2:0]();", the elements returned will be u1[2], u1[1], u1[0]. * Each tag in a taglist (used as data extraction parameters) may now include a subset of the XPath syntax to identify elements not only by tag name but also by the contents of attributes attached to said elements. This pseudo-Xpath syntax only handles "=" and "!=" and can only examine the attribute values attached to the element being compared. Moreover, only one attribute comparison may be performed. For example, the following extraction parameter: "-starttags Worksheet[@ss:Name=Sheet1]" will match the following element in the incoming XML: <Worksheet ss:Name="Sheet1">...</Worksheet> but will not match the following element: <Worksheet ss:Name="Sheet2">...</Worksheet> * The behavior of several extraction parameters in the XML Import utility has been clarified to allow various parameters to work more independently. The affected parameters are: starttags, stoptags, excludetags, and startstoring. * VCD extensions for SystemVerilog supported as per Section 24: VCD Data in IEEE-P1800. LRM is not extending VCD for interfaces and programs. They will be dumped as "module" scope. * The source window has been changed to remove the separate column used to display breakpoints. Breakpoints will be shown within the "line number" column (as they were in the pre-6.3 releases). The LMB event handling has been improved to avoid inadvertant setting of breakpoints. Also, there is now a subtle visual separator bar between the text area and the line number column to help guide the user during text selection. * The coverage numbers shown in the source window can appear to be in conflict with what's shown in the "Missed Coverage" window. This occurs when the Missed Coverage window is in "By Instance" mode and the source window is in "By File" mode. The latter is the default for the source window but it gives no indication what its current mode is. To make it clear for the user, the title bar of the source window will be enhanced to include the current coverage data mode(either "by file" or "by instance"). * The Contains toolbar now supports multiple wildcard modes. The default mode is now "glob" style which is the more common form of wildcards as found in UNIX shells. The wildcards are *, ?, [chars], and \x where x is any character, removing that character's special meaning. Previously, this filtering tool used full regular expressions. This option is selectable from the menu button in the Contains entry box, by selecting the value "regular-expression". The third option, "exact", does not use wildcards so no characters have any special meaning. In all modes, the search patterns are considered case insensitive. If a case sensitive pattern is needed, use the regular-expression mode and perpend the search string with "(?c)". The preference variable PrefMain(ContainsMode) defines the filter mode for all windows with one of the values of "glob", "regexp", or "exact". More information on regular expressions can be found in the Tcl reference manual under "re_syntax". Information on glob style matching

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can be found in the Tcl reference manual under the "string match" command. Macro arguments to Verilog and SystemVerilog macros are now expanded prior to substitution into the macro body. SDF annotation of RECREM or SETUPHOLD matching only a single setup/hold/recovery/removal timing check will result in a warning message. The transaction recording engine no longer issues a warning if a design attempts to record a transaction of zero length. The log and nolog commands are now supported for transaction streams of all kinds. TR streams created through the SCV or Verilog APIs have logging enabled by default. The rule is that a transaction will be logged in WLF if logging is enabled at the simulation time when the design calls ::begin_transaction() or $begin_transaction. The effective start time of the transaction (the time passed by the design as a parameter to beginning the transaction) does not matter. Thus, a stream could have logging disabled between T1 and T2 and still record a transaction in that period using retroactive logging after time T2. A transaction is always entirely logged or entirely ignored. PSL LTL and OBE operators are now disabled by default. Use -pslext vcom/vlog/vopt switch to enable these operators. The Win32/Win32PE platform executables (excluding vish.exe) are now linked with the /LARGEADDRESSAWARE switch. This switch allows an executable to allocate an extra gigabyte of process space (up to 3GB). The additional gigabyte of process space is available on Windows configurations that include the /3GB (/userva on Vista) boot switch. Vish.exe is not linked with /LARGEADDRESSAWARE and we do not recommended that this switch be used with vish.exe. Testing vish.exe with this switch exhibited a tendency to exceed the one GB system limitation which results in a crash. When the simulator's GUI displays several windows with large amounts of graphical data and a full redraw occurs, a temporary surge in the allocation of system memory can cause the limit to be exceeded. The behavior of virtual expressions has changed in a subtle way. Normally when a virtual expression contains a relative context pathname, for example u1/x2/b, the current context would be used in order to resolve the name. However, relative paths that started with a toplevel name would also be recognized, ignoring the current context. This unintended behavior has been corrected so that the current context is always used to resolve a relative name. This may cause some previously accepted virtual expressions to fail to be accepted. modules found through source library search are no longer treated by default as if they contained a `celldefine compiler directive. To obtain the old behavior, add +libcell to the vlog command line. Source library search is enabled with -v and -y compilation options. Whether a module is considered a cell or not affects logging defaults with log -r *, coverage defaults within the module, and PLI access routines acc_next_cell and acc_next_cell_load. This change simplifies migration from other simulator products. Support for Verilog hierarchical references through VHDL design units has been greatly improved. It is now possible for hierarchical references from a higher level Verilog to refer to objects in a Verilog module instantiated beneath a VHDL design unit. In previous releases, upward references from a lower level Verilog module would only work if the target's scope was a direct parent, or a silbing that was instantiate lexially earlier in source. This restrictions are now removed. Hierarchical references that pass through a VHDL design will not work in the follow cases: + Is the target of a defparam. + Used as an actual to a unconstrained VHDL port.

+ Target of the reference is a VHDL object. * A new toolbar has been added to the Wave window for access to the existing Bookmark functionality. * Enabled use of the "contains" filter for the Files tab of the Workspace window. * Support for some additional VPI features has been added in this release. The vpiDriver transition has been extended, and partial support for vpiContAssign objects has been added. * When encrypting Verilog source text any macros without parameters defined on the command line are substituted (not expanded) into the encrypted Verilog file. * Wave searches initiated from the keyboard or toolbar buttons can now be stopped by clicking the Wave window's "Stop Wave Drawing" toolbar button or the Simulation toolbar's "Break" button. * The SystemVerilog array manipulation methods now reflect the latest changes in the P1800 Draft5 version of the LRM, in that iteration occurs only in the top dimension of the array. That is, the correct way to sum the elements of a 2-dimensional memory, as indicated in the LRM's example, is: logic [7:0] m [2][2] = '{ '{5, 10}, '{15, 20} }; int y; y = m.sum with (item.sum with (item)); // y becomes 50 => 5+10+15+20 Previously, ModelSim iterated through all the unpacked dimensions, "[2][2]" in this case. * When using C-debugger to debug quit callback functions, user needed to turn on 'stop on quit' mode. User start debugging by issuing 'quit -f' command. When simulation ends, user needed to quit C-debugger using 'cdbg quit' and then GUI using 'quit -f'. Now, Users do not need to issue extra commands at the end of the run. Simulator automatically quits C-debugger and GUI, after debugging is done and simulation has stopped running. * If a VHDL signal is read during elaboration the value read may differ from value read in previous releases. The VHDL LRM considers this illegal(Section 12.3) but tool behavior has always been to just warn and allow a value to be read. What the value read has always been undefined. Additionally previous releases allowed functions and procedure with signal parameter to be called during elaboration. This is now illegal and reported at compile time. * The menus which control the functional coverage tab display options (assertion, cover directives and functional coverage) have changed slightly. Most significant of the changes is that each pane now has a separate control for "Show All Contexts" and "Recursive Mode" that is not shared with the other panes. They are available with the right mouse click popup window as well as under the tool's main menu, under the "Display Options" menu pick. * The bp command now outputs a list of existing C breakpoints with their enabled/disabled states in the bp command syntax, so that this output can be saved and executed later to recreate the breakpoints. * The effect of assertions on some coverage features has changed. Because asserion pass counts were not reliable without -assertdebug used in simulation, pass counts have been removed from the coverage database and reports by default. (With -assertdebug, they remain, along with other counts.) Also, the contribution of assertions to total coverage -- in the Verification Management Tracker and Browser -- has changed. Previously, an assertion contributed to "100% coverage" if it non-vacuously passed at least once. Now, with -assertdebug, "100% coverage" is met if an assertion both non-vacuously passed and never failed. Without -assertdebug, "100% coverage" is met if the assertion never failed. There is a new VM Browser column called "%SuccessAsserts" to indicate this statistic. If assertions are included in a test plan,

this statistic is automatically used in the VM Tracker and "coverage analyze" command. * Following modifications have been done to coverage switches: Earlier name New name -coverNoSub -nocoversub -nocoverNoSub -coversub -coverExcludeDefault -coverexcludedefault -nocoverExcludeDefault -nocoverexcludedefault -fsmnoresettrans -nofsmresttrans * Errors involving unpacked array assignment, where the packed elements do not match exactly (signed/unsigned, different widths, 2-state/4-state), may now be suppressed using '-suppress 7034'. * The HTML report now shows the total number of covergroup bins per coverpoint or cross and, of those, how many were covered. This information appears on the covergroup details pages for each scope. * When the simulation encounters an error during a run, a message will be displayed showing the file and line location of the error and the sequence of calls showing how it got there. This is an extension of the Stopped At message displayed previously. In GUI mode, this message may be used to view the file by double-clicking on the file name in the message. This message may be suppressed by setting the PrefMain(noRunMsg) preference to 1. * The assertion gui panel now will save the state of the display option settings when the simulation exits. * The vsim -title switch can now be used with the -load_elab switch. Previously this option was disallowed. ______________________________________________________________________ New Features Added to 6.4c * A new argument -item has been added to the coverage exclude command. This is to allow exclusions to be finer grained than by line. Now, if a source line contains more than one coverage item, the user can selectively apply exclusions for a subset of them. Coverage types affected by this change are statements, branches, expressions, and conditions. Items are numbered in left-to-right order within a line -regardless of nesting -- from 1 upward. Item numbering is per type. So, if a source line contains two statements and two branches, the first of each type will get an item number of 1. The syntax for the new item argument is as follows: -item [bces]* [int int-int]+ A limitation on the use of item is that a single invocation can have at most one item argument. The item argument can be mixed with other arguments of coverage exclude command.

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