A PROJECT REPORT ON

METRO TRAIN PROTOTYPE MODEL WITH LCD DISPLAY AND BUZZER SYSTEM
Submitted in the partial fulfillment for the award of

The Degree of Bachelor of Technology in

ELECTRONICS & COMMUNICATION ENGINEERING

SUBMITTED NIDHI NAGAR NITESH KUMAR PATEL PRAGYA KUSHWAHA SUNITI GARG

BYROLL NO. 0503331070 ROLL NO: 0503331072 ROLL NO: 0503331085 ROLL NO: 0503331112

Under the Guidance of-

MS. KALPANA SHARMA

Department of Electronics & Communication Raj Kumar Goel Institute of Technology Ghaziabad (U.P.), India

CONTENTS
1. Introduction of Metro train prototype 2. Component description I) MICROCONTROLLER II) LED& STEPPER MOTOR III) VOLTAGE REGULATOR IV) LCD DISPLAY & DIODE V) POWER SUPPLY& TRANSFORMER VI) RESISTOR & CAPACITOR VII) BUZZER 3. Working of project 4. Cost analysis of components used 5. Assembly program 6. PCB designing and working 7. Memory and Register Unit 8. Timer and counter 9. 8051 Instruction set 10. The Complete Microcontroller System 11. Development Tools 12. Problem faced 13. AT89C52 Description 14. Major applications& Future scope 15. Bibliography

INTRODUCTION OF METROTRAIN PROTOTYPE

This project is designed so that students can understand the technology used in the now a days driver less metro train which is used in most of the developed countries like Germany, France, and Japan etc. These trains are equipped with the CPU, which control the train. The train is programmed for the specific path. Every station on the path is defined; stoppage timing of the train and distance between the two stations is predefined.

In this project we try to give the same prototype for this type of trains. We are using microcontroller 8051 as CPU. The motion of the train is controlled by the Stepper Motor, for displaying message in the train we are using Intelligent LCD Display of two lines. The train is designed for three stations, named as Aligarh, Ghaziabad & New Delhi. The Stoppage time is of 3 Sec and time between two consecutive stations is 6 sec. There is a LCD display for showing various messages in the train for passengers. There are indicators, which are used to show the train direction i.e. Up path and Down path. Before stopping at station the train blows the buzzer. It also includes an emergency brake system due to which the train stops as soon as the brakes are applied and resumes journey when the emergency situation is over. This paper describes a prototype that has been developed to demonstrate the concept of integrated gaming and simulation for incident management. Architecture for the purpose was developed and presented at the last conference. A hypothetical emergency incident scenario has been developed for demonstrating the applicability of integrated simulation and gaming. A number of simulation and gaming modules have been utilized to model the major aspects of the hypothetical scenario. The modules demonstrate the value of utilizing simulation for incident management applications. They can be used to highlight the value of simulation and gaming for training applications in particular. Two of the simulation modules have been integrated using a modified implementation of the high level architecture to give an idea of the advantages. Technical issues in integration are identified.

INTRODUCTION OF EMBEDDED SYSTEM

WHAT IS EMBEDDED TECHNOLOGY? Embedded technology is software or hardware that is hidden embedded in a large device or system. It typically refers to a fixed function device, as compared with a PC, which runs general purpose application. Embedded technology is nothing new. It all around us and has been for years. An early example of embedded technology is the engine control unit in a car, which measures what setting to give the engine. Your coffee maker has embedded technology in the form of a microcontroller, which is what tells it to make the coffee at 6 a.m. the vending machine has it too. Overall, billions of devices woven into everyday life use embedded technology. In the past embedded technology existed in standalone device vending machines and copiers that did their jobs with little regard for what went on around them,. But as technology has learned to connect device to the internet and to each other, embedded technology potential has grown. Suddenly it is and what actions those connections let them perform. Cell phone companies figured that out a long time ago, which is why cell phones are cheap and the service, plans are expensive. It is not the phone itself that matters, but the connectivity to a vast network of other phones, other people and the internet. Until you download software that lets you find a local restaurant or mange your finances. Let say you make freezers the big, expensive kind that grocery stores buy. You sell ne and you are done with that customer. When it brakes the customer calls a service person, who probably comes from somewhere other than your company. But let us say that freezer knows that it is about to go on the fritz. Let say three refrigerator alerts the customer before it breaks. Better yet, let us say the freezer alerts the manufacturer and you are able to send a service person to do preventative work and save a lot of haagen- dazs from melting. Embedded technology allows all of that to happen. You, the freezer company have transformed yourself from a product company to product and services company. The possibilities go beyond that programming device to communicate with businesses can eliminate the need for costly call centers. Copy machines that can order their own replacement cartridges will save businesses time and money. Remember, the fact the technology is embedded is not what important, and neither is the device.

APPLICATIONS Telecom Mobile phone systems (handsets and base stations), modems, routers Automotive application Braking system, Traction control, Airbag release system, Management units, and Steer-by-wire systems. Domestic application Dishwasher, television, washing machines, microwave ovens, Video recorders, Security system, Garage door controllers, Calculators, Digital watches, VCRs, Digital cameras, Remote Controls, Treadmills Robotic Fire fighting robot, Automatic floor cleaner, robotic arm Aerospace application Flight control system, Engine controllers, Autopilots, Passenger entertainment system Medical equipment Anesthesia monitoring system, ECG monitors, Pacemakers, Drug delivery systems, MRI scanners Defense system Radar systems, Fighter aircraft flight control system, Radio system, Missile guidance systems Office automation Laser printer.

COMPONENT DESCRIPTION
A) MICRO CONTROLLER

The IC 8051 is a low-power; high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmels high-density nonvolatile memory technology and is 5

compatible with the industry-standard MCS-51 instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel IC 8051 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.

The IC 8051 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, full duplex serial port, on-chip oscillator and clock circuitry. In addition, the IC 8051 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning.

FEATURES OF MICROCONTROLLER Compatible with MCS51 Products 4K Bytes of Reprogrammable Flash Memory 2.7V to 6V Operating Range Fully Static Operation: 0 Hz to 24 MHz Two-level Program Memory Lock 128 x 8-bit Internal RAM 15 Programmable I/O Lines Two 16-bit Timer/Counters Six Interrupt Sources Programmable Serial UART Channel Direct LED Drive Outputs Low-power Idle and Power-down Modes

PIN CONFIGURATION:

PIN DESCRIPTION:
1) VCC Supply voltage. 2) GND Ground.

3) Port 0 Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming, And outputs the code bytes during program verification. External pull-ups are required during program verification.

4) Port 1 Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source Current (IIL) because of the internal pull-ups. Port 1 also receives the low-order address bytes during Flash programming and verification.

5) Port 2 Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull-ups and can be used as inputs.

As inputs, Port 2 pins that are externally being pulled low will source Current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during access to external data memory that uses 16-bit addresses (MOVX @ DPTR).

In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that uses 8-bit addresses (MOVX @ RI); Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.

6) Port 3 Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source Current (IIL) because of the pull-ups. Port 3 also serves the functions of various special features of the AT89C51 as listed below:

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Port 3 also receives some control signals for Flash programming and verification. 7) RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.

8) ALE/PROG Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

9) PSEN Program Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.

10) EA/VPP External Access Enable EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the

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12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.

11) XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

12) XTAL2 Output from the inverting oscillator amplification.

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B) LED: All early devices emitted low-intensity red light, but modern LEDs are available across the visible, ultraviolet and infra red wavelengths, with very high brightness. LEDs are based on the semiconductor diode. When the diode is forward biased (switched on), electrons are able to recombine with holes and energy is released in the form of light. This effect is called electroluminescence and the color of the light is determined by the energy gap of the semiconductor. The LED is usually small in area (less than 1 mm2) with integrated optical components to shape its radiation pattern and assist in reflection.

LEDs present many advantages over traditional light sources including lower energy consumption, longer lifetime, improved robustness, smaller size and faster switching. However, they are relatively expensive and require more precise current and heat management than traditional light sources.

Applications of LEDs are diverse. They are used as low-energy and also for replacements for traditional light sources in well-established applications such as indicators and automotive lighting. The compact size of LEDs has allowed new text and video displays and sensors to be developed, while their high switching rates are useful in communications technology. 13

INTERFACING WITH LED:

In assembly language programmingSetb p1.0 = led off Clr p1.0 = led on

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ADVANTAGE OF LED
1) Traffic light

2) LED destination displays on buses, one with a colored route number.

TYPES OF LED

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C) STEPPER MOTOR

12-Volt 75 Ohm Unipolar Stepper Motor

GENERAL INFORMATION A stepper motor system is an electro-mechanical rotary actuator that converts electrical pulses into unique shaft rotations. This rotation is directly related to the number of pulses. Motion Control, in electronic terms, means to accurately control the movement of an object based on speed, distance, load, inertia or a combination of all these factors. There are numerous types of motion control systems, including; Stepper Motor, Linear Step Motor, DC Brush, Brushless, Servo, Brushless Servo and more. Stepper motors are ideally suited for precision control. This motor can be operated in forward/reverse with controllable speed from a BASIC Stamp or any other microcontroller through a transistor driver circuit.

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WORKING OF STEPPER MOTOR:

FUNDAMENTALS OF OPERATION
Stepper motors operate differently from normal DC motors, which rotate when voltage is applied to their terminals. Stepper motors, on the other hand, effectively have multiple "toothed" electromagnets arranged around a central gear-shaped piece of iron. The electromagnets are energized by an external control circuit, such as a microcontroller. To make the motor shaft turn, first one electromagnet is given power, which makes the gear's teeth magnetically attracted to the electromagnet's teeth. When the gear's teeth are thus aligned to the first electromagnet, they are slightly offset from the next electromagnet. So when the next electromagnet is turned on and the first is turned off, the gear rotates slightly to align with the next one, and from there the process is repeated. Each of those

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slight rotations is called a "step," with an integral number of steps making a full rotation. In that way, the motor can be turned by a precise angle.

STEPPER MOTOR CHARACTERSTICS

Stepper motors are constant power devices. As motor speed increases, torque decreases. The torque curve may be extended by using current limiting drivers and increasing the driving voltage. Steppers exhibit more vibration than other motor types, as the discrete step tends to snap the rotor from one position to another. This vibration can become very bad at some speeds and can cause the motor to lose torque. The effect can be mitigated by accelerating quickly through the problem speed range, physically damping the system, or using a micro-stepping driver. Motors with a greater number of phases also exhibit smoother operation than those with fewer phases.

OPEN LOOP VERSUS CLOSED LOOP COMMUTATION

Steppers are generally commutated open loop, i.e. the driver has no feedback on where the rotor actually is. Stepper motor systems must thus generally be over engineered, especially if the load inertia is high, or there is widely varying load, so that there is no possibility that the motor will lose steps. This has often caused the system designer to consider the trade-offs between a closely sized but expensive servomechanism system and an oversized but relatively cheap stepper. A new development in stepper control is to incorporate a rotor position feedback (e.g. an encoder or resolver), so that the commutation can be made optimal for torque generation according to actual rotor position. This turns the stepper motor into a high pole count brushless servo motor, with exceptional low speed torque and position resolution. An advance on this technique is to normally run the motor in open loop mode, and only enter closed loop mode if the rotor position error becomes too large -- this will allow the system to avoid hunting or oscillating, a common servo problem.

TYPES
There are three main types of stepper motorsy y y

Permanent Magnet Stepper Hybrid Synchronous Stepper Variable Reluctance Stepper

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TWO-PHASE STEPPER MOTOR

There are two basic winding arrangements for the electromagnetic coils in a two phase stepper motor 1)-UNIPOLAR 2)-BIPOLAR

UNIPOLAR MOTORS
A unipolar stepper motor has logically two windings per phase, one for each direction of magnetic field. Since in this arrangement a magnetic pole can be reversed without switching the direction of current, the commutation circuit can be made very simple (eg. a single transistor) for each winding. Typically, given a phase, one end of each winding is made common: giving three leads per phase and six leads for a typical two phase motor. Often, these two phase commons are internally joined, so the motor has only five leads. A microcontroller or stepper motor controller can be used to activate the drive transistors in the right order, and this ease of operation makes unipolar motors popular with hobbyists; they are probably the cheapest way to get precise angular movements. (For the experimenter, one way to distinguish common wire from a coil-end wire is by measuring the resistance. Resistance between common wire and coil-end wire is always half of what it is between coil-end and coil-end wires. This is due to the fact that there is actually twice the length of coil between the ends and only half from center (common wire) to the end.).A quick Unipolar stepper motor coils way to determine if the stepper motor is working is to short circuit every two pairs and try turning the shaft, whenever a higher than normal resistance is felt, it indicates that the circuit to the particular winding is 19

closed and that the phase is working. Unipolar stepper motors with six or eight wires may be driven using bipolar drivers by leaving the phase commons disconnected, and driving the two windings of each phase together[diagram needed]. It is also possible to use a bipolar driver to drive only one winding of each phase, leaving half of the windings unused [diagram needed].

BIPOLAR MOTOR
Bipolar motors have logically a single winding per phase. The current in a winding needs to be reversed in order to reverse a magnetic pole, so the driving circuit must be more complicated, typically with an H-bridge arrangement. There are two leads per phase, none are common. Static friction effects using an H-bridge have been observed with certain drive topologies.. Because windings are better utilised, they are more powerful than a unipolar motor of the same weight.

8-LEAD STEPPER
An 8 lead stepper is wound like a unipolar stepper, but the leads are not joined to common internally to the motor. This kind of motor can be wired in several configurations:
y y y y

Unipolar. Bipolar with series windings. This gives higher inductance but lower current per winding. Bipolar with parallel windings. This requires higher current but can perform better as the winding inductance is reduced. Bipolar with a single winding per phase. This method will run the motor on only half the available windings, which will reduce the available low speed torque but require less current.

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HIGHERPHASE COUNT STEPPER MOTORS

Multi-phase stepper motors with many phases tend to have much lower levels of vibration, although the cost of manufacture is higher too.

Stepper motor drive circuits

Stepper motor performance is strongly dependent on the drive circuit. Torque curves may be extended to greater speeds if the stator poles can be reversed more quickly, the limiting factor being the winding inductance. To overcome the inductance and switch the windings quickly, one must increase the drive voltage. This leads further to the necessity of limiting the current that these high voltages may otherwise induce.

L/R drive circuits

L/R drive circuits are also referred to as constant voltage drives because a constant positive or negative voltage is applied to each winding to set the step positions. However, it is winding current, not voltage that applies torque to the stepper motor shaft. The current I in each winding is related to the applied voltage V by the winding inductance L and the winding resistance R. The resistance R determines the maximum current according to Ohm's law I=V/R. The inductance L determines the maximum rate of change of the current in the winding according to the formula for an Inductor dI/dt = V/L. Thus when controlled by an L/R drive, the maximum speed of a stepper motor is limited by its inductance since at some speed, the voltage V will be changing faster than the current I can keep up. With an L/R drive it is possible to control a low voltage resistive motor with a higher voltage drive simply by adding an external resistor in series with each winding. This will waste power in the resistors, and generate heat. It is therefore considered a low performing option, albeit simple and cheap.

Chopper drive circuits

Chopper drive circuits are also referred to as constant current drives because they generate a somewhat constant current in each winding rather than applying a constant voltage. On each new step, a very high voltage is applied to the winding initially. This causes the current in the winding to rise quickly since dI/dt = V/L where V is very large. The current in each winding is monitored by the controller, usually by measuring the voltage across a small sense resistor in series with each winding. When the current exceeds a specified current limit, the voltage is turned off or "chopped", typically using power transistors. When the winding current drops below the specified limit, the voltage is turned on again. In this way, the current is held relatively constant for a particular step position. This requires additional electronics to sense winding currents, and control the 21

switching, but it allows stepper motors to be driven with higher torque at higher speeds than L/R drives. Integrated electronics for this purpose are widely available.

Phase current waveforms

A stepper motor is a polyphase AC synchronous motor (see Theory below), and it is ideally driven by sinusoidal current. A full step waveform is a gross approximation of a sinusoid, and is the reason why the motor exhibits so much vibration. Various drive techniques have been developed to better approximate a sinusoidal drive waveform: these are half stepping and micro stepping.

Full step drive (two phases on)

This is the usual method for full step driving the motor. Both phases are always on. The motor will have full rated torque.

Wave drive
In this drive method only a single phase is activated at a time. It has the same number of steps as the full step drive, but the motor will have significantly less than rated torque. It is rarely used.

Half stepping
When half stepping, the drive alternates between two phases on and a single phase on. This increases the angular resolution, but the motor also has less torque at the half step position (where only a single phase is on). This may be mitigated by increasing the current in the active winding to compensate. The advantage of half stepping is that the drive electronics need not change to support it.

Micro stepping
What is commonly referred to as micro stepping is actual "sine cosine micro stepping" in which the winding current approximates a sinusoidal AC waveform. Sine cosine micro stepping is the most common form, but other waveforms are used. Regardless of the waveform used, as the micro steps become smaller, motor operation becomes more smooth. However, the purpose of micro stepping is not usually to achieve smoothness of motion, but to achieve higher position resolution. A micro step driver may split a full step into as many as 256 micro steps. A typical motor may have 200 steps per revolution. Using such a motor with a 256 micro step controller (also referred to as a "divide by 256" controller) results in an angular resolution of 360/(200x256) = 0.00703125 or 51200 discrete positions per revolution. However, it should be noted that such fine resolution is rarely achievable in practice, regardless of the controller, due to mechanical stiction and other sources of error between the specified and actual positions.

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Step size repeatability is an important step motor feature and a fundamental reason for their use in positioning. Micro stepping can affect the step size repeatability of the motor. Example: many modern hybrid step motors are rated such that the travel of every Full step (example 1.8 Degrees per Full step or 200 Full steps per revolution) will be within 3% or 5% of the travel of every other Full step; as long as the motor is operated with in its specified operating ranges. Several manufacturers show that their motors can easily maintain the 3% or 5% equality of step travel size as step size is reduced from Full stepping down to 1/10th stepping. Then, as the micro stepping divisor number grows, step size repeatability degrades. At large step size reductions it is possible to issue many micro step commands before any motion occurs at all and then the motion can be a "jump" to a new position.

Stepper motor ratings and specifications

Stepper motors nameplates typically give only the winding current and occasionally the voltage and winding resistance. The rated voltage will produce the rated winding current at DC: but this is mostly a meaningless rating, as all modern drivers are current limiting and the drive voltages greatly exceed the motor rated voltage. A stepper's low speed torque will vary directly with current. How quickly the torque falls off at faster speeds depends on the winding inductance and the drive circuitry it is attached to, especially the driving voltage. Steppers should be sized according to published torque curve, which is specified by the manufacturer at particular drive voltages and/or using their own drive circuitry. It is not guaranteed that you will achieve the same performance given different drive circuitry, so the pair should be chosen with great care.

Applications
Computer-controlled stepper motors are one of the most versatile forms of positioning systems. They are typically digitally controlled as part of an open loop system, and are simpler and more rugged than closed loopservosystems. Industrial applications are in high speed pick and place equipment and multi-axis machine CNC machines often directly driving lead screws or ball screws. In the field of lasers and optics they are frequently used in precision positioning equipment such as linear actuators, linear stages, rotation stages, goniometers, and mirror mounts. Other uses are in packaging machinery, and positioning of valve pilot stages for fluid control systems. Commercially, stepper motors are used in floppy disk drives, flatbed scanners, computer printers, plotters and many more devices.

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INTERFACING OF STEPPER MOTOR

In assembly language programming-

Mov a,#88h lebel: mov p2,a rr a acall lebel delay:loop end

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ULN 2003 CHIP

FEATURES
Output current 500mA per driver (600mA peak) - Output voltage 50V - Integrated suppression diodes for inductive loads - Outputs can be paralleled for higher current TTL/CMOS/PMOS/DTL Compatible inputs - Inputs pinned opposite outputs to simplify Layout DESCRIPTION The ULN2001, ULN2002, ULN2003 and ULN2004 are high voltage, high current Darlington Arrays each contain seven open collector Darlington pairs with common emitters.

WHY WE USE ULN 2003?

Digital system and microcontroller pins lack sufficient current to drive the relay. While the stepper motors coil needs around 10ma to be energized, the microcontrollers pin can provide a maximum of 1-2 mA current. For this reason, we place a driver.

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D) VOLAGE REGULATOR
Voltage regulator ICs are available with fixed (typically 5, 12 and 15V) or variable output voltages. The maximum current they can pass also rates them. Most regulators include some automatic protection from excessive current (over load protection) and overheating (thermal protection). Many of fixed voltage regulator ICs has 3 leads. They include a hole for attaching a heat sink if necessary. 7805 Voltage Regulator

DESCRIPTION:
These voltage regulators are monolithic circuit integrated circuit designed as fixed voltage regulators for a wide variety of applications including local, on card regulation. These regulators employ internal current limiting, thermal shutdown, and safe-area compensation. With adequate heat sinking they can deliver output current in excess of 1.0 A. Although designed primarily as a fixed voltage regulator, these devices can be used with external components to obtain adjustable voltage and current. FEATURES Output current in Excess of 1.0 A No external component required Internal thermal overload protection Internal short circuit current limiting Output transistor safe-area compensation Output voltage offered in 2% and 4% tolerance

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E) LCD DISPLAY
DESCRIPTION OF LCD DISPLAY: This is the first interfacing example for the Parallel Port. We will start with something simple. This example doesn't use the Bi-directional feature found on newer ports, thus it should work with most, if not all Parallel Ports. It however doesn't show the use of the Status Port as an input. These LCD Modules are very common these days, and are quite simple to work with, as all the logic required running them is on board.

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CIRCUIT DESCRIPTION:
Above is the quite simple schematic. The LCD panel's Enable and Register Select is connected to the Control Port. The Control Port is an open collector / open drain output. While most Parallel Ports have internal pull-up resistors, there is a few which don't. Therefore by incorporating the two 10K external pull up resistors, the circuit is more portable for a wider range of computers, some of which may have no internal pull up resistors. We make no effort to place the Data bus into reverse direction. Therefore we hard wire the R/W line of the LCD panel, into write mode. This will cause no bus conflicts on the data lines. As a result we cannot read back the LCD's internal Busy Flag which tells us if the LCD has accepted and finished processing the last instruction. This problem is overcome by inserting known delays into our program. The 10k Potentiometer controls the contrast of the LCD panel. Nothing fancy here. As with all the examples, I've left the power supply out. You can use a bench power supply set to 5v or use an onboard +5 regulator. Remember a few de-coupling capacitors, especially if you have trouble with the circuit working properly.

INTELLIGENT LCD DISPLAY:

LCD displays are widely used in many application like mobile phones, robotics, DVD players measurement instrument etc. Intelligent LCD display are very capable because they can display complete ASCII character set and even graphics. These displays are easily connected with microcontroller and microprocessor. LCD displays are complete embedded system in them, because it include micro controller, RAM and ROM. The intelligent displays are of two types a) text display b) graphics display Text display can display all character set and graphics display can show any graphics because they are interfaced pixel wise. In recent yr the LCD is finding wide spread use replacing LEDs (seven segment LEDS and other multi segment LEDs). 28

This is due to following reasons: a) The declining prices of LCD. b) The ability to display the numbers, characters and graphics. Ths is not possible in LEDS, which can display and few characters. c) Incorporation of a refreshing controller into the LCDS, thereby relieving the cpu of the task of refreshing the LCD. In contrast, the LED must be refreshed by The cpu (or in some other way) to keep displaying the data. The interfacing of LCD is quite difficult but we will try to make it simple and let us explain it for u. We will learn how to interface the text intelligent LCD display. These displays are available in the market of 16 column and one row and more than one row displays.

Here is the block diagram of a LCD display:

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MICROCONTROLLER: It is the brain of LCD display. This is handling the all working of the LCD display.

DATA RAM: This ram is storing the ASCII value of corresponding characters which will be displays on the LCD. For each column there is one location in the RAM. When we will the store the ASCII value at that location den the its corresponding character will be display on the screen.

CODE RAM : This ram store the binary pattern according to the character.

ROM: This ROM stores the binary pattern which is according to the pixels of LCD and there are patterns of every character.

DATA REGISTER: The register work as buffer for data lines and the internal busses of LCD. The ASCII value of character will be given to the data register.

BF (BUSY FLAG): It indicates the internal working of the LCD. It show whether LCD is busy in any operation or not. IF BF=0 (LCD id idle we can proceed for next operation). IF BF=1 (LCD is busy we can not proceed for next operation and we have to wait unless operation complete.

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DESCRIPTION OF PINS GIVEN BELOW AS:

VCC, VSS and VEE: While VCC and VSS provides +5v and GND respectively, VEE is used for controlling LCD contrast. RS (Register select): The RS pin is used to select DR or CR. If RS =0 , CR register is selected allowing the user to send a command such as clr display, cursor at home ,etc. If RS =1, DR register is selected, allowing the user to send data to be display on the LCD.

RW( Read /write): When RW=0 write operation. When RW=1 read operation.

EN: The EN pin is used by the LCD to latch binary bits available on its data pins. When data is supplied to data pins, in negative edge is applied to this pin so that the LCD latches in the data present at the data pins. This pulse must be a minimum of 450ns wide. There should be positive edge at EN pin when read operation is required.

D7-D0: This is 8 bit data pins D7-D0 is used to send information to the LCD pr read the contents of the LCD internal register. BK-LED: These pin are used to give the supply to the back light of the LCD display, so the content of the LCD display can bi view in the dark.

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PIN diagram is shown below: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

GND VCC VEE RS RW EN D0 D1 D2 D3 D4 D5 D6 D7 LED+ LED-

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Command code (hex) 01h 02h 04h 06h 05h 07h 08h 0Ah 0Ch 0Eh 0Fh 10h 14h 18h 1Ch 80h C0h 38h

Description Clear display screen Return home Decrement cursor (shift cursor to left) Increment cursor (shift cursor to right) Shift display right Shift display left Display off, cursor off Display off, cursor on Display on, cursor off Display on, cursor blinking Display on, cursor not blinking Shift cursor position to left Shift cursor position to right Shift the entire display to the left Shift the entire display to the right Force cursor to beginning of 1st line Force cursor to beginning of 2nd line 2 lines and 5*7 matrix

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INTERFACING OF LCD DISPLAY:

The LCD can be easily interfaced wit h the micro controller for that we connect port line with pins of LCD. In this example RS of LCD is connected with p3.5, RW of LCD is connected with p3.3, EN of LCD is connected with p3.4. Data lines of LCD are connected with p1 of MC(microcontroller).

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F) POWER SUPPLY

BRIDGE RECTIFIER: Bridge rectifier circuit consists of four diodes arranged in the form of a bridge as shown in figure.

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OPERATION: During the positive half cycle of the input supply, the upper end A of the transformer secondary becomes positive with respect to its lower point B. This makes Point1 of bridge Positive with respect to point 2. The diode D1 & D2 become forward biased & D3 & D4 become reverse biased. As a result a current starts flowing from point1, through D1 the load & D2 to the negative end. During negative half cycle, the point2 becomes positive with respect to point1. Diodes D1 & D2 now become reverse biased. Thus a current flow from point 2 to point1.

G) TRANSFORMER
Transformer is a major class of coils having two or more windings usually wrapped around a common core made from laminated iron sheets. It has two cols named primary and secondary. If the current flowing through primary is fluctuating, then a current will be inducted into the secondary winding. A steady current will not be transferred from one coil to other coil.

Basic Transformers are of two types: 1. Step up transformer 2. Step down transformer In the power supply we use step down transformer. We apply 220V AC on the primary of step down transformer. This transformer step down this voltage to 6V AC. We Give 6V AC to rectifier circuit, which convert it to 5V DC.

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H) DIODE
The diode is a p-n junction device. Diode is the component used to control the flow of the current in any one direction. The diode widely works in forward bias.

Diode when the current flows from the P to N direction. Then it is in forward bias. The Zener diode is used in reverse bias function i.e. N to P direction. Visually the identification of the diode`s terminal can be done by identifying he silver/black line. The silver/black line is the negative terminal (cathode) and the other terminal is the positive terminal (cathode). APPLICATION Diodes: Rectification, free-wheeling, etc Zener diode: Voltage control, regulator etc. Tunnel diode: Control the current flow, snobbier circuit, etc

I) RESISTORS
The flow of charge through any material encounters an opposing force similar in many respects to mechanical friction .this opposing force is called resistance of the material .in some electric circuit resistance is deliberately introduced in form of resistor. Resistor used fall in three categories , only two of which are color coded which are metal film and carbon film resistor .the third category is the wire wound type ,where value are generally printed on the vitreous paint finish of the component. Resistors are in ohms and are represented in Greek letter omega, looks as an upturned horseshoe. Most electronic circuit requires resistors to make them work properly and it is obliviously important to find out something about the different types of resistors available. Resistance is measured in ohms; the symbol for ohm is an omega ohm. 1 ohm is quite small for electronics so resistances are often given in kohm and Mohm. Resistors used in electronics can have resistances as low as 0.1 ohm or as high as 10 Mohm.

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Figure

No.

1.14:

Symbol

of

Resistance

FUNCTION:Resistor restricts the flow of electric current, for example a resistor is placed in series with a light-emitting diode (LED) to limit the current passing through the LED. TYPES OF RESISTORS:FIXED VALUE RESISTORS metal film .These two types are it includes two types of resistors as carbon film and explained under

1. CARBON FILM RESISTORS During manufacture, at in film of carbon is deposited onto a small ceramic rod. The resistive coating is spiraled away in an automatic machine until the resistance between there two ends of the rods is as close as possible to the correct value. Metal leads and end caps are added, the resistors is covered with an insulating coating and finally painted with colored bands to indicate the resistor value

2. METAL FILM RESISTORS Metal film and metal oxides resistors are made in a similar way,
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but can be made more accurately to within 2% or 1% of their nominal vale there are some difference in performance between these resistor types, but none which affects their use in simple circuit. 3.WIRE WOUND RESISTOR A wire wound resistor is made of metal resistance wire, and because of this, they can be manufactured to precise values. Also, high wattage resistors can be made by using a thick wire material. Wire wound resistors cannot be used for high frequency circuits. Coils are used in high frequency circuit. Wire wound resistors in a ceramic case, strengthened with special cement. They have very high power rating, from 1 or 2 watts to dozens of watts. These resistors can become extremely hot when used for high power application, and this must be taken into account when designing the circuit. TESTING Resistors are checked with an ohm meter/millimeter. For a defective resistor the ohm-meter shows infinite high reading.

J) CAPACITORS How Batteries Work In a way, a capacitor is a little like a battery. Although they work in completely different ways, capacitors and batteries both store electrical energy. If you have read , then you know that a battery has two terminals. Inside the battery, chemical reactions produce electrons on one terminal and absorb electrons at the other terminal.

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BASIC Like a battery, a capacitor has two terminals. Inside the capacitor, the terminals connect to two metal plates separated by a dielectric. The dielectric can be air, paper, plastic or anything else that does not conduct electricity and keeps the plates from touching each other. You can easily make a capacitor from two pieces of aluminum foil and a piece of paper. It won't be a particularly good capacitor in terms of its storage capacity, but it will work. In an electronic circuit, a capacitor is shown like this:

: Symbol of Capacitor When you connect a capacitor to a battery, heres what happens: The plate on the capacitor that attaches to the negative terminal of the battery accepts electrons that the batter is producing.

The plate on the capacitor that attaches to the positive terminal of the battery loses electrons to the battery.

40

Figure : Capacitor & Battery Connection TESTING To test the capacitors, either analog meters or special digital meters with the specified function are used. The non-electrolyte capacitor can be tested by using the digital meter.

K)BUZZER
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Buzzer is a device used for beep signal. This will help us to make understand information or message. A buzzer is usually electronic device used in automobiles,household applications

Figure : Buzzer It mostly consists of switches or sensors connected to a control unit that determines if and which button was pushed or a preset time has lapsed, and usually illuminates a light on appropriate button or control panel, and sounds a warning in the form of a continuous or intermittent buzzing or beeping sound. Initially this device was based on an electromechanical system which was identical to an electrical bell without the metal gong. Often these units were anchored to a wall or ceiling and used the ceiling or wall as a sounding board. Another implementation with some AC-connected devices was to implement a circuit to make the AC current into a noise loud enough to derive a loudspeaker and hook this circuit to a cheap 8ohm speaker. These buzzers do not make a sound or turn on a light, they stop a nearby digital clock, briefly fire two smoke cannons on each side of the stage exit and open the exit. However,
42

at the end of the Heartbreaker in Viking, the buzzer is replaced with a sword that, when removed, causes two contacts to touch, closing the circuit and causing the latter two actions above to occur. A buzzer or beeper is a signalling device, usually electronic, typically used in automobiles, household appliances such as a microwave oven, or game shows. It most commonly consists of a number of switches or sensors connected to a control unit that determines if and which button was pushed or a preset time has lapsed, and usually illuminates a light on the appropriate button or control panel, and sounds a warning in the form of a continuous or intermittent buzzing or beeping sound. Initially this device was based on an electromechanical system which was identical to an electric bell without the metal gong (which makes the ringing noise).

Often these units were anchored to a wall or ceiling and used the ceiling or wall as a sounding board. Another implementation with some AC-connected devices was to implement a circuit to make the AC current into a noise loud enough to drive a loudspeaker and hook this circuit up to a cheap 8-ohm speaker. Nowadays, it is more popular to use a ceramic-based piezoelectric sounder which makes a high-pitched tone. Usually these were hooked up to "driver" circuits which varied the pitch of the sound or pulsed the sound on and off. In game shows it is also known as a "lockout system," because when one person signals ("buzzes in"), all others are locked out from signalling.Several game shows have large buzzer buttons which are identified as "plungers". The buzzer is also used to signal wrong answers and when time expires on many game
43

shows, such as Wheel of Fortune, Family Feud and The Price is Right. The word "buzzer" comes from the rasping noise that buzzers made when they were electromechanical devices, operated from stepped-down AC line voltage at 50 or 60 cycles. Other sounds commonly used to indicate that a button has been pressed are a ring or a beep. WORKING OF PROJECT It is a microcontroller based device. It is used in driverless metro train, which is used in most of developed countries. These trains are equipped with CPU, which control the chain. The train is programmed for the specific path. Every station on the path is defined; stoppage timing of the train and distance between the two stations is predefined. Basically it has four parts 1. POWER SUPPLY 2. 8051 IC 3. DISPLAY UNIT 4. STEPPER MOTOR The 230 AC supply is converted into 9 volts by the power supply sectioninwhich4 Elements are used. 1. TRANSFORMER 2. 7805 REGULATOR 3. DIODES 4007 (in bridge shape) 4. CAPACITOR OF 100 MICRO FARADS & 470 MICRO FARAD . The 230 volts is attenuated by 9 volts by transformer. Then it is rectified by the bridge rectifier made up of diodes. Then the 9 v is regulated by 7805. 1000 micro farad capacitor is used to filter the DC voltage. The LED attaches to check the correctness of
44

power supply. In this project we try to give the same prototype for this type of trains. We are using microcontroller 8051 as CPU. The motion of the train is controlled by the Stepper Motor, for displaying message in the train we are using Intelligent LCD Display of two lines. The train is designed for three stations, named as Aligarh, Ghaziabad and New Delhi. The stoppage time is of 3 Sec and time between two consecutive stations is 6 Sec. There is a LCD display for showing various messages in the train for passengers. There are indicators, which are used to show the train direction i.e. UP path and Down path. Before stopping at station the train blows the buzzer. BLOCK DIAGRAM :

CIRCUIT DIAGRAM:

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46

COST ANALYSIS OF COMPONENTS USED Sr. Equipment Rating Quantity Cost no 1 IC 8051 MC --1 80 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 IC ULN 2003 Transformer Voltage Regulator 2 line LCD display Stepper Motor Crystal Oscillator Switch LED Resistors Capacitors(ceramic disk) Diode Buzzer PCB Variable Resistance 40 Pin IC Base Total --9-0-9 7805 ----12Mhz ----220,4.7k,10k 33pf,470f,100f ------10k --1 1 1 1 1 1 2 2 9 4 4 1 1 1 1 40 45 5 120 80 10 10 4 18 8 12 20 60 8 4 545

PROGRAM

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The sequence of instructions is what constitutes a program. The sequence of instructions may be altered to suit the application. ASSEMBLY LANGUAGE Writing and understanding such programs in binary or hexadecimal form is very difficult ,so each instructions is given a symbolic notation in English language called as mnemonics. A program written in mnemonics Form is called an assembly language program. But it must be converted into machine language for execution by processor. ASSEMBLER An assembly language program should be converted to machine language for execution by processor. Special software called ASSEMBLER converts a program written in mnemonics to its equivalent machine opcodes. HIGH LEVEL LANGUAGE A high level language like C may be used to write programs for processors. Software called compiler converts this high level language program down to machine code. Ease of programming and portability. PIN DESCRIPTION VCC (Pin 40) Provides voltage to the chip . +5V GND (Pin 20) Ground XTAL1 (Pin 19) and XTAL2 (Pin 18) Crystal Oscillator connected to pins 18, 19.Two capacitors of 30pF value. Time for one machine

cycle:11.0592/12=1.085 secs ASSEMBLY PROGRAM:

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$mod51 lcd equ p1 rs equ p3.5 rw equ p3.4 en equ p3.3 org 0000h acall delay setb p3.1 clr a mov dptr,#data1 again: movc a,@a+dptr mov lcd,a acall command jz lable clr a inc dptr ajmp again lable: clr a mov dptr,#data2 again1: movc a,@a+dptr mov lcd,a acall display jz lable1 clr a inc dptr ajmp again1

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lable1: clr a mov dptr,#data1 again2: movc a,@a+dptr mov lcd,a acall command jz lable11 clr a inc dptr ajmp again2 lable11: clr a mov dptr,#data3 again12: movc a,@a+dptr mov lcd,a acall display jz lable3 clr a inc dptr ajmp again12

lable3: clr a mov dptr,#data1 again4: movc a,@a+dptr mov lcd,a acall command jz lable33 clr a inc dptr
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ajmp again4 lable33: clr a mov dptr,#data4 again14: movc a,@a+dptr mov lcd,a acall display jz lable40 clr a inc dptr ajmp again14 lable40: clr p3.1 mov a,#88h mov r3,#20 again0: mov p2,a rr a acall delay djnz r3,again0 setb p3.1 acall delay acall delay

clr a mov dptr,#data1 again5: movc a,@a+dptr mov lcd,a acall command jz lable44 clr a inc dptr
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ajmp again5 lable44: clr a mov dptr,#data5 again15: movc a,@a+dptr mov lcd,a acall display jz lable50 clr a inc dptr ajmp again15 lable50: clr p3.1 mov a,#88h mov r3,#20 again01: mov p2,a rr a acall delay djnz r3,again01 setb p3.1 acall delay acall delay acall delay

clr a mov dptr,#data1 again7: movc a,@a+dptr mov lcd,a acall command jz lable77 clr a inc dptr
52

ajmp again7 lable77: clr a mov dptr,#data7 again17: movc a,@a+dptr mov lcd,a acall display jz lable8 clr a inc dptr ajmp again17 lable8: clr a mov dptr,#data1 again8: movc a,@a+dptr mov lcd,a acall command jz lable88 clr a inc dptr ajmp again8 lable88: clr a mov dptr,#data4 again18: movc a,@a+dptr mov lcd,a acall display jz lable80 clr a inc dptr ajmp again18
53

lable80: clr p3.1 mov a,#88h mov r3,#20 again81: mov p2,a rl a acall delay djnz r3,again81 setb p3.1 acall delay acall delay acall delay

clr a mov dptr,#data1 again9: movc a,@a+dptr mov lcd,a acall command jz lable99 clr a inc dptr ajmp again9 lable99: clr a mov dptr,#data8 again19: movc a,@a+dptr mov lcd,a acall display jz lable90 clr a inc dptr ajmp again19
54

lable90: clr p3.1 mov a,#88h mov r3,#20 again91: mov p2,a rl a acall delay djnz r3,again91 setb p3.1 acall delay acall delay acall delay

clr a mov dptr,#data1 again6: movc a,@a+dptr mov lcd,a acall command jz lable55 clr a inc dptr ajmp again6 lable55: clr a mov dptr,#data6 again16: movc a,@a+dptr mov lcd,a acall display jz lable6 clr a inc dptr ajmp again16
55

lable6: sjmp lable6

command: clr rs clr rw clr en acall delay1 setb en ret display: setb rs clr rw clr en acall delay1 setb en ret

delay1: mov r0,#0ffh loop1:mov r1,#05h loop2: DJNZ r1,loop2 loop3: djnz 05h,loop1 DJNZ r0,loop1 ret delay: push acc push 00h push 01h
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push p0 push p1 mov r0,#0eh loopr: mov a,#0ffh loopb: mov b,#0ffh loopa: djnz b,loopa djnz 0e0h,loopb djnz r0,loopr pop p1 pop p0 pop 01h pop 00h pop acc ret

org 200h data1: db 38h,0eh,01h,06h,80h,0 data2: db 'WELCOME TO ALL IN METRO TRAIN',0 data3: db ' THIS STATION IS ROORKEE',0 data4: db 'THE NEXT STATION IS HARIDWAR',0 data5: db 'THE NEXT STATION IS RISHIKESH',0 data6: db ' THANKS FOR USING METRO TRAIN',0 data7: db ' ITS RISHIKESH NOW RETURN JOURNEY STARTS',0 data8: db ' NEXT STATION IS ROORKEE',0 end

P.C.B. DESIGNING & WORKING 1) P.C.B. DESIGNING P.C.B. LAYOUT The entire circuit can
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be easily assembled on a general purpose P.C.B. board respectively. Layout of desired diagram and preparation is first and most important operation in any printed circuit board manufacturing process. First of all layout of component side is to be made in accordance with available components dimensions. The following points are to be observed while forming the layout of P.C.B. 1. Between two components, sufficient space should be maintained. 2. High voltage/max dissipated components should be mounted at sufficient distance from semiconductor and electrolytic capacitors. 3. The most important points are that the components layout is making proper compromise with copper side circuit layout. Printed circuit board (P.C.B.s) is used to avoid most of all the disadvantages of conventional breadboard. These also avoid the use of thin wires for connecting the components; they are small in size and efficient in performance. PREPARING CIRCUIT LAYOUT First of all the actual size circuit layout is to be drawn on the copper side of the copper clad board. Then enamel paint is applied on the tracks of connection with the help of a shade brush. We have to apply the paints surrounding the point at which the connection is to be made. It avoids the disconnection between the leg of the component and circuit track. After completion of painting work, it is allowed to dry. DRILLING After completion of painting work, holes 1/23inch(1mm) diameter are drilled at desired points where we have to fix the components.

ETCHING The removal of excess of copper on the plate apart from the printed circuit is known as etching. From this process the copper clad board wit printed circuit is placed in the solution of FeCl with
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3-4 drops of HCL in it and is kept so for about 10 to 15 minutes and is taken out when all the excess copper is removed from the P.C.B. After etching, the P.C.B. is kept in clean water for about half an hour in order to get P.C.B. away from acidic, field, which may cause poor performance of the circuit. After the P.C.B. has been thoroughly washed, paint is removed by soft piece of cloth dipped I thinner or turbine. Then P.C.B. is checked as per the layout, now the P.C.B. is ready for use. SOLDERING Soldering is the process of joining two metallic conductor the joint where two metal conductors are to be join or fused is heated with a device called soldering iron and then as allow of tin and lead called solder is applied which melts and converse the joint. The solder cools and solidifies quickly to ensure is good and durable connection between the jointed metal converting the joint solder also present oxidation. SOLDERING AND DESOLDERING TECHIQUES: These are basically two soldering techniques. Manual soldering with iron. Mass soldering. SOLDERING WITH IRON The surface to be soldered must be cleaned & fluxed. The soldering iron switched on and bellowed to attain soldering temperature. The solder in form of wire is allied hear the component to be soldered and heated with iron. The surface to be soldered is filled, iron is removed and joint is cold without disturbing. SOLDER JOINT ARE SUPPOSED TO 1. Provide permanent low resistance path. 2. Make a robust mechanical link between P.C.B. and leads of components. 3. Allow heat flow between component, joining elements and P.C.B. 4. Retain adequate strength with temperature variation. The following precaution should be taken while soldering: 1. Use always an iron plated copper core tip for soldering
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iron. 2. Slightly for the tip with a cut file when it is cold. 3. Use a wet sponge to wipe out dirt from the tip before soldering instead of asking the iron. 4. Tighten the tip screw if necessary before iron is connected to power supply. 5. Clean component lead and copper pad before soldering. 6. Apply solder between component leads, P.C.B. pattern and tip of soldering iron. 7. Iron should be kept in contact with the joint for 2-3 seconds only instead of keeping for very long or very small time. 8. Use optimum quantity of solder.

MEMORY AND REGISTER ORGANISATION: The 8051 has a separate memory space for code (programs) and data. We will refer here to on-chip memory and external memory as shown in figure. In an actual implementation the external memory may, in fact, be contained within the microcomputer chip. However, we will use the definitions of internal and externalbnmemory to be consistent with 8051 instructions which operate on memory. Note, the separation of the code and data memory in the 8051 architecture is a little unusual. The separated memory architecture is referred to as Harvard architecture whereas Von Neumann architecture defines a system where code and data can share common memory.

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8051 Memory representation

External Code Memory The executable program code is stored in this code memory. The code memory size is limited to 64KBytes (in a standard 8051). The code memory is read-only in normal operation and is programmed under special conditions e.g. it is a PROM or a Flash RAM type of memory.

External RAM Data Memory

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This is read-write memory and is available for storage of data. Up to 64KBytes of external RAM data memory is supported (in a standard 8051).

Internal Memory The 8051s on-chip memory consists of 256 memory bytes organised as follows: First 128 bytes: 00h to 1Fh Register Banks 0h to 2Fh Bit Addressable RAM 30 to 7Fh General Purpose RAM Next 128 bytes: 80h to FFh Special Function RegistersThe first 128 bytes of internal memory is organised as shown in figure 1.6, and is referred to as Internal RAM, or IRAM.1 Organization of Internal RAM (IRAM) memory:

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63

Register Banks: 00h to 1Fh The 8051 uses 8 general-purpose registers R0 through R7 (R0, R1, R2, R3, R4, R5, R6, and R7). These registers are used in instructions such as: ADD A, R2 ; adds the value contained in R2 to the accumulator Note since R2 happens to be memory location 02h in the Internal RAM the following instruction has the same effect as the above instruction. Now, things get more complicated when we see that there are four banks of these general-purpose registers defined within the Internal RAM. For the moment we will consider register bank 0 only. Register banks 1 to 3 can be ignored when writing introductory level assembly language programs. Bit Addressable RAM: 20h to 2Fh The 8051 supports a special feature which allows access to bit variables. This is where individual memory bits in Internal RAM can be set or cleared. In all there are 128 bits numbered 00h to 7Fh. Being bit variables any one variable can have a value 0 or 1. A bit variable can be set with a command such as SETB and cleared with a command such as CLR. Example instructions are: SETB 25h ; sets the bit 25h (becomes 1) CLR 25h ; clears bit 25h (becomes 0)
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The Bit Addressable area of the RAM is just 16 bytes of Internal RAM located between 20h and 2Fh. So if a program writes a byte to location 20h, for example, it writes 8 bit variables, bits 00h to 07h at once. Note bit addressing can also be performed on some of the SFR registers.

General Purpose RAM: 30h to 7Fh These 80 bytes of Internal RAM memory are available for generalpurpose data storage. Access to this area of memory is fast compared to access to the main memory and special instructions with single byte operands are used. However, these 80 bytes are used by the system stack and in practice little space is left for general storage. The general purpose RAM can be accessed using direct or indirect addressing modes. Examples of direct addressing: MOV A, 6Ah ; reads contents of address 6Ah to accumulator Examples for indirect addressing (use registers R0 or R1): MOV R1, #6Ah ; move immediate 6Ah to R1 MOV A, @R1 ; move indirect: R1 contains address of Internal RAM which contains data that is moved to A.
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These two instructions have the same effect as the direct instruction above. SFR Registers The SFR registers are located within the Internal Memory in the address range 80h to FFh, as shown in figure 1.7. Not all locations within this range are defined. Each SFR has a very specific function. Each SFR has an address (within the range 80h to FFh) and a name which reflects the purpose of the SFR. Although 128 byes of the SFR address space is defined only 21 SFR registers are defined in the standard 8051. Undefined SFR addresses should not be accessed as this might lead to some unpredictable results. Note some of the SFR registers are bit addressable. SFRs are accessed just like normal Internal RAM locations.

Timer and Counters The 8051 has two internal sixteen bit hardware Timer/Counters. Each Timer/Counter can be configured in various
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modes, typically based on 8-bit or 16-bit operation. The 8052 product has an additional (third) Timer/Counter. Figure provides us with a brief refresher on what a hardware counter looks like. This is a circuit for a simple 3-bit counter which counts from 0 to 7 and then overflows, setting the overflow flag. A 3-bit counter would not be very useful in a microcomputer so it is more typical to find 8-bit and 16-bit counter circuits.

3 bit counter circuit 8-bit COUNTER OPERATION First let us consider a simple 8-bit counter. Since this is a modulo8 set up we are concerned with 256 numbers in the range 0 to 255

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(28 =256). The counter will count in a continuous sequence as follows: Hex Binary Decimal 00h 00000000 0 01h 00000001 1 02h 00000010 2 ... ... FEh 11111110 254 FFh 11111111 255 00h 00000000 0 here the counter overflows to zero1 01h 00000001 1 etc. etc. We will use Timer/Counter 1 in our examples below.

Supposing we were to initialise this Timer/Counter with a number, say 252, then the counter would overflow after just four event pulses, i.e.: FCh 11111100 252 counter is initialised at 252 FDh 11111101 253
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FEh 11111110 254 FFh 11111111 255 00h 00000000 0 here the counter overflows An 8-bit counter can count 255 events before overflow, and overflows on the 256th. event. When initialised with a predefined value of say 252 it overflows after counting just four events. Thus the number of events to be counted can be programmed by preloading the counter with a given number value. 8-bit TIMER OPERATION The 8051 internally divides the processor clock by 12. If a 12 MHz. processor clock is used then a 1 MHz. instruction rate clock, or a pulse once every microsecond, is realised internally within the chip. If this 1 microsecond pulse is connected to a Timer/Counter input, in place of an event input, then the Timer/Counter becomes a timer which can delay by up to 255 microseconds. There is a clear difference between a timer and a counter. The counter will count events, up to 255 events before overflow, and the timer will count time pulses, thus creating delays up to 255 microseconds in our example.

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If the timer is initialised to zero it will count 256 microseconds before overflow. If the timer is initialised to a value of 252, for example, it will count just 4 microseconds before overflow. Thus this timer is programmable between 1 microsecond and 256 microsecond. The 8051 Instruction Set

Program StatusWord The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU. The PSW, shown in Table 1-1 on page 3, resides in SFR space. It contains the Carry bit, the Auxiliary Carry (for BCD operations), the two register bank select bits, the Overflow flag, a parity bit, and two user-definable status flags. The Carry bit, other than serving the functions of a Carry bit in arithmetic operations, also serves as the Accumulator for a number of Boolean operations. The bits RS0 and RS1 are used to select one of the four register banks shown below. A number of instructions refer to these RAM locations as R0 through R7. The selection
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of which of the four banks is being referred to is made on the basis of the bits RS0 and RS1 at execution time. The parity bit reflects the number of 1s in the Accumulator: P = 1 if the Accumulator contains an odd number of 1s, and P = 0 if the Accumulator contains an even number of 1s. Thus the number of 1s in the Accumulator plus P is always even. Two bits in the PSW are uncommitted and may be used as general purpose status flags 1.2 AddressingModes The addressing modes in the 8051 instruction set are as follows: 1.2.1 Direct Addressing In direct addressing the operand is specified by an 8-bit address field in the instruction. Only 128 Lowest bytes of internal Data RAM and SFRs can be directly addressed. 1.2.2 Indirect Addressing In indirect addressing the instruction specifies a register which contains the address of the operand. Both internal and external RAM can be indirectly addressed. The address register for 8-bit addresses can be R0 or R1 of the selected register bank, or the Stack Pointer. The address register for 16-bit addresses can only be the 16-bit data pointer register, DPTR 1.2.3 RegisterInstructions The register banks, containing registers R0 through R7, can be accessed by certain instructions which carry a 3-bit register specification within the opcode of the instruction. Instructions that access the registers this way are code efficient, since this mode eliminates
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an address byte. When the instruction is executed, one of the eight registers in the selected bank is accessed. One of four banks is selected at execution time by the two bank select bits in the PSW. 1.2.4 Register-specific Instructions Some instructions are specific to a certain register. For example, some instructions always operate on the Accumulator, or Data Pointer, etc., so no address byte is needed to point to it. The opcode does this itself. Instructions that refer to the Accumulator as A assemble as accumulator-specific opcodes. 1.2.5 ImmediateConstants The value of a constant can follow the opcode in Program Memory. For example; MOV A, # 100 loads the Accumulator with the decimal number 100. The same number could be specified in hex digits as 64H. 1.2.6 Indexed Addressing Only Program Memory can be accessed with indexed addressing, and it can only be read. This addressing mode is intended for reading look-up tables in Program Memory. A 16-bit base register (either DPTR or the Program Counter) points to the base of the table, and the Accumulator is set up with the table entry number. The address of the table entry in Program Memory is formed by adding the Accumulator data to the base pointer. Another type of indexed addressing is used in the case jump instruction. In this case
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the destination address of a jump instruction is computed as the sum of the base pointer and the Accumulator data. ArithmeticInstructions The menu of arithmetic instructions is listed in Table 1-2. The table indicates the addressing modes that can be used with each instruction to access the <byte> operand. For example, the ADD A, <byte> instruction can be written as: ADD A,7FH (direct addressing) ADD A,@ R0(indirect addressing) ADD A,R7 (register addressing) ADD A,# 127(immediate constant) One of the INC instructions operates on the 16-bit Data Pointer. The Data Pointer isused to generate 16-bit addresses for external memory, so being able to increment it inone 16-bit operation is a useful feature. The MUL AB instruction multiplies the Accumulator by the data in the B register and puts the 16-bit product into the concatenated B and Accumulator registers. The DIV AB instruction divides the Accumulator by the data in the B register and leaves the 8-bit quotient in the Accumulator, and the 8-bit remainder in the B register. Oddly enough, DIV AB finds less use in arithmetic divide routines than in radix conversions and programmable shift operations. An example of the use of DIV AB in a radix conversion will be given later. In shift operations, dividing a number by 2n shifts its n bits to the right. Using DIV AB to perform the division completes the shift in 4 s leaves the B register holding the bits that were shifted out.
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The DA A instruction is for BCD arithmetic operations. In BCD arithmetic ADD and ADDC instructions should always be followed by a DA A operation, to ensure that the result is also in BCD. Note that DAA will not convert a binary number to BCD. The DA A operation produces a meaningful result only as the second step in the addition of two BCD bytes. 1.4 LogicalInstructions The instructions that perform Boolean operations (AND, OR, Exclusive OR, NOT) on bytes perform the operation on a bit-bybit basis. That is, if the Accumulator contains 00110101B and <byte> contains 01010011B, then ANL A,<byte> will leave the Accumulator holding 00010001B. The addressing modes that can be used to access the <byte> operand are listed in Thus, the ANL A, <byte> instruction may take any of the following forms. ANL A, 7FH(direct addressing) ANL A, @ R1(indirect addressing) ANL A, R6(register addressing) ANL A, # 53H(immediate constant) All of the logical instructions that are Accumulator specific execute in 1 s (using a 12 MHz clock and X1 mode). ORL performs the bitwise logical-OR operation between the indicated variables, storing the results in the destination byte. No flags are affected.
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The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the Accumulator or immediate data. Note: When this instruction is used to modify an output port, the value used as the original port data is read from the output data latch, not the input pins. Example: If the Accumulator holds 0C3H (11000011B) and R0 holds 55H (01010101B) then the following instruction, ORL A,R0 leaves the Accumulator holding the value 0D7H (1101011lB).When the destination is a directly addressed byte, the instruction can set combinations of bits in any RAM location or hardware register. The pattern of bits to be set is determined by a mask byte, which may be either a constant data value in the instruction or a variable computed in the Accumulator at run-time. The instruction, ORL P1,#00110010B sets bits 5, 4, and 1 of output Port 1. ORL A,Rn Bytes: 1 Cycles: 1 Encoding: 0 1 0 0 1 r r r Operation: ORL (A) (A) (Rn) ORL A,direct Bytes: 2 Cycles: 1 Encoding: 0 1 0 0 0 1 0 1 direct address Operation: ORL (A) (A) (direct) ORL A,@Ri Bytes: 1 Cycles: 1
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Encoding: 0 1 0 0 0 1 1 i Operation: ORL ORL A,#data Bytes: 2 Cycles: 1 Encoding: 0 1 0 0 0 1 0 0 immediate data Operation: ORL (A) (A) #data ORL direct,A Bytes: 2 Cycles: 1 Encoding: 0 1 0 0 0 0 1 0 direct address Operation: ORL (direct) (direct) (A) ORL direct,#data Bytes: 3 Cycles: 2 Encoding: 0 1 0 0 0 0 1 1 direct addr. immediate data Operation: ORL (direct) (direct) #data Function: Logical-OR for bit variables Description: Set the carry flag if the Boolean value is a logical 1; leave the carry in its current state otherwise. A slash ( / ) preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected. No other flags are affected. Example: Set the carry flag if and only if P1.0 = 1, ACC. 7 = 1, or OV = 0: MOV C,P1.0 ;LOAD CARRY WITH INPUT PIN P10 ORL C,ACC.7 ;OR CARRY WITH THE ACC. BIT 7 ORL C,/OV ;OR CARRY WITH THE INVERSE OF OV. ORL C,bit Bytes: 2 Cycles: 2
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Encoding: 0 1 1 1 0 0 1 0 bit address Operation: ORL (C) (C) (bit) ORL C,/bit Bytes: 2 Cycles: 2 Encoding: 1 0 1 0 0 0 0 0 bit address Operation: ORL (C) (C) (bit) POP direct PUSH direct Function: Pop from stack. Description: The contents of the internal RAM location addressed by the Stack Pointer is read, and the Stack Pointer is decremented by one. The value read is then transferred to the directly addressed byte indicated. No flags are affected. Example: The Stack Pointer originally contains the value 32H, and internal RAM locations 30H through 32H contain the values 20H, 23H, and 01H, respectively. The following instruction sequence, POP DPH POP DPL leaves the Stack Pointer equal to the value 30H and sets the Data Pointer to 0123H. At this point, the following instruction, POP SP leaves the Stack Pointer set to 20H. In this special case, the Stack Pointer was decremented to 2FH before being loaded with the value popped (20H). Bytes: 2 Cycles: 2 Encoding: 1 1 0 1 0 0 0 0 direct address Operation: POP (direct) ((SP))
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(SP) (SP) - 1 Function: Push onto stack Description: The Stack Pointer is incremented by one. The contents of the indicated variable is then copied into the internal RAM location addressed by the Stack Pointer. Otherwise no flags are affected. Example: On entering an interrupt routine, the Stack Pointer contains 09H. The Data Pointer holds the value 0123H. The following instruction sequence, PUSH DPL PUSH DPH leaves the Stack Pointer set to 0BH and stores 23H and 01H in internal RAM locations 0AH and 0BH, respectively. Bytes: 2 Cycles: 2 Encoding: 1 1 0 0 0 0 0 0 direct address Operation: PUSH (SP) (SP) + 1 ((SP)) (direct) RET RETI Function: Return from subroutine Description: RET pops the high- and low-order bytes of the PC successively from the stack, decrementing the Stack Pointer by two. Program execution continues at the resulting address, generally the instruction immediately following an ACALL or LCALL. No flags are affected. Example: The Stack Pointer originally contains the value 0BH. Internal RAM locations 0AH and 0BH contain the values 23H and 01H, respectively. The following instruction, RET leaves the Stack Pointer equal to the value 09H. Program execution continues at location 0123H. Bytes: 1
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Cycles: 2 Encoding: 0 0 1 0 0 0 1 0 Operation: RET (PC15-8) ((SP)) (SP) (SP) - 1 (PC7-0) ((SP)) (SP) (SP) - 1 Function: Return from interrupt Description: RETI pops the high- and low-order bytes of the PC successively from the stack and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed. The Stack Pointer is left decremented by two. No other registers are affected; the PSW is not automatically restored to its pre-interrupt status. Program execution continues at the resulting address, which is generally the instruction immediately after the point at which the interrupt request was detected. If a lower- or same-level interrupt was pending when the RETI instruction is executed, that one instruction is executed before the pending interrupt is processed. Example: The Stack Pointer originally contains the value 0BH. An interrupt was detected during the instruction ending at location 0122H. Internal RAM locations 0AH and 0BH contain the values 23H and 01H, respectively. The following instruction, RETI leaves the Stack Pointer equal to 09H and returns program execution to location 0123H. Bytes: 1 Cycles: 2 Encoding: 0 0 1 1 0 0 1 0 Operation: RETI (PC15-8) ((SP)) (SP) (SP) - 1 (PC7-0) ((SP))
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(SP) (SP) - 1 RL A RLC A Function: Rotate Accumulator Left Description: The eight bits in the Accumulator are rotated one bit to the left. Bit 7 is rotated into the bit 0 position. No flags are affected. Example: The Accumulator holds the value 0C5H (11000101B). The following instruction, RL A leaves the Accumulator holding the value 8BH (10001011B) with the carry unaffected. Bytes: 1 Cycles: 1 Encoding: 0 0 1 0 0 0 1 1 Operation: RL (An + 1) (An) n = 0 - 6 (A0) (A7) Function: Rotate Accumulator Left through the Carry flag Description: The eight bits in the Accumulator and the carry flag are together rotated one bit to the left. Bit 7 moves into the carry flag; the original state of the carry flag moves into the bit 0 position. No other flags are affected. Example: The Accumulator holds the value 0C5H(11000101B), and the carry is zero. The following instruction, RLC A leaves the Accumulator holding the value 8BH (10001010B) with the carry set. Bytes: 1 Cycles: 1 Encoding: 0 0 1 1 0 0 1 1 Operation: RLC (An + 1) (An) n = 0 - 6 (A0) (C) (C) (A7)
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RR A RRC A Function: Rotate Accumulator Right Description: The eight bits in the Accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7 position. No flags are affected. Example: The Accumulator holds the value 0C5H (11000101B). The following instruction, RR A leaves the Accumulator holding the value 0E2H (11100010B) with the carry unaffected. Bytes: 1 Cycles: 1 Encoding: 0 0 0 0 0 0 1 1 Operation: RR (An) (An + 1) n = 0 - 6 (A7) (A0) Function: Rotate Accumulator Right through Carry flag Description: The eight bits in the Accumulator and the carry flag are together rotated one bit to the right. Bit 0 moves into the carry flag; the original value of the carry flag moves into the bit 7 position. No other flags are affected. Example: The Accumulator holds the value 0C5H (11000101B), the carry is zero. The following instruction, RRC A leaves the Accumulator holding the value 62 (01100010B) with the carry set. Bytes: 1 Cycles: 1 Encoding: 0 0 0 1 0 0 1 1 Operation: RRC (An) (An + 1) n = 0 - 6 (A7) (C) (C) (A0)
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SETB<bit> SJMP rel Function: Set Bit Description: SETB sets the indicated bit to one. SETB can operate on the carry flag or any directly addressable bit. No other flags are affected. Example: The carry flag is cleared. Output Port 1 has been written with the value 34H (00110100B). The following instructions, SETB C SETB P1.0 sets the carry flag to 1 and changes the data output on Port 1 to 35H (00110101B). SETB C Bytes: 1 Cycles: 1 Encoding: 1 1 0 1 0 0 1 1 Operation: SETB (C) 1 SETB bit Bytes: 2 Cycles: 1 Encoding: 1 1 0 1 0 0 1 0 bit address Operation: SETB (bit) 1 Function: Short Jump Description: Program control branches unconditionally to the address indicated. The branch destination is computed by adding the signed displacement in the second instruction byte to the PC, after incrementing the PC twice. Therefore, the range of destinations allowed is from 128 bytes preceding this instruction 127 bytes following it. Example: The label RELADR is assigned to an instruction at program memory location 0123H. The following instruction, SJMP RELADR
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assembles into location 0100H. After the instruction is executed, the PC contains the value 0123H. Note: Under the above conditions the instruction following SJMP is at 102H. Therefore, the displacement byte of the instruction is the relative offset (0123H-0102H) = 21H. Put another way, an SJMP with a displacement of 0FEH is a one-instruction infinite loop. Bytes: 2 Cycles: 2 Encoding: 1 0 0 0 0 0 0 0 rel. address Operation: SJMP (PC) (PC) + 2 (PC) (PC) + rel SUBB A,<src-byte> Function: Subtract with borrow Description: SUBB subtracts the indicated variable and the carry flag together from the Accumulator, leaving the result in the Accumulator. SUBB sets the carry (borrow) flag if a borrow is needed for bit 7 and clears C otherwise. (If C was set before executing a SUBB instruction, this indicates that a borrow was needed for the previous step in a multiple-precision subtraction, so the carry is subtracted from the Accumulator along with the source operand.) AC is set if a borrow is needed for bit 3 and cleared otherwise. OV is set if a borrow is needed into bit 6, but not into bit 7, or into bit 7, but not bit 6. When subtracting signed integers, OV indicates a negative number produced when a negative value is subtracted from a positive value, or a positive result when a positive number is subtracted from a negative number. The source operand allows four addressing modes: register, direct, register-indirect, or immediate.
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Example: The Accumulator holds 0C9H (11001001B), register 2 holds 54H (01010100B), and the carry flag is set. The instruction, SUBB A,R2 will leave the value 74H (01110100B) in the accumulator, with the carry flag and AC cleared but OV set. Notice that 0C9H minus 54H is 75H. The difference between this and the above result is due to the carry (borrow) flag being set before the operation. If the state of the carry is not known before starting a single or multiple-precision subtraction, it should be explicitly cleared by CLR C instruction. SUBB A,Rn Bytes: 1 Cycles: 1 Encoding: 1 0 0 1 1 r r r Operation: SUBB (A) (A) - (C) - (Rn) SUBB A,direct Bytes: 2 Cycles: 1 Encoding: 1 0 0 1 0 1 0 1 direct address Operation: SUBB (A) (A) - (C) - (direct) SUBB A,@Ri Bytes: 1 Cycles: 1 Encoding: 1 0 0 1 0 1 1 i Operation: SUBB (A) (A) - (C) - ((Ri)) SWAP A XCH A,<byte> SUBB A,#data Bytes: 2 Cycles: 1
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Encoding: 1 0 0 1 0 1 0 0 immediate data Operation: SUBB (A) (A) - (C) - #data Function: Swap nibbles within the Accumulator Description: SWAP A interchanges the low- and high-order nibbles (four-bit fields) of the Accumulator (bits 3 through 0 and bits 7 through 4). The operation can also be thought of as a 4-bit rotate instruction. No flags are affected. Example: The Accumulator holds the value 0C5H (11000101B). The instruction, SWAP A leaves the Accumulator holding the value 5CH (01011100B). Bytes: 1 Cycles: 1 Encoding: 1 1 0 0 0 1 0 0 Operation: SWAP (A3-0) D (A7-4) Function: Exchange Accumulator with byte variable Description: XCH loads the Accumulator with the contents of the indicated variable, at the same time writing the original Accumulator contents to the indicated variable. The source/destination operand can use register, direct, or register-indirect addressing. Example: R0 contains the address 20H. The Accumulator holds the value 3FH (0011111lB). Internal RAM location 20H holds the value 75H (01110101B). The following instruction, XCH A,@R0 leaves RAM location 20H holding the values 3FH (00111111B) and 75H (01110101B) in the accumulator. XCH A,Rn Bytes: 1 Cycles: 1 Encoding: 1 1 0 0 1 r r r Operation: XCH (A) D ((Rn)XCH A,direct
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XCHD A,@Ri Bytes: 2 Cycles: 1 Encoding: 1 1 0 0 0 1 0 1 direct address Operation: XCH (A) D (direct) XCH A,@Ri Bytes: 1 Cycles: 1 Encoding: 1 1 0 0 0 1 1 i Operation: XCH (A) D ((Ri)) Function: Exchange Digit Description: XCHD exchanges the low-order nibble of the Accumulator (bits 3 through 0), generally representing a hexadecimal or BCD digit, with that of the internal RAM location indirectly addressed by the specified register. The high-order nibbles (bits 7-4) of each register are not affected. No flags are affected. Example: R0 contains the address 20H. The Accumulator holds the value 36H (00110110B). Internal RAM location 20H holds the value 75H (01110101B). The following instruction, XCHD A,@R0 leaves RAM location 20H holding the value 76H (01110110B) and 35H (00110101B) in the Accumulator. Bytes: 1 Cycles: 1 Encoding: 1 1 0 1 0 1 1 i Operation: XCHD (A3-0) D ((Ri3-0)) XRL <destbyte>,<src-byte> Function: Logical Exclusive-OR for byte variables Description: XRL performs the bitwise logical Exclusive-OR operation between the indicated variables, storing the results in the destination. No flags are affected.
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The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the Accumulator or immediate data. Note: When this instruction is used to modify an output port, the value used as the original port data is read from the output data latch, not the input pins. Example: If the Accumulator holds 0C3H (1100001lB) and register 0 holds 0AAH (10101010B) then the instruction, XRL A,R0 leaves the Accumulator holding the value 69H (01101001B). When the destination is a directly addressed byte, this instruction can complement combinations of bits in any RAM location or hardware register. The pattern of bits to be complemented is then determined by a mask byte, either a constant contained in the instruction or a variable computed in the Accumulator at run-time. The following instruction, XRL P1,#00110001B complements bits 5, 4, and 0 of output Port 1. XRL A,Rn Bytes: 1 Cycles: 1 Encoding: 0 1 1 0 1 r r r Operation: XRL (A) (A) V (Rn) XRL A,direct Bytes: 2 Cycles: 1 Encoding: 0 1 1 0 0 1 0 1 direct address Operation: XRL (A) (A) V (direct) XRL A,@Ri Bytes: 1
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Cycles: 1 Encoding: 0 1 1 0 0 1 1 i Operation: XRL (A) (A) V (Ri) XRL A,@#data Bytes: 2 Cycles: 1 Encoding: 0 1 1 0 0 1 0 0 immediate data Operation: XRL (A) (A) V #data XRL direct,A Bytes: 2 Cycles: 1 Encoding: 0 1 1 0 0 0 1 0 direct address Operation: XRL (direct) (direct) V (A) DIVAB Function: Divide Description: DIV AB divides the unsigned eight-bit integer in the Accumulator by the unsigned eight-bit integer in register B. The Accumulator receives the integer part of the quotient; register B receives the integer remainder. The carry and OV flags are cleared. Exception: if B had originally contained 00H, the values returned in the Accumulator and B-register are undefined and the overflow flag are set. The carry flag is cleared in any case. Example: The Accumulator contains 251 (0FBH or 11111011B) and B contains 18 (12H or 00010010B). The following instruction, DIV AB leaves 13 in the Accumulator (0DH or 00001101B) and the value 17 (11H or 00010001B) in B, since 251 = (13 x 18) + 17. Carry and OV are both cleared. Bytes: 1
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Cycles: 4 Encoding: 1 0 0 0 0 1 0 0 Operation: DIV DJNZ<byte>,<reladdr> Function: Decrement and Jump if Not Zero Description: DJNZ decrements the location indicated by 1, and branches to the address indicated by the second operand if the resulting value is not zero. An original value of 00H underflows to 0FFH. No flags are affected. The branch destination is computed by adding the signed relative-displacement value in the last instruction byte to the PC, after incrementing the PC to the first byte of the following instruction. The location decremented may be a register or directly addressed byte. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. Example: Internal RAM locations 40H, 50H, and 60H contain the values 01H, 70H, and 15H, respectively. The following instruction sequence, DJNZ 40H,LABEL_1 DJNZ 50H,LABEL_2 DJNZ 60H,LABEL_3 causes a jump to the instruction at label LABEL_2 with the values 00H, 6FH, and 15H in the three RAM locations. The first jump was not taken because the result was zero. This instruction provides a simple way to execute a program loop a given number of times or for adding a moderate time delay (from 2 to 512 machine cycles) with a single instruction. The following instruction sequence, MOV R2, # 8 TOGGLE: CPL P1.7 DJNZ R2,TOGGLE
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toggles P1.7 eight times, causing four output pulses to appear at bit 7 of output Port 1. Each pulse lasts three machine cycles; two for DJNZ and one to alter the pin. DJNZ Rn,rel Bytes: 2 Cycles: 2 Encoding: 1 1 0 1 1 r r r rel. address Operation: DJNZ (PC) (PC) + 2 (Rn) (Rn) - 1 IF (Rn) > 0 or (Rn) < 0 THEN (PC) (PC) + rel DJNZ direct,rel Bytes: 3 Cycles: 2 Encoding: 1 1 0 1 0 1 0 1 direct address rel. address Operation: DJNZ (PC) (PC) + 2 (direct) (direct) - 1 IF (direct) > 0 or (direct) < 0 THEN (PC) (PC) + rel INC<byte> Function: Increment Description: INC increments the indicated variable by 1. An original value of 0FFH overflows to 00H. No flags are affected. Three addressing modes are allowed: register, direct, or registerindirect. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. Example: Register 0 contains 7EH (011111110B). Internal RAM locations 7EH and 7FH contain 0FFH and 40H, respectively. The following instruction sequence,
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INC @R0 INC R0 INC @R0 leaves register 0 set to 7FH and internal RAM locations 7EH and 7FH holding 00H and 41H, respectively. INC A Bytes: 1 Cycles: 1 Encoding: 0 0 0 0 0 1 0 0 Operation: INC (A) (A) + 1 INC Rn Bytes: 1 Cycles: 1 Encoding: 0 0 0 0 1 r r r Operation: INC (Rn) (Rn) + 1 INC direct Bytes: 2 Cycles: 1 Encoding: 0 0 0 0 0 1 0 1 direct address Operation: INC (direct) (direct) + 1 INC @Ri Bytes: 1 Cycles: 1 Encoding: 0 0 0 0 0 1 1 i Operation: INC ((Ri)) ((Ri)) + 1 INC DPTR JB blt,rel Function: Increment Data Pointer Description: INC DPTR increments the 16-bit data pointer by 1. A 16-bit increment (modulo 216) is performed, and an
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overflow of the low-order byte of the data pointer (DPL) from 0FFH to 00H increments the high-order byte (DPH). No flags are affected. This is the only 16-bit register which can be incremented. Example: Registers DPH and DPL contain 12H and 0FEH, respectively. The following instruction sequence, INC DPTR INC DPTR INC DPTR changes DPH and DPL to 13H and 01H. Bytes: 1 Cycles: 2 Encoding: 1 0 1 0 0 0 1 1 Operation: INC (DPTR) (DPTR) + 1 Function: Jump if Bit set Description: If the indicated bit is a one, JB jump to the address indicated; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relativedisplacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified. No flags are affected. Example: The data present at input port 1 is 11001010B. The Accumulator holds 56 (01010110B). The following instruction sequence, JB P1.2,LABEL1 JB ACC. 2,LABEL2 causes program execution to branch to the instruction at label LABEL2. Bytes: 3 Cycles: 2 Encoding: 0 0 1 0 0 0 0 0 bit address rel. address Operation: JB (PC) (PC) + 3
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IF (bit) = 1 THEN (PC) (PC) + rel JBC bit,rel JC rel Function: Jump if Bit is set and Clear bit Description: If the indicated bit is one, JBC branches to the address indicated; otherwise, it proceeds with the next instruction. The bit will not be cleared if it is already a zero. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. No flags are affected. Note: When this instruction is used to test an output pin, the value used as the original data will be read from the output data latch, not the input pin. Example: The Accumulator holds 56H (01010110B). The following instruction sequence, JBC ACC.3,LABEL1 JBC ACC.2,LABEL2 causes program execution to continue at the instruction identified by the label LABEL2, with the Accumulator modified to 52H (01010010B). Bytes: 3 Cycles: 2 Encoding: 0 0 0 1 0 0 0 0 bit address rel. address Operation: JBC (PC) (PC) + 3 IF (bit) = 1 THEN (bit) 0 (PC) (PC) +rel Function: Jump if Carry is set Description: If the carry flag is set, JC branches to the address indicated; otherwise, it proceeds with the next instruction. The
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branch destination is computed by adding the signed relativedisplacement in the second instruction byte to the PC, after incrementing the PC twice. No flags are affected. Example: The carry flag is cleared. The following instruction sequence, JC LABEL1 CPL C JC LABEL 2 sets the carry and causes program execution to continue at the instruction identified by the label LABEL2. Bytes: 2 Cycles: 2 Encoding: 0 1 0 0 0 0 0 0 rel. address Operation: JC (PC) (PC) + 2 IF (C) = 1 THEN (PC) (PC) + rel JMP @A+DPTR JNB bit,rel Function: Jump indirect Description: JMP @A+DPTR adds the eight-bit unsigned contents of the Accumulator with the 16-bit data pointer and loads the resulting sum to the program counter. This is the address for subsequent instruction fetches. Sixteen-bit addition is performed (modulo 216): a carry-out from the loworder eight bits propagates through the higher-order bits. Neither the Accumulator nor the Data Pointer is altered. No flags are affected. Example: An even number from 0 to 6 is in the Accumulator. The following sequence of instructions branches to one of four AJMP instructions in a jump table starting at JMP_TBL. MOV DPTR, # JMP_TBL JMP @A + DPTR JMP_TBL: AJMP LABEL0
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AJMP LABEL1 AJMP LABEL2 AJMP LABEL3 If the Accumulator equals 04H when starting this sequence, execution jumps to label LABEL2. Because AJMP is a 2-byte instruction, the jump instructions start at every other address. Bytes: 1 Cycles: 2 Encoding: 0 1 1 1 0 0 1 1 Operation: JMP (PC) (A) + (DPTR) Function: Jump if Bit Not set Description: If the indicated bit is a 0, JNB branches to the indicated address; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relativedisplacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified. No flags are affected. Example: The data present at input port 1 is 11001010B. The Accumulator holds 56H (01010110B). The following instruction sequence, JNB P1.3,LABEL1 JNB ACC.3,LABEL2 causes program execution to continue at the instruction at label LABEL2. Bytes: 3 Cycles: 2 Encoding: 0 0 1 1 0 0 0 0 bit address rel. address Operation: JNB (PC) (PC) + 3 IF (bit) = 0 THEN (PC) (PC) + rel
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JNC rel JNZ rel Function: Jump if Carry not set Description: If the carry flag is a 0, JNC branches to the address indicated; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signal relativedisplacement in the second instruction byte to the PC, after incrementing the PC twice to point to the next instruction. The carry flag is not modified. Example: The carry flag is set. The following instruction sequence, JNC LABEL1 CPL C JNC LABEL2 clears the carry and causes program execution to continue at the instruction identified by the label LABEL2. Bytes: 2 Cycles: 2 Encoding: 0 1 0 1 0 0 0 0 rel. address Operation: JNC (PC) (PC) + 2 IF (C) = 0 THEN (PC) (PC) + rel Function: Jump if Accumulator Not Zero Description: If any bit of the Accumulator is a one, JNZ branches to the indicated address; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The Accumulator is not modified. No flags are affected. Example: The Accumulator originally holds 00H. The following instruction sequence, JNZ LABEL1 INC A JNZ LABEL2
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sets the Accumulator to 01H and continues at label LABEL2. Bytes: 2 Cycles: 2 Encoding: 0 1 1 1 0 0 0 0 rel. address Operation: JNZ (PC) (PC) + 2 IF (A) 0 THEN (PC) (PC) + rel JZ rel LCALLaddr16 Function: Jump if Accumulator Zero Description: If all bits of the Accumulator are 0, JZ branches to the address indicated; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The Accumulator is not modified. No flags are affected. Example: The Accumulator originally contains 01H. The following instruction sequence, JZ LABEL1 DEC A JZ LABEL2 changes the Accumulator to 00H and causes program execution to continue at the instruction identified by the label LABEL2. Bytes: 2 Cycles: 2 Encoding: 0 1 1 0 0 0 0 0 rel. address Operation: JZ (PC) (PC) + 2 IF (A) = 0 THEN (PC) (PC) + rel Function: Long call
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Description: LCALL calls a subroutine located at the indicated address. The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16bit result onto the stack (low byte first), incrementing the Stack Pointer by two. The high-order and loworder bytes of the PC are then loaded, respectively, with the second and third bytes of the LCALL instruction. Program execution continues with the instruction at this address. The subroutine may therefore begin anywhere in the full 64K byte program memory address space. No flags are affected. Example: Initially the Stack Pointer equals 07H. The label SUBRTN is assigned to program memory location 1234H. After executing the instruction, LCALL SUBRTN at location 0123H, the Stack Pointer will contain 09H, internal RAM locations 08H and 09H will contain 26H and 01H, and the PC will contain 1234H. Bytes: 3 Cycles: 2 Encoding: 0 0 0 1 0 0 1 0 addr15-addr8 addr7-addr0 Operation: LCALL (PC) (PC) + 3 (SP) (SP) + 1 ((SP)) (PC7-0) (SP) (SP) + 1 ((SP)) (PC15-8) (PC) addr15-0 LJMPaddr16 MOV <destbyte>,<src-byte> Function: Long Jump Description: LJMP causes an unconditional branch to the indicated address, by loading the high-order and low-order bytes of the PC (respectively) with the second and third instruction bytes. The destination may therefore be anywhere in
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the full 64K program memory address space. No flags are affected. Example: The label JMPADR is assigned to the instruction at program memory location 1234H. The instruction, LJMP JMPADR at location 0123H will load the program counter with 1234H. Bytes: 3 Cycles: 2 Encoding: 0 0 0 0 0 0 1 0 addr15-addr8 addr7-addr0 Operation: LJMP (PC) addr15-0 Function: Move byte variable Description: The byte variable indicated by the second operand is copied into the location specified by the first operand. The source byte is not affected. No other register or flag is affected. This is by far the most flexible operation. Fifteen combinations of source and destination addressing modes are allowed. Example: Internal RAM location 30H holds 40H. The value of RAM location 40H is 10H. The data present at input port 1 is 11001010B (0CAH). MOV R0,#30H ;R0 < = 30H MOV A,@R0 ;A < = 40H MOV R1,A ;R1 < = 40H MOV B,@R1 ;B < = 10H MOV @R1,P1 ;RAM (40H) < = 0CAH MOV P2,P1 ;P2 #0CAH leaves the value 30H in register 0, 40H in both the Accumulator and register 1, 10H in register B, and 0CAH (11001010B) both in RAM location 40H and output on port 2. MOV A,Rn Bytes: 1 Cycles: 1 Encoding: 1 1 1 0 1 r r r Operation: MOV (A) (Rn)
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*MOV A,direct Bytes: 2 Cycles: 1 Encoding: 1 1 1 0 0 1 0 1 direct address Operation: MOV (A) (direct) * MOV A,ACC is not a valid Instruction. MOV A,@Ri Bytes: 1 Cycles: 1 Encoding: 1 1 1 0 0 1 1 i Operation: MOV (A) ((Ri)) MOV A,#data Bytes: 2 Cycles: 1 Encoding: 0 1 1 1 0 1 0 0 immediate data Operation: MOV (A) #data MOV Rn,A Bytes: 1 Cycles: 1 Encoding: 1 1 1 1 1 r r r Operation: MOV (Rn) (A) MOV Rn,direct Bytes: 2 Cycles: 2 Encoding: 1 0 1 0 1 r r r direct addr. Operation: MOV (Rn) (direct) MOV Rn,#data Bytes: 2 Cycles: 1 Encoding: 0 1 1 1 1 r r r immediate data
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Operation: MOV (Rn) #data MOV direct,A Bytes: 2 Cycles: 1 Encoding: 1 1 1 1 0 1 0 1 direct address Operation: MOV (direct) (A) MOV direct,Rn Bytes: 2 Cycles: 2 Encoding: 1 0 0 0 1 r r r direct address Operation: MOV (direct) (Rn) MOV direct,direct Bytes: 3 Cycles: 2 Encoding: 1 0 0 0 0 1 0 1 dir. addr. (scr) dir. addr. (dest) Operation: MOV (direct) (direct) MOV direct,@Ri Bytes: 2 Cycles: 2 Encoding: 1 0 0 0 0 1 1 i direct addr. Operation: MOV (direct) ((Ri)) MOV direct,#data Bytes: 3 Cycles: 2 Encoding: 0 1 1 1 0 1 0 1 direct address immediate data Operation: MOV (direct) #data MOV @Ri,A Bytes: 1 Cycles: 1
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Encoding: 1 1 1 1 0 1 1 i Operation: MOV ((Ri)) (A) 1.14.29 MOV <destbit>,< src-bit> MOV @Ri,direct Bytes: 2 Cycles: 2 Encoding: 1 0 1 0 0 1 1 i direct addr. Operation: MOV ((Ri)) (direct) MOV @Ri,#data Bytes: 2 Cycles: 1 Encoding: 0 1 1 1 0 1 1 i immediate data Operation: MOV ((Ri)) #data Function: Move bit data Description: MOV <dest-bit>,<src-bit> copies the Boolean variable indicated by the second operand into the location specified by the first operand. One of the operands must be the carry flag; the other may be any directly addressable bit. No other register or flag is affected. Example: The carry flag is originally set. The data present at input Port 3 is 11000101B. The data previously written to output Port 1 is 35H (00110101B). MOV P1.3,C MOV C,P3.3 MOV P1.2,C leaves the carry cleared and changes Port 1 to 39H (00111001B). MOV C,bit Bytes: 2 Cycles: 1 Encoding: 1 0 1 0 0 0 1 0 bit address Operation: MOV
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(C) (bit) MOV bit,C Bytes: 2 Cycles: 2 Encoding: 1 0 0 1 0 0 1 0 bit address Operation: MOV (bit) (C) 1.14.30 MOV DPTR,#data16 1.14.31 MOVC A,@A+ <base-reg> Function: Load Data Pointer with a 16-bit constant Description: MOV DPTR,#data16 loads the Data Pointer with the 16-bit constant indicated. The 16-bit constant is loaded into the second and third bytes of the instruction. The second byte (DPH) is the high-order byte, while the third byte (DPL) holds the lower-order byte. No flags are affected. This is the only instruction which moves 16 bits of data at once. Example: The instruction, MOV DPTR, # 1234H loads the value 1234H into the Data Pointer: DPH holds 12H, and DPL holds 34H. Bytes: 3 Cycles: 2 Encoding: 1 0 0 1 0 0 0 0 immed. data15-8 immed. data7-0 Operation: MOV (DPTR) #data15-0 DPH DPL #data15-8 #data7-0 Function: Move Code byte Description: The MOVC instructions load the Accumulator with a code byte or constant from program memory. The address of the byte fetched is the sum of the original unsigned 8-bit Accumulator contents and the contents of a 16-bit base register, which may be either the Data Pointer or the PC. In the latter case, the PC is incremented to the
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address of the following instruction before being added with the Accumulator; otherwise the base register is not altered. Sixteen-bit addition is performed so a carry-out from the low-order eight bits may propagate through higher-order bits. No flags are affected. Example: A value between 0 and 3 is in the Accumulator. The following instructions will translate the value in the Accumulator to one of four values defined by the DB (define byte) directive. REL_PC: INC A MOVC A,@A+PC RET DB 66H DB 77H DB 88H DB 99H If the subroutine is called with the Accumulator equal to 01H, it returns with 77H in the Accumulator. The INC A before the MOVC instruction is needed to gget around h the RET instruction above the table. If several bytes of code separate the MOVC from the table, the corresponding number is added to the Accumulator instead. 1.14.32 MOVX <destbyte>,< src-byte> MOVC A,@A+DPTR Bytes: 1 Cycles: 2 Encoding: 1 0 0 1 0 0 1 1 Operation: MOVC (A) ((A) + (DPTR)) MOVC A,@A+PC Bytes: 1 Cycles: 2 Encoding: 1 0 0 0 0 0 1 1 Operation: MOVC
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(PC) (PC) + 1 (A) ((A) + (PC)) Function: Move External Description: The MOVX instructions transfer data between the Accumulator and a byte of external data memory, which is why gX h is appended to MOV. There are two types of instructions, differing in whether they provide an 8-bit or 16-bit indirect address to the external data RAM. In the first type, the contents of R0 or R1 in the current register bank provide an 8-bit address multiplexed with data on P0. Eight bits are sufficient for external I/O expansion decoding or for a relatively small RAM array. For somewhat larger arrays, any output port pins can be used to output higher-order address bits. These pins are controlled by an output instruction preceding the MOVX. In the second type of MOVX instruction, the Data Pointer generates a 16-bit address. P2 outputs the high-order eight address bits (the contents of DPH), while P0 multiplexes the low-order eight bits (DPL) with data. The P2 Special Function Register retains its previous contents, while the P2 output buffers emit the contents of DPH. This form of MOVX is faster and more efficient when accessing very large data arrays (up to 64K bytes), since no additional instructions are needed to set up the output ports. It is possible to use both MOVX types in some situations. A large RAM array with its high-order address lines driven by P2 can be addressed via the Data Pointer, or with code to output high-order address bits to P2, followed by a MOVX instruction using R0 or R1. Example: An external 256 byte RAM using multiplexed address/data lines is connected to the 8051 Port 0. Port 3 provides control lines for the external RAM. Ports 1 and 2 are used for normal I/O. Registers 0 and 1 contain 12H and 34H. Location 34H of the external RAM holds the value 56H. The instruction sequence,
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MOVX A,@R1 MOVX @R0,A copies the value 56H into both the Accumulator and external RAM location 12H. MOVX A,@Ri Bytes: 1 Cycles: 2 Encoding: 1 1 1 0 0 0 1 i 1.14.33 MUL AB Operation: MOVX (A) ((Ri)) MOVX A,@DPTR Bytes: 1 Cycles: 2 Encoding: 1 1 1 0 0 0 0 0 Operation: MOVX (A) ((DPTR)) MOVX @Ri,A Bytes: 1 Cycles: 2 Encoding: 1 1 1 1 0 0 1 i Operation: MOVX ((Ri)) (A) MOVX @DPTR,A Bytes: 1 Cycles: 2 Encoding: 1 1 1 1 0 0 0 0 Operation: MOVX (DPTR) (A) Function: Multiply Description: MUL AB multiplies the unsigned 8-bit integers in the Accumulator and register B. The low-order byte of the 16-bit product is left in the Accumulator, and the high-order byte in B. If the product is greater than 255 (0FFH), the
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overflow flag is set; otherwise it is cleared. The carry flag is always cleared. Example: Originally the Accumulator holds the value 80 (50H). Register B holds the value 160 (0A0H). The instruction, MUL AB will give the product 12,800 (3200H), so B is changed to 32H (00110010B) and the Accumulator is cleared. The overflow flag is set, carry is cleared. Bytes: 1 Cycles: 4 Encoding: 1 0 1 0 0 1 0 0 Operation: MUL (A)7-0 (A) X (B) (B)15-8 1.14.34 NOP Function: No Operation Description: Execution continues at the following instruction. Other than the PC, no registers or flags are affected. Example: A low-going output pulse on bit 7 of Port 2 must last exactly 5 cycles. A simple SETB/CLR sequence generates a one-cycle pulse, so four additional cycles must be inserted. This may be done (assuming no interrupts are enabled) with the following instruction sequence, CLR P2.7 NOP NOP NOP NOP SETB P2.7 Bytes: 1 Cycles: 1 Encoding: 0 0 0 0 0 0 0 0 Operation: NOP
(PC) (PC) + 1

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Complete microcontroller system: When designing a complete micro controller system, there are many more consideration than merely the choice of micro controller. In todays world of fast and complex embedded system , often times field Programmable Gate Arrays (FPGAs) or Programmable logic device (PLDs) must be included. These devices serves a number of different purposes, but often time they serve as combinational and sequential logic replacement , interface logic implement various operation and function etc. Many of these devices are also program able on the fly, which alloys the system to reconfigure during operation.

When maximum cost and performance efficiency is required, designers can also turn to micro controllers with customizable functionality, right on the chip. Such ASICs (application specific integrated circuits) let designer to add their own logic elements and cells right next to the micro controller core allowing high performance ,single chip solutions. Cost can be drastically reduced to high volume application using ASICs because of decreased chip count, lower power operation, greater integration, etc.

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Other factor under consideration when designing an embedded system include the printed circuit board ( whether to go with a single sided board all the way up to a professionally fabricated 8-layer board) multi voltage power supplies (todays chips use a combination of +5 ,+3.3,+3 and now even +1.8 volts for power), electro magnetic interference shielding FCC certification etc.

Development Tools: In the past, tools used to develop and produce embedded systems were not vary sophisticated, nor did they have to be. However in todays competitive world the difference between a successful micro controller and a failure is the quality of its development tools. Such tools include code assemblers, high level language compiler and support (such as \C and BASIC). Integrated development equipments (IDES), debuggers, emulator, development kit, etc.. The importance of development tools has also brought about a new principle in micro controller design. Many manufacturers are design their micro controller architecture with the sole purpose of making it efficient for high level language, since embedded system designers no longer have the time to write all their code in raw assembly. They must typically reset to C programming many more computer architecture cannot execute code written in C because such high level language depend on efficient memory access. Multiple register is used for temporary space etc.
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however most new architecture have RISC-like designs with many register which alloys efficient execution of C code. In fact there are some architecture can no longer be programmed in assembly language; you must use their C compiler.

Third party software libraries are also becoming very important. It can be difficult to perform certain mathematical operation or functions inside a micro controller, and this is where third party routines play a role. Also important are the development of new Real Time Operating Systems( RTOSs). An RTOSs serves as a task manager in an embedded system. Allocating processor resources to various threads of execution, keeps thing in order, etc RTOSs are generally written in C code and can portable to most any micro controller architecture.

PROBLEM FACED First problem that was in making the circuit of METRO TRAIN PROTOTYPE that, it is difficult to match time with rotation of stepper motor & LCD. Second problem is faced due to redundancy in handling the rotation of STEPPER MOTOR We have to take extra care while soldering 2 line. During soldering, many of the connection become short cktd. So
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We desolder the connection and did soldering again. A leg of the crystal oscillator was broken during mounting. So it has to be replaced. LED`s get damaged when we switched ON the supply so we replace it by the new one.

AT89C52 Description:-

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The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8Kbytes of Flash programmable and erasable read only memory (EPROM). The device is manufactured using Atmels high density nonvolatile memory technology and is compatible with the industry standard 80C51 and 80C52 instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.

Major applications:

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The theme of the project when merged with certain established technologies can be quite effective in number of countries like Germany, France & Japan etc. which control the train . The project when used with an improved sensitivity. The train is programmed for the specific path. Every station on the path is defined; stoppage timing of the train & distance between the two stations is predefined. The circuit diagram is shown in the figure. Here LCD display is connected with the P1 of the MC. Control lines are connected with port 3 of the microcontroller. The contrast of the LCD is controlled by 10K variable resistor. Unipolar Stepper motor is used for running of the train. This motor has 5 wires, which are named as A1, B1, B2, and COM. Common line is given at +5V. The other lines can be connected with port 2 of microcontroller. The stepper motor is derived by the ULN 2003 chip. This Chip includes Darlington pairs, so that motor can get enough current to for its running. This chip required pull ups at inputs. FUTURE SCOPE This Project is useful in dveloping conturies & this project has a bright future as it is being used in countries like Germany, France & Japan. This project helps us to control train without a driver and the stations are shown on the LCD so the passenger doesnt has any difficulty. This project will lead to increase in technological trends & this will help the people in many ways.

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Bibliography:

1. Kenneth J, Ayala 8051 MICROCONTROLLER PRI Publications, second edition 2. J, Wilson PROGRAMING 8051 Pearson publications, third edition 3. D. V. Hall- MICROPROCESSOR ANDINTERFACING Tata McGraw Hill Publications, third edition 4. www.microcontrollers.com/8051/Philips/P89C51RD2 6.http://www.microslectronica.co.yu/english/product/books/PICbo ok/1_chapter/htm#introbuction 7. http://www.pmb.co.nz/hobbycorner/pages/intmicro.htm#definition 8. http://www.win.tue.nl/~aeb/comp/8051/set8051.htm/#51inc

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