Backend physical design Interview Questions

I have listed below a set of common interview questions asked mainly in interviews related to physical design or backend activities in ASIC or VLSI chip design process. Typically these interviews start with questions on physical design(PD) flow and goes on to deeper details. * What is signal integrity? How it affects Timing? * What is IR drop? How to avoid .how it affects timing? * What is EM and it effects? * What is floor plan and power plan? * What are types of routing? * What is a grid .why we need and different types of grids? * What is core and how u will decide w/h ratio for core? * What is effective utilization and chip utilization? * What is latency? Give the types? * What is LEF? * What is DEF? * What are the steps involved in designing an optimal pad ring? * What are the steps that you have done in the design flow? * What are the issues in floor plan? * How can you estimate area of block? * How much aspect ratio should be kept (or have you kept) and what is the utilization? * How to calculate core ring and stripe widths? * What if hot spot found in some area of block? How you tackle this? * After adding stripes also if you have hot spot what to do? * What is threshold voltage? How it affect timing? * What is content of lib, lef, sdc? * What is meant my 9 track, 12 track standard cells? * What is scan chain? What if scan chain not detached and reordered? Is it compulsory? * What is setup and hold? Why there are ? What if setup and hold violates? * In a circuit, for reg to reg path ...Tclktoq is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps. Then what is the maximum operating frequency? * How R and C values are affecting time? * How ohm (R), fared (C) is related to second (T)? * What is transition? What if transition time is more? * What is difference between normal buffer and clock buffer? * What is antenna effect? How it is avoided? * What is ESD? * What is cross talk? How can you avoid? * How double spacing will avoid cross talk? * What is difference between HFN synthesis and CTS? * What is hold problem? How can you avoid it? * For an iteration we have 0.5ns of insertion delay and 0.1 skew and for other iteration

0.29ns insertion delay and 0.25 skew for the same circuit then which one you will select? Why? * What is partial floor plan? * What parameters (or aspects) differentiate Chip Design & Block level design?? * How do you place macros in a full chip design? * Differentiate between a Hierarchical Design and flat design? * Which is more complicated when u have a 48 MHz and 500 MHz clock design? * Name few tools which you used for physical verification? * What are the input files will you give for primetime correlation? * What are the algorithms used while routing? Will it optimize wire length? * How will you decide the Pin location in block level design? * If the routing congestion exists between two macros, then what will you do? * How will you place the macros? * How will you decide the die size? * If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem? * If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using 7LM? * In your project what is die size, number of metal layers, technology, foundry, number of clocks? * How many macros in your design? * What is each macro size and no. of standard cell count? * How did u handle the Clock in your design? * What are the Input needs for your design? * What is SDC constraint file contains? * How did you do power planning? * How to find total chip power? * How to calculate core ring width, macro ring width and strap or trunk width? * How to find number of power pad and IO power pads? * What are the problems faced related to timing? * How did u resolve the setup and hold problem? * If in your design 10000 and more numbers of problems come, then what you will do? * In which layer do you prefer for clock routing and why? * If in your design has reset pin, then itll affect input pin or output pin or both? * During power analysis, if you are facing IR drop problem, then how did u avoid? * Define antenna problem and how did u resolve these problem? * How delays vary with different PVT conditions? Show the graph. * Explain the flow of physical design and inputs and outputs for each step in flow. * What is cell delay and net delay? * What are delay models and what is the difference between them? * What is wire load model? * What does SDC constraints has? * Why higher metal layers are preferred for Vdd and Vss?

* What is logic optimization and give some methods of logic optimization. * What is the significance of negative slack? * How the width of metal and number of straps calculated for power and ground? * What is negative slack ? How it affects timing? * What is track assignment? * What is grided and gridless routing? * What is a macro and standard cell? * What is congestion? * Whether congestion is related to placement or routing? * What are clock trees? * What are clock tree types? * Which layer is used for clock routing and why? * What is cloning and buffering? * What are placement blockages? * How slow and fast transition at inputs effect timing for gates? * What is antenna effect? * What are DFM issues? * What is .lib, LEF, DEF, .tf? * What is the difference between synthesis and simulation? * What is metal density, metal slotting rule? * What is OPC, PSM? * Why clock is not synthesized in DC? * What are high-Vt and low-Vt cells? * What corner cells contains? * What is the difference between core filler cells and metal fillers? * How to decide number of pads in chip level design? * What is tie-high and tie-low cells and where it is used

VHDL Interview Question(s)

1. What are the two key concepts in the simulation semantics of VHDL and how does each
concept help VHDL simulation produce waveforms that match the behaviour that we expect? 2. What is the advantage of RTL simulation in comparison to simulation as defined by the VHDL standard? 3. What is the disadvantage of RTL simulation in comparison to simulation as defined by the VHDL standard? 4. For each of the architectures muruku 1. . . muruku 4, answer the following questions. o INSTRUCTIONS: 1. Is the code legal VHDL? 2. If the code is legal VHDL:  Answer whether the behaviour of the signal z has the same behaviour as in the main architecture of sumit.  Answer whether the code is synthesizable.  If the code is synthesizable, answer whether it adheres to good coding practices. If the the code is not legal, not synthesizable, or does not follow good coding practices, explain why. entity sumit is port ( a, b, clk : in std_logic; z : out std_logic ); end schreyer; architecture main of sumit is signal m : std_logic; begin process ( clk ) begin if rising_edge( clk ) then m <= a or b; end if; end process; process ( clk ) begin if rising_edge( clk ) then z <= not m; end if; end process; end main; 1. Muruku 1

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architecture muruku_1 of sumit is signal m : std_logic; begin process ( clk ) begin if rising_edge( clk ) then m <= a or b; z <= not m; end if; end process; end muruku_1; Muruku_X o architecture muruku_X of sumit is signal m, p : std_logic; begin process ( clk ) begin if rising_edge( clk ) then m <= a or b; end if; end process; process ( clk ) begin if rising_edge( clk ) then z <= p; end if; end process; p <= not m; end muruku_X; Muruku_2 o architecture muruku_2 of sumit is signal m, p : std_logic; begin if (a or b) = 1 generate m <= 1 ; end generate; if (a or b) = 0 generate m <= 0 ; end generate; process ( clk ) begin if rising_edge( clk ) then p <= m; end if; end process; process ( clk ) begin if rising_edge( clk ) then z <= not p; end if; end process; end muruku_2; Muruku_3 o architecture muruku_3 of sumit is begin process begin wait until rising_edge(clk); wait until rising_edge(clk); z <= not (a or b); end process; end muruku_3; Muruku_4 o architecture muruku_4 of sumit is signal m, p : std_logic; begin process ( clk ) begin if rising_edge( clk ) then m <= a or b; end if; end process; process ( clk ) begin if rising_edge( clk ) then p <= m; end if; end process; z <= not p; end muruku_4;
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Gate level simulation - Introduction

With wide acceptance of STA and Formal verification tools by the industry one question still arises in the minds of many, "Why do we need gate level simulation?" The common reasons quoted by many engineers are simple.. 1. To check if reset release, initialization sequence and boot-up is proper. 2. Since Scan insertions occur during and after synthesis, they are not checked by simulations. 3. STA does not analyze asynchronous interfaces. 4. Unwarranted usage of wild cards in static timing constraints set false and multi cycle paths where they dont belong. This can also be due to design changes, misunderstanding or typos. 5. Usage of create_clock instead of using create_generated_clock between clock domains. 6. For switching factor to estimate power. 7. X's in RTL sim can be pessimistic or optimistic. Any unintended dependencies on initial conditions can be found through GLS. 8. Design changes, wrong understanding of the design can lead to incorrect false paths or multicycle paths in the constraints. 9. Can be used to study the activity factor for power estimation. 10. It's an excellent feel good quotient that the design has been implemented correctly.

Some design teams use GLS only in a zero-delay, ideal clock mode to check that the design can come out of reset cleanly or that the test structures have been inserted properly. Other teams do fully back annotated simulation as a way to check that the static timing constraints have been set up correctly. In all cases, getting a gate level simulation up and running is generally accompanied by a series of challenges so frustrating that they precipitate a shower of adjectives as caustic as those typically directed at your most unreliable internet service provider. There are many sources of trouble in gate level simulation. This series will look at examples of problems that can come from your library vendor, problems that come from the design, and problems that can come from synthesis. It will also look at some of the additional challenges that arise when running gate level simulation with back annotated SDF.