Precision Readout Circuits for Capacitive Microaccelerometers

Navid Yazdi, Haluk Kulah, Khalil Najafi

Center of Wireless Integrated Microsystems
University of Michigan, Ann Arbor, MI, USA
nyazdi@umich.edu, najafi@umich.edu
Abstract
This paper presents a review of capacitive readout front-
end circuits for high-precision accelerometers. The
primary design parameters and the trade-offs affecting the
resolution are presented. The discussions apply to all
capacitive microsensor interfaces. Also a high-sensitivity
capacitive accelerometer interface circuit for hybrid-
integration with a surface/bulk micromachined micro-g
accelerometer is described [7, 10]. The first generation of
the circuit resolves 75aF of capacitance on ~120pF
parasitic capacitance with a 200kHz sampling rate, and the
second generation resolves 20aF with 1MHz sampling rate.
The overall sensor-circuit module has a noise floor of
1.6ug/\Hz at ambient atmosphere.
Keywords
Capacitive sensor readout circuit, MEMS accelerometer
interface, micro-g accelerometer
INTRODUCTION
Capacitive accelerometers, and in general capacitive
microsensors, have the main advantages of low-power,
high-sensitivity, relatively simple structure, and inherently
low temperature sensitivity. The capacitive sense
microstructures can be used for electrostatic actuation as
well, which results in reduced complexity of closed-loop
microsensors (or microactuators). The key challenge in
capacitive sensor interfaces is the high impedance readout
node, and its susceptibility to parasitics and EMI. The
overall sensor module performance is affected by sense
element design and technology, readout circuit, and
packaging. The readout circuit design cannot be developed
without considering the sensor and packaging
specifications, since both affect the circuit performance.
Several readout circuits for capacitive MEMS
accelerometers and gyroscopes have been reported [1-10].
These circuits are in three general groups: ac-bridge with
voltage amplifier [1-4], transimpedance amplifier [5],
switched-capacitor circuit [6-10]. First a review of these
capacitive readout circuits and the trade-offs involved in
their performance are presented. Note that the discussions
apply to all capacitive microsensor interfaces. Then, a
high-performance fully-differential switched-capacitor
readout front-end for micro-g accelerometers with high dc
stability is described [7, 10]. The accelerometer uses a
combined surface/bulk micromachining process [11] to
attain high sensitivity and low mechanical noise without the
need for vacuum packaging.
CAPACITIVE SENSOR READOUT FRONT-ENDS
Figure 1 shows the simplified block diagram of the three
main capacitance readout circuits. While in most cases the
microsensor is designed to provide a differential
capacitance output, for a general case a single sense
capacitor with a fixed reference capacitor equal to the sense
rest capacitance (C
r
=C
s0
) is assumed. The readout circuit
detects the capacitance change (AC= C
s
-C
r
). Also a single-
ended readout circuit is considered, and the discussions can
be readily applied to a fully-differential topology which is
advantageous and more commonly used.
1. ac-bridge with voltage amplifier:
In an ac-bridge configuration (Fig. 1-a) [1-4] a half-bridge
consisting of the sense capacitors and reference capacitor is
formed, and driven by two ac signals (digital pulses) with
180 phase difference. A full-bridge configuration can be
formed as well when differential sense-capacitors are
available. The amplitude of the bridge output is
proportional to the capacitance change (AC) and is buffered
(or amplified) by a voltage-mode amplifier. The output
voltage is obtained after a synchronous demodulator and is
given by:
v
p s
p
A
C C
C
V Vout
+
A
=
0
2
(1)
where A
v
is the amplifier gain. In order to minimize the
noise it is desired to increases the ac signal beyond the 1/f
corner frequency of the amplifier. Also increasing the
drive voltage amplitude (V
p
) and reducing the parasitics
(C
p
) improve the minimum detectable capacitance. The
effective input parasitics can be reduced by boot-strapping
where the interconnects from the sensor to the readout
front-end are shielded and the shield is driven by the output
of a unity-gain buffer [4]. This helps to increase the
readout voltage amplitude and in practice improves the
readout resolution where substrate-noise coupling, EMI,
and series connection resistance could contribute to the
overall noise. However, the minimum detectable
capacitance is determined by the thermal noise floor of the
amplitude and is still a function of the total parasitic
capacitance regardless of the feedback for boot-strapping.
Assuming that the ac-bridge drive frequency plus the
sensor output bandwidth is smaller than the amplifier
bandwidth, the lower limit of the capacitance detection is
calculated:
BW V
V
C C
C
rms n
p
p s
rms
+
= A
0
min
2
(2)
0-7803-8692-2/04/$20.00 2004 IEEE. 28
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where V
n-rms
is the input-referred thermal noise floor of the
amplifier and BW is the capacitance detection bandwidth.
2. Transimpedance amplifier:
Figure 1-b shows the transimpedance amplifier readout
scheme. The sense and reference half-bridge is driven by
two ac-signals with 180 phase difference. The bridge
output is held at virtual ground by an operational-amplifier
with resistive feedback (R
f
) and the bridge output current
goes through R
f
. The drive signal needs to be sinusoidal to
avoid errors induced by distortion. This limits the drive
signal amplitude (V
m
) in monolithic implementations.
However, this is not a concern in resonance mode sensors
where a large dc bias voltage at the sensor can be used to
effectively generate a larger sinusoidal output [5]. The
input virtual ground reduces the effect of the parasitics.
The output voltage of the amplifier is proportional to the
drive voltage frequency (f
drive
) and R
f
if f
drive
is smaller than
overall readout circuit bandwidth:
C R V f Vout
f m drive
A = t 2
(3)
However, the pole associated with R
f
limits the bandwidth
[f
p1
=1/(2tR
f
(2C
s
+C
p
))]. Moreover, the amplifier dominant
pole creates an inductive effect resulting in a potential
resonance and larger bandwidth. The maximum output
voltage is obtained at the resonance which yields the
optimal drive frequency:
) 2 ( 2
p s f
amp
opt drive
C C R
GBW
f
+
=

t
(4)
where GBW
amp
is the amplifier gain bandwidth. The noise
performance is typically dominated by the thermal noise of
the feedback resistor as the amplifier noise is minimized.
In this case the minimum detectable capacitance at the
optimal drive frequency is independent of R
f
:
amp
p s B
m
rms
GBW
C C T k
V
BW
C
t
) 2 ( 2
0
min
+
= A

(5)
3. Switched-capacitor circuit:
In a switched capacitor circuit the sense and reference
capacitors are charged with opposite polarity voltages and a
packet of charge proportional to the capacitance difference
is integrated on the input feedback capacitor (C
int
, Fig. 1-c):
int
C
C
V V
p out
A
=
(6)
The amplifier 1/f noise can be cancelled by correlated
double sampling (CDS) [7-10]. The wideband thermal
noise sources of amplifier and the switches are sampled at
the high impedance nodes of the circuit and aliased into the
baseband frequency range. The sampled switch noise (also
referred to as kT/C noise) is dominated by that of feedback
capacitance since this capacitor is typically small to
increase the output voltage. Also by the proper choice of
circuit topology the sampled noise at the sense and
reference capacitor remain the same and cancel each other
(e.g. [7]). The capacitance readout resolution is given by:
( ) ( ) BW TC k
C
C C C T k
f
C
B
out
p s B
s
rms
|
|
.
|

\
|
+
+
= A
int
int 0 2
min
2
) 2 ( 16
1
(7)
where C
out
is the total amplifier output capacitance and f
s
is
the sampling frequency. The first term corresponds to the
sampled amplifier noise power which is doubled due to
CDS for 1/f noise cancellation.
The kT/C
int
noise can be cancelled by sampling and
deducting it from the output as shown in [8-9]. The
sampled noise of the reset switch at the end of o
reset
is
stored on the output capacitor C
o
since o
1
goes low after a
delay with respect to o
reset
. In o
2
the sampled voltage across
C
o
is in series and deducted from the amplifier output
resulting in cancellation of kT/C
int
noise (Fig. 1-d). Note
that the amplifier offset and 1/f noise can be similarly
cancelled using double-sampling at C
o
[9]. In this case the
minimum detectable capacitance is calculated by Eq. (8):
Figure 1: Simplified block diagram of various capacitive readout circuits: (a) ac-bridge with voltage amplifier;
(b) Transimpedance amplifier; (c) Switch-capacitor circuit; (d) Switched-capacitor circuit with kT/C noise reduction.
Cp
Amp
Sync.
Demod.
LPF
Vout
Cs
Cr
Vp+
Vp-
Cp
Amp
Sync.
Demod.
LPF
Vout
Cs
Cr
Vp+
Vp-
Vp+
Vp-
-
+
Cp
Cint
Vout
LPF
o
reset
Cs
Cr
Vp+
Vp-
o
1
o
2
-
+
Cp
Cint
Vout
LPF
o
reset
Cs
Cr
Vp+
Vp-
o
1
o
2
(a)
(c)
-
+
Cp
Cint
Vout
LPF
o
reset
Cs
Cr
Vp+
Vp-
o
1
o
2
Co
o
1
-
+
Cp
Cint
Vout
LPF
Vout
LPF
o
reset
Cs
Cr
Vp+
Vp-
o
1
o
2
Co
o
1
Sync.
Demod.
LPF
Vout
-
+
Rf
Cs
Vm+
Cr
Vm-
Cp
Sync.
Demod.
LPF
Vout
-
+
Rf
Cs
Vm+
Cr
Vm-
Cp
(b)
(d)
29
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( ) BW
C
C C C T k
f
C
out
p s B
s
rms
|
|
.
|

\
|
+
= A

int 0
min
) 2 ( 16
1 (8)
4. Comparison of capacitive readout schemes:
The capacitance readout schemes are compared based on
their readout resolution using equations (2), (5), (7), and
(8). These equations provide the minimum achievable
capacitance based on thermal noise limit. However, as
mentioned in the previous section other noise sources
including substrate-noise coupling, EMI, and series
interconnect resistance noise can result in an overall worse
capacitance readout resolution in practice.
Figure 2 presents the capacitance resolution for various
readout schemes with V
p
=3V and V
m
=1V as the input
parasitics and some of the circuit parameters change. As
expected the resolution for ac-bridge with voltage amplifier
increases linearly with parasitics and input referred
amplifier noise. For a transimpedance amplifier the
minimum detectable capacitance improves as the amplifier
gain bandwidth increases (10MHz & 50MHz plotted). The
SC circuit readout resolution is plotted when C
out
=15pF,
C
int
=0.5pF, and for two sampling frequencies of 500kHz
and 2MHz. The resolution improves as the sampling
frequency increases, and significant improvement is
obtained when kT/C noise is cancelled. The virtual ground
at the input of transimpedance amplifier and SC readout
circuits reduce the input parasitic capacitance effect. The
AC-bridge provides the best performance when parasitics
are small. The SC scheme is suitable for the cases when
input parasitics are large due to non-monolithic integration.
Figure 3 shows the capacitance resolution vs. C
p
for two
cases of C
s0
=100fF and C
s0
=1pF as input parasitics change.
The minimum detectable capacitance increases as the sense
capacitance becomes larger. Also the input parasitics
threshold above which the SC circuits perform better than
the ac-bridge with voltage amplifier is reduced in this case.
MICRO-G ACCELEROMETER READOUT CIRCUIT
Meeting the overall sensor module performance target
requires proper choice and optimization of the sensor and
its fabrication technology, readout circuit, and package. A
Figure 4: Switched-capacitor readout circuit for micro-g accelerometer. The main clock phases are o
p
: precharge; o
1
:
readout phase; o
2
: Offset sampling for CDS; o
f
: Feedback phase for closed-loop operation mode; o
sw
: Sense electrode
in readout & feedback phases. Reset phase (reset) and o
2
are the same.
Figure 2: Capacitance readout resolution versus input
capacitance parasitics (C
s0
=250fF) for various readout schemes.
Figure 3: Minimum detectable capacitance as the
parasitics and sense rest capacitance change.
30
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micro-g accelerometer requires both high capacitance
sensitivity and low-mechanical noise that can be achieved
by surface-bulk micromachined accelerometer [11].
However, unlike surface-micromachined accelerometers
monolithic circuit integration is not available and therefore
SC readout circuit is more suitable.
As evident from equations (6)-(8), the signal-to-noise ratio
of the SC front-end can be improved by reducing C
int
.
However, in practice C
int
cannot be reduced arbitrarily due
to switching noise and dynamic range considerations. Even
in a fully-differential SC topology the matching
requirements limit the performance with small C
int
. Figure
4 shows the schematic diagram of a switched capacitor
readout front-end which uses CDS for amplifier finite gain,
1/f noise and offset cancellation, and chopper-stabilization
of the switches to improve the matching, and to further
reduce the offset [7,10]. The CDS is implemented by
sampling the input amplifier offset on C
o
in o
2
. Chopper-
stabilization is implemented by alternating the switches at
the high impedance nodes between the two differential
signal paths. The first generation of this circuit
implemented in 1.2um 5V CMOS process resolves 75aF of
capacitance on ~120pF total sense and parasitic capacitance
with a 200kHz sampling rate. The combined micro-g
accelerometer and interface chip module (Fig. 5) achieves
Table 1: Summary of the sensor module performance.
Surface-Bulk Micromachined Accelerometer
Sensitivity
1.3pF/g (2x1mm
2
bridge)
6pF/g (4x1mm
2
bridge)
20pF/g (2x1mm
2
cantilever)
Sense + parasitic capacitance > 80pF
Mechanical Noise 0.39ug/\Hz @ 1 atmosphere
2
nd
Generation Readout Circuit
Sampling clock 1MHz
Power dissipation <12mW @ 5V
Capacitance sensitivity 0.2-1.2V/pF (adjustable)
Resolution <20aF
Sensor and Readout Circuit Module
Sensitivity 0.26-1.6V/g (2x1mm
2
bridge)
Open-loop resolution <1.6g/Hz (2x1mm
2
bridge)
Full scale range 1.35g with 5V supply
a sensitivity of 430 mV/g and a resolution of 3.5ug/\Hz
[10]. The offset is reduced by >7x to ~82ppm of the full-
scale output range when chopper stabilization is employed.
The second generation of this circuit implemented in 0.5um
CMOS resolves 20aF with 1MHz sampling rate, and has a
resolution of 1.6ug/\Hz at ambient pressure [10].
SUMMARY
This paper presents a review of capacitive readout circuits
and the trade-offs involved in their performance. Also a
high-performance switched-capacitor readout front-end for
micro-g accelerometers with high dc stability is described.
The hybrid-packaged interface circuit with an all-silicon
microaccelerometer fabricated in a combined surface and
bulk process has a resolution of 1.6ug/\Hz at ambient
pressure.
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R.G. Marcheselli, An integrated force-balanced capacitive
accelerometer for low-g applications, 1995 IEEE Conf. on
Solid-State Sensors & Actuators, June 1995, pp. 593-596.
[3] J. Wu, G.K. Fedder, L.R. Carley, A low-noise low-offset
capacitive sensing amplifier for a 50-ug/\Hz monolithic
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Circuits, vol. 39, May 2004, pp. 722-730.
[4] W. Yun, R.T. Howe, and P.R. Gray, Surface
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Figure 5: Hybrid-packaged micro-g accelerometer
and the capacitive interface chip.
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