Courses In Electrical Engineering

Volume II DIGITAL ELECTRONICS CHAPTER SIX: COMBINATORY LOGIC

By J-P. NGOUNE DIPET I (Electrotechnics), DIPET II (Electrotechnics) DEA (Electrical Engineering) Teacher in the Electrical Department, GTHS KUMBO, Cameroon.

Digital Electronics_Jean-Paul NGOUNE

Chapter Six

COMBINATORY LOGIC
6.0 Specific objectives: At the end of this chapter, the student will be able to: Design basic combinatory logic circuits such as the adder, the decoder, the encoder, the transcoder, the multiplexer, and the demultiplexer. Give the applications of those circuits in various domains of Engineering Sciences. 6.1 Introduction: Complex digital systems like computers are made up of many simple combinatory, sequential and hybrid (combinatory and sequential) circuits connected together. A combinatory logic circuit is a logic circuit whose outputs depends only on the combination of its inputs logic states. One of the most important circuits of a computer, which is the Arithmetical and Logical Unit (ALU), is made up of simple circuits capable of performing operations such as addition, multiplication, subtraction and division. The aim of this chapter is to learn how to design simple combinatory circuits used in the conception of digital systems.

6.2 Principle of addition in digital systems: Computers can add only two binary numbers at once. These numbers can have up to 64 bits, with respect to the width of the data bus of the mother board. Let us consider two binary numbers of 5 bits each to be added. 10111 + 00101 11100 00111 Number A Number B Sum (A + B) Carry out

We start the operation by adding the two LSB of the numbers A and B: 1 + 1 = 102 (Sum = 0; Carry out = 1). The carry out is added to the bits of the rank situated immediately at the left.
Digital Electronics_Jean-Paul NGOUNE

The same operation will be repeated for the other ranks, until the addition is completed. There is a special circuit which is able to perform this operation: It is the full adder. The following figure gives us the principle of the addition involving many full adders: B2 B1 B0

C3

C2 FA2 FA1

C1 FA0

C0

...

S2

A2

S1

A1

S0

A0

Figure 6.1: Principle of addition Each element of the circuit above represents a full adder. Each full adder is intended to add one bit of the number A to the bit of the number B having the same weight. The two numbers to be added should have the same number of bits. So, if the two numbers to be added have five bits each, the addition will be performed using five full adders connected in parallel as shown above. 6.3 The full adder: As presented above, the full adder is combinatory logic circuit intended to add two bits. The principle diagram of a full adder is given by the figure bellow: A

S FA Cout

Cin

Figure 6.2: Principle diagram of a full adder B

Digital Electronics_Jean-Paul NGOUNE

The full adder has three inputs: A: bit from number A; B: Bit from number B; Cin: Carry out coming from the previous rank.

And two outputs: A 0 0 0 0 1 1 1 1 S: the bit of sum; Cout: The carry out (to be added to the bits of the next rank).

Truth table:

B 0 0 1 1 0 0 1 1

Ci 0 1 0 1 0 1 0 1

S 0 1 1 0 1 0 0 1

Co 0 0 0 1 0 1 1 1

Equations of the outputs : We can either use Boolean algebra or k-map to determine the equations of

the outputs. Using Boolean algebra:

S = A.BCi + ABCi + A B.Ci + ABCi

) ( = A(B C ) + A(B C ) Let X = (B C )

in i
i

= A BCi + BCi + A B.Ci + BCi

S = AX + A X = A X = A B Ci
S = A B Ci
Digital Electronics_Jean-Paul NGOUNE

Co = A.BCi + A BCi + ABCi + ABCi

The expression will not change if one of the elements of the sum of products is duplicated (After the Boolean additive identity according to which A + A = A, A being a Boolean variable). So we will duplicate the product ABCi three times in order to simplify the expression easily.
Co = A.BCi + A BCi + ABCi + ABCi + ABCi + ABCi

= BCi A + A + ACi B + B + AB Ci + Ci = BCi + ACi + AB

Co = BCi + ACi + AB S
A BCi

Using k-map: 00 01 1 0 11 0 1 10 1 0

0 1

0 1

S = A.BCi + ABCi + A B.Ci + ABCi

S = A B Ci

Co
A

BCi

00 0 1 0 0

01 0 1

11 1 1

10 0 1

Co = BCi + ACi + AB

Digital Electronics_Jean-Paul NGOUNE


A B

Logic diagram
Ci Ri

Ro Co

6.4 The half adder: The half adder has two inputs A and B which are the two bits to be added, and two outputs which are the sum output S and the carry output Co. The principle diagram of the half adder is given by the following diagram.

A HA B

Co

Figure 6.3: Principle diagram of a half adder

Truth table: A 0 0 1 1 B 0 1 0 1 S 0 1 1 0 Co 0 0 0 1

Equations of the outputs

S = A .B + A.B S = A B Co = A.B

Digital Electronics_Jean-Paul NGOUNE

Exercise 6.1: Consider the following digital system made up of two half adders and an OR gate. Establish the truth table of the system and draw a conclusion. A B DA So
Co

S DA

Ci Co

6.4 The Subtractor: As we have seen in the previous chapter, the subtraction of a number B from a number A can be treated as the addition of the number A with the twos complement of the number B. A B = A + ( B) = A + C2 ( B) = A + ( B + 1) 6.4.1 The half subtractor: The half Subtractor performs the subtraction of a number having one bit from another number having one bit. It has two inputs which are the two numbers A and B to be added, and two outputs Di and Co which are respectively the difference and the carry out. Truth table

A 0 0 1 1 Remark 6.1:

B 0 1 0 1

Di 0 1 1 0

Co 0 1 0 0

0 1 = -1 = 11(Twos complement notation) 1 and carry out of 1

Digital Electronics_Jean-Paul NGOUNE

Equations of the outputs:

Di = A .B + A.B = A B

Co = AB

Logic diagram:

Di

B Ro Co

6.4.2 The full subtractor : The structure above can be modified to achieve subtractions involving numbers having more than one bit. In fact, such operation is performed by a full subtractor. It has then an additional input Ci which is the Carry in (from the previous rank). A 0 0 0 0 1 1 1 1 Truth table: B 0 0 1 1 0 0 1 1 Ci 0 1 0 1 0 1 0 1 Di 0 1 1 0 1 0 0 1 Co 0 1 1 1 0 0 0 1

Remark 6.2: 0 1 1 = 1102 (-210 in twos complement notation) 0 and carry out of 1.

Digital Electronics_Jean-Paul NGOUNE


Di
A BCi

Equations of the outputs:

00 0 1 0 1

01 1 0

11 0 1

10 1 0

Di = A.B.Ci + A.B.Ci + A B.Ci + ABCi

= A B.Ci + B.Ci + A B.Ci + BCi

i

) ( = A(B C ) + A(B C )
= A B Ci

Di = A B Ci

Co
A

BCi

00 0 1 0 0

01 1 0

11 1 1

10 1 0

Co = A.Ci + A.B + BCi

A B

Logic diagram
Ri Ci

Di

Co Ro

Digital Electronics_Jean-Paul NGOUNE

6.5 The comparator A comparator is a combinatory logic circuit which is intended to detect among two binary numbers the one which is the greater (or the smaller). It detects also the equality of the two numbers. The numbers to be compared should have the same number of bits. Let us design a comparator for two numbers having one bit each. Truth table: S2 S3 Equations of the outputs

S1 A 0 0 1 1
A B

B 0 1 0 1

(A>B) (A=B) (A<B) 0 0 1 0 1 0 0 1 0 1 0 0

S1 = A.B S2 = A B S3 = A.B

Logic diagram

S1

S2

S3

Exercise 6.2: Design a logic circuit which is able to compare two numbers having two bits each.

6.6 The decoder: The decoder is a combinatory logic circuit which functions in such a way that for a given input address, only one of its outputs is activated. The principle diagram of the decoder is presented by the following figure:

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I0 . . . IN-1 . . .

O0

Decoder N to M

OM-1 M outputs, only one is activated

N inputs

Figure 6.4: Principle diagram of a decoder. The Input address is a binary code of N bits. For N bits, there are 2N possible input addresses. So, the decoder has M = 2N outputs such that, for each input address, only one output can be activated among the 2N available. Let us design a decoder having three inputs (And therefore 2N = 8 outputs). Such a decoder is also called a 3 to 8 decoder. A 0 0 0 0 1 1 1 1

Truth table:

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

O0 1 0 0 0 0 0 0 0

O1 0 1 0 0 0 0 0 0

O2 0 0 1 0 0 0 0 0

O3 0 0 0 1 0 0 0 0

O4 0 0 0 0 1 0 0 0

O5 0 0 0 0 0 1 0 0

O6 0 0 0 0 0 0 1 0

O7 0 0 0 0 0 0 0 1

Equations of the outputs:

O0 = A.B .C O1 = A.B .C O2 = A.B.C O3 = A.B.C

Digital Electronics_Jean-Paul NGOUNE

O4 = A.B .C O5 = A.B .C O6 = A.B.C O7 = A.B.C

11

Logic diagram:
B C

O0

O1

. . .
O7

Applications of decoders The applications of decoders are found in many digital systems. Here are

some of them.

a) Addressing of a memory: A memory is made up of registers which contain memory words. Addressing a memory consist of allocate to each register a particular code which permits to identify it and also to get access to the data stored within it. Let us consider a memory having 16 registers, each register storing a memory word of 8 bits (1 byte). We want to address that memory so that, for each address code sent to the memory, only one register will be accessible. To solve this problem, we can use a decoder having 4 inputs and 24 = 16 outputs. Each output will be connected to one of the 16 registers such that, for each of the 16 possible input addresses, only one register can be selected. The following figure presents the synoptic diagram of the system.

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Ligne 0

10100110
Address Decoder 4 to 16

Register storing one byte

Ligne 15

. . .

Chip select

Figure 6.5: Addressing of a memory having a capacity of 16 bytes b) DCB seven segments decoder: In many systems, seven segments displays are used to represent numbers from 0 to 9 and sometimes alphabetical characters.

Each segment is made up of one or two LED

Figure 6.6: Seven segment display. The DCB - seven segments decoder accepts at its inputs a DCB code of four bits, and activate its outputs which will permit to enlighten the LEDs representing the corresponding cipher (corresponding to the DCB code). Protective resistor

a b DCD input codes DCB 7 Segments decoder c . . . g

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Let us design a DCB Seven segment segments decoder which will permit us to represent digital numbers from 0 to 9 on a 7 segments display.

D 0 0 0 0 0 0 0 0 1 1

Truth table: C 0 0 0 0 1 1 1 1 0 0
a

B 0 0 1 1 0 0 1 1 0 0

A 0 1 0 1 0 1 0 1 0 1

a 1 0 1 1 0 1 1 1 1 1

b 1 1 1 1 1 0 0 1 1 1

c 1 1 0 1 1 1 1 1 1 1

d 1 0 1 1 0 1 1 0 1 1

e 1 0 1 0 0 0 1 0 1 0

f 1 0 0 0 1 1 1 1 1 1

g 0 0 1 1 1 1 1 0 1 1

f g b

Equations of the outputs :

a = D.C .B. A + D.B.C . A

a = D+C + B + A. D+C + B+ A

)(

Exercise 6.3: Determine the Boolean expressions for the others outputs.

Exercise 6.4: The following system uses a 3 bits segments decoder to represent the letters ABCDEFGH on a seven segments display. Design that decoder after filling its truth table.

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A B C

3 to seven segment decoder

f g

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

a 1

b 1

c 1

d 0

e 1

f 1

g 1

Display A B C D E F G H

a) Fill the truth table; b) Determine the Boolean expressions of the output a,b,c,d,e,f,g; c) Draw the logic diagram of the circuit.

Exercise 6.5: Design a DCB Decimal decoder. It is a decoder whose inputs are the four bits of the DCB code and who has ten outputs.

6.7 The encoder: The encoder is a combinatory logic circuit which outputs an exclusive binary code when each of its inputs is activated. When one of its inputs is activated, a binary

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code corresponding to that input is sent to the output. The encoder does the reverse of the decoder. Encoder circuits are used in the conception of keyboards.

I0

O0

. . . IM-1

Encoder

. . . ON-1

M inputs, only one among them is high

Binary code at the output

Figure 6.7: Principle diagram of an encoder

Let us realise an 8 to 3 encoder. It is a combinatory logic circuit having 8 inputs an 3 outputs which functions in such a way that, when an input is activated, a corresponding binary number coded in three bits is sent to the output. I0 1 0 0 0 0 0 0 0

Truth table: Only one among the eight inputs should be activated at once. I1 0 1 0 0 0 0 0 0 I2 0 0 1 0 0 0 0 0 I3 0 0 0 1 0 0 0 0 I4 0 0 0 0 1 0 0 0 I5 0 0 0 0 0 1 0 0 I6 0 0 0 0 0 0 1 0 I7 0 0 0 0 0 0 0 1 O2 0 0 0 0 1 1 1 1 O1 0 0 1 1 0 0 1 1 O0 0 1 0 1 0 1 0 1

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Equations of the outputs: The equation of each output is simply the Boolean addition of all the inputs for

which that outputs is at the high logic level. Hence, O2 = I 4 + I 5 + I 6 + I 7 O1 = I 2 + I 3 + I 6 + I 7 O0 = I1 + I 3 + I 5 + I 7

Logic diagram:
I0 I1

O0
I2 I3 I4 I5 I6 I7

O1

O2

When no input is activated, the circuit outputs automatically 000. That is why the input I0 is not connected. Exercise 6.6: Design a decimal DCB encoder. It is an encoder having 10 inputs representing the 10 digits of the decimal system of numeration, and 4 outputs intended to produce DCB codes corresponding to each input when it is activated. Remark 6.2: encoder with priority The encoder designed above would produce a wrong result if two inputs were activated at the same time. There are encoders with priority circuits which functions in such a way that, if two or more inputs are activated at once, the binary code sent to the output is that of the input having the highest value. For instance, if the inputs I2, I5 and I6 are activated the same time, the encoder will output the binary code 110 corresponding to the input I6.
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Exercise 6.7: Design a digital system which permits to display the 10 symbols of the decimal system of numeration on a 7 segments display using a 10 buttons keyboard. 6.8 The transcoder: The transcoder is a combinatory logic circuit which converts a given binary code into another binary code. For instance, let us design binary to Gray encoder. It is a circuit which receives at its inputs binary numbers and outputs corresponding Gray codes.

Binary system

Binary to Gray transcoder

Gray Code

Figure 6.8: Principle diagram of a binary to Gray transcoder

Truth table:

Binary code A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 X 0 0 0 0 1 1 1 1

Gray code Y 0 0 1 1 1 1 0 0 Z 0 1 1 0 0 1 1 0

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X
A BC

Equations of the outputs:

00 0 1 0 1

01 0 1

11 0 1

10 0 1 X=A

Y
A

BC

00 0 1 0 1

01 0 1

11 1 0

10 1 0

Y = A.B + A.B Y = A B

Z
A

BC

00 0 1 0 0

01 1 1

11 0 0

10 1 1

Z = B .C + B.C Z = B C

Logic diagram:

X Y

C
6.9 : The multiplexer:

A multiplexer also called data selector is a combinatory logic circuit which permits to direct towards single output information coming from many inputs. According to the address received by the multiplexer, only one among the information available at its inputs is selected and directed toward the output. A multiplexer can be

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considered as a commutator having multiple poles which are switched according to the address sent to the multiplexer. 2n data inputs

n address inputs

MUX

Output Figure 6.9: Principle diagram of a multiplexer

E is the enable input. It enable the multiplexer to function when the right logic
signal level is sent to it (For the principle diagram above, the right signal level is slow). For an address bus having n lines, up to 2n data can be addressed such that for each of these addresses, one among the 2n data is selected and directed towards the output. Let us design an elementary multiplexer. It is a multiplexer having two data inputs I0 and I1 and one address input A. I0 I1

Address A

Mux

Output

The address can be either 0 or 1. When the address is 0, the datum I0 is selected and sent to the output. When the address is 1, I1 is selected and directed towards the output.

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Truth table:

A 0 1

S I0 I1
S = I 0 . 0 + I1.0 S = I0 S = I 0 A + I1 A

When A = 0, we have:

The information I0 is therefore directed to the output. That information can be a logic state or even a set of data coded in many bits. When A = 1, we have:
I1
1 3 2

S = I 0 . 1 + I1.1 S = I1

Logic diagram:

I0

Let us design now a more complex multiplexer; it is a multiplexer having four data inputs. For 4 data, we need 2 address lines to address all the information.

Truth table: A 0 0 1 1 B 0 1 0 1 S I0 I1 I2 I3
S = A.B .I 0 + A.B.I1 + A.B .I 2 + A.B.I3

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I0

Logic diagram:

I1 S I2

I3

Exercise 6.8: Design a multiplexer having 8 data inputs

Application of multiplexer:

The applications of multiplexers are found in many digital systems. These are some of those applications:

Parallel to series conversion: In many digital systems, the treatment of information is done in parallel;

however, when those information are to be transferred on a long distance, this cannot be done in parallel. In fact, parallel transfer of information is not effective because it requires a large number of lines trough which data will flow; on the other hand, its causes a lot of errors in data transfer. The parallel to series conversion permits to make in such a way that the information treated in parallel can be transferred in series trough a single line. A parallel to series converter can be realised using a multiplexer as shown by the following figure:

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I0 I1 I2 I3 I4 I5 I6 I7 Multiplexer with 8 data inputs The modulo 8 counter

generate successively addresses from 000 to 111. Each of those Series output addresses permits to direct

towards the series output one of the 8 bits stored in the register.

Register containing data in parallel

Modulo 8 counter

Figure 6.10: Parallel to series converter

Realisation of logic functions: Logic functions can be realised using multiplexers. Let us consider a logic

function described by the following truth table: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 S 0 1 0 0 0 1 1 0 I0 I1 I2 I3 I4 I5 I6 I7

This function can be realised without using logic gates. We can use a single multiplexer integrated circuit having 8 data inputs. The principle consist in connecting the outputs having low logic level to the earth and those having high logic level to the positive probe of the supply Vcc, as shown by the following figure:

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Vcc

E
A B C

I0 I1 I2 I3 I4 I5 I6 I7 MUX

S Figure 6.11: Realisation of a logic function using a multiplexer.

Exercise 6.9: Consider a combinatory logic circuit described the following truth table:

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

S 1 1 0 1 0 1 0 1

a. Design the circuit and draw its logic diagram using logic gates. b. Realise the same logic function using a multiplexer.

Exercise 6.10: Realise a multiplexer having 4 data inputs using a 2 to 4 decoder and logic gates of your choice.

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6.10 The demultiplexer: The demultiplexer is a combinatory logic circuit which permits to direct towards many outputs information coming from a single input. The demultiplexer has n address inputs and 2n outputs such that, when an address is sent to it, the information is directed towards the corresponding output (the information is sent to only one among the 2n available outputs).

One data input

n address inputs

DEMUX

2n Outputs Figure 6.12: Principle diagram of a multiplexer.

Let us realise a multiplexer having four outputs (and therefore 2 address inputs). A 0 0 1 1 Truth table: B 0 1 0 1 O0 I 0 0 0 O1 0 I 0 0 O2 0 0 I 0 O3 0 0 0 I

O0 = A.B .I O1 = A.B.I O2 = A.B .I O3 = A.B.I

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Logic diagram:
A B

O0

O1

O2

O3

Exercise 6.11: Design a demultiplexer having 8 outputs.

6.11 Conclusion: The present chapter has permitted us to study many of the most common combinatory circuits. The particularity of those type of circuits was that the logic state of their outputs at a given instant depends only on the combination of the logic states of their inputs. The next chapter will deal with sequential logic. The output of a sequential logic circuit depends not only on the combination of its inputs logic states, but also on the memory of the circuit. The chapter will start with the study of multivibrators (latches and flip-flops) which are tools used in the conception of sequential logic circuits.

REVIEW QUESTIONS
1. (From Probatoire F3, 2009 session). Full adder. The figure 6.13 below represents the circuit of a full adder, where A1 and B1 are the variable inputs. R1 is the carry while So and Ro are the sum and the reminder respectively. A1 B1 R1 So Ro

Full adder Figure 6.13: Full adder.

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a. Complete the truth table below.

A1 0 0 0 0 1 1 1 1

B1 0 0 1 1 0 0 1 1

R1 0 1 0 1 0 1 0 1

So

Ro

b. Simplify the expressions of So and Ro using the Boolean algebra method. c. Simplify the expressions of S0 and Ro using k-maps. d. Using the logic gates, draw the logigram of this full adder.

2. (From Probatoire F3, 2011 session). Parity detector We desire to realise a 3-bit parity detector of bits B1, B2 and B3. The operation is as follows: If 0 or 2 bits are at high logic level (logic level 1), the output is at the high logic level (logic level 1). If 1 or 3 bits are at high logic level, the output is at low logic level (level 0).

a. Establish the corresponding truth table. b. Give the Boolean expression of the output S in terms of B1, B2 and B3. c. Write the expression of S using the operator Exclusive-OR. d. Draw the logic diagram of S.

3. (From Probatoire F3, 2007 session). Electronic multiplicator circuit. The figure 6.14 below shows the block diagram of an electronic circuit which accepts two binary numbers of two bits X1X0 and Y1Y0 and gives at the output the binary number Z3Z2Z1Z0 which is equal to the arithmetic product of the two input numbers. For the inputs, X0 and Y0 are the least significant bits (LSB) while fore the outputs, Z3 is the most significant bit (MSB) and Z0 is the least significant bit.

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X1 X0 Multiplicator circuit Y1 Y0

Z3 Z2

Z1 Z0

Figure 6.14: Multiplicator circuit.

a. What do you understand by the statements Least Significant Bit and Most Significant Bit? b. Establish the truth table of the system. c. Write the expression of each of the outputs Z3, Z2, Z1 and Z0 as function of X1, X0, Y1 and Y0. d. Using k-maps, simplify the output equations obtained from above. e. Draw the logic diagram of the electronic multiplicator circuit using the simplified output equations from the k-maps: Using AND gates only Using NAND and NOR gates only.

4. (From Probatoire 2007). Multiplexer circuit. Consider the diagram of the figure 6.14 bellow. It is a multiplexer connected as a function generator.
GND (0) Vcc (1)
A B C D

E0 A1 A2 A3

E1

E2

E3

E4

E5

E6

E7

Figure 6.14: Multiplexer as function generator.

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a. Identify the inputs of this multiplexer and give their roles. b. Give the output equation of the function S. c. Simplify that equation using k-map d. Realise the simplified function using two-inputs NAND gates exclusively.

5. (From GCE A Level, 2000 session). A factory crane operator is to control red and green safety lights by four switches A, B, C and D. Design a simple logic system which will operate under the following conditions: Red light ON for: Switch A ON and switch B OFF or Switch C ON.

Green light ON for: Switches A and B ON and Switches C and D OFF.

NB: In designing you should respect the following steps: a. Establish the truth table. b. Write the equations of the outputs. c. Simplify the equations if possible. d. Draw the logic circuit.

References: 1. Digital systems, principles and applications, Ronald J.Tocci, 3rd edition, Prentice-Hall inc., Englewood Cliffs, New Jersey , USA,1985. 2. Lessons In Electric Circuits Volume IV Digital, Tony R. Kuphaldt, Fourth Edition, 2007, www.allaboutcircuits.com . www.ibiblio.org/obp/electricCircuits. 3. Cours de systmes logiques, Notes de cours, Premire anne du gnie lectrique, ENSET de Douala, J.C Tsokezo, 2004-2005.

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