Overview

Laboratory Introduction

Learning the architecture of the PIC16F877 Learning the instruction set of the PIC16F877 35 instructions same as previous PIC versions (eg 16F74) Evaluation of example code Experimentation with lab software (today) Experimentation with lab hardware (Wednesday)

Details of the Architecture

14 bit instructions 8 bit data values, byte addressed

PIC 16F877

Harvard architecture (separate address/data memory) Storage capacity: 8k x 14 Flash EPROM (program storage) 256x8 EEPROM 368x8 SRAM (data storage) Universal Asynch./Synch. (UART) Receiver/Transmitter

8 channel, 1-bit A/D converter.

January 24, 2002

16F877 Data Path

PIC16F87X
FIGURE 1-2:
Device PIC16F874 PIC16F877

PIC16F874 AND PIC16F877 BLOCK DIAGRAM

Program FLASH 4K 8K Data Memory 192 Bytes 368 Bytes
13 FLASH Program Memory 8 Level Stack (13-bit) Program Counter

Data EEPROM 128 Bytes 256 Bytes

Data Bus 8 PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS PORTB RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTD W reg RD7/PSP7:RD0/PSP0

RAM File Registers

Program Bus

14 Instruction reg Direct Addr 7

RAM Addr (1)

Addr MUX 8 Indirect Addr

FSR reg STATUS reg 8 3 PORTC

Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset In-Circuit Debugger Low-Voltage Programming 8

MUX

ALU

Parallel Slave Port

PORTE RE0/AN5/RD RE1/AN6/WR

MCLR

VDD, VSS

RE2/AN7/CS

Timer0

Timer1

Timer2

10-bit A/D

Data EEPROM

CCP1,2

Synchronous Serial Port

USART

Note 1: Higher order bits are from the STATUS register.

DS30292B-page 6

1999 Microchip Technology Inc.

Page 6 - 16F877 data sheet

16F877 Program Memory Map

Figure 2-1 of 16F877 data sheet.

Location 0 is rst instruction executed (go to Start). Interrupt vector aids with spurious actions. Eight-deep program stack.

Peatman - Chapter 2

16F877 Data Memory and Register Files

PIC16F87X
FIGURE 2-3: PIC16F877/876 REGISTER FILE MAP
File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD (1) PORTE (1) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISA TRISB TRISC TRISD (1) TRISE (1) PCLATH INTCON PIE1 PIE2 PCON 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h General Purpose Register 80 Bytes accesses 70h-7Fh 7Fh Bank 0 Bank 1 Indirect addr.(*) 100h 101h TMR0 102h PCL 103h STATUS 104h FSR 105h 106h PORTB 107h 108h 109h 10Ah PCLATH 10Bh INTCON 10Ch EEDATA EEADR 10Dh 10Eh EEDATH 10Fh EEADRH 110h 111h 112h 113h 114h 115h 116h General 117h Purpose 118h Register 119h 16 Bytes 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISB 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h General Purpose Register 80 Bytes accesses 70h - 7Fh Bank 3

PCLATH INTCON EECON1 EECON2 Reserved(2) Reserved(2)

SSPCON2 PR2 SSPADD SSPSTAT

TXSTA SPBRG

General Purpose Register 16 Bytes

ADRESL ADCON1

General Purpose Register 96 Bytes

EFh F0h FFh

General Purpose Register 80 Bytes accesses 70h-7Fh Bank 2

16Fh 170h 17Fh

1EFh 1F0h 1FFh

Unimplemented data memory locations, read as 0. * Not a physical register. Note 1: These registers are not implemented on 28-pin devices. 2: These registers are reserved, maintain these registers clear.

1999 Microchip Technology Inc.

DS30292B-page 13

16F877 data sheet - page 13

16F877 Status Register

PIC16F87X
2.2.2.1 STATUS REGISTER The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable, therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions not affecting any status bits, see the "Instruction Set Summary." Note 1: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.

REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)

R/W-0 IRP bit7 R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as 0 - n= Value at POR reset

bit 7:

IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh)

bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the twos complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.

bit 3:

bit 2:

bit 1:

bit 0:

DS30292B-page 18

1999 Microchip Technology Inc.

16F877 data sheet - page 18

16F877 Instruction Set

See Table 13-1 of the 16F877 data sheet.

See Figure 13-1 of the 16F877 data sheet.

3 types of instructions: Byte-oriented operations Bit-oriented operations Literal and control operations

16F877 data sheet - page 137

16F877 Instruction Set

PIC16F87X
TABLE 13-2:
Mnemonic, Operands

PIC16CXXX INSTRUCTION SET

Description Cycles 14-Bit Opcode MSb BYTE-ORIENTED FILE REGISTER OPERATIONS Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 1 1 1 (2) 1 (2) 1 1 2 1 2 1 1 2 2 2 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff LSb ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff Status Affected Notes

ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF BCF BSF BTFSC BTFSS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note 1:

f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, b f, b f, b f, b k k k k k k k k k

C,DC,Z Z Z Z Z Z Z Z Z

1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2

C C C,DC,Z Z

1,2 1,2 1,2 1,2 1,2 1,2 1,2 3 3

BIT-ORIENTED FILE REGISTER OPERATIONS 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff C,DC,Z Z TO,PD Z

LITERAL AND CONTROL OPERATIONS 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk

TO,PD C,DC,Z Z

When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is 1 for a pin configured as input and is driven low by an external device, the data will be written back with a 0. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.

Note:

Additional information on the mid-range instruction set is available in the PICmicro Mid-Range MCU Family Reference Manual (DS33023).

DS30292B-page 138

1999 Microchip Technology Inc.

16F877 data sheet - page 138

16F877 Instruction Set

See page 27 of Peatman book.

Peatman - page 27

16F877 Instruction Set

See page 27 of Peatman book.

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Peatman - page 27

16F877 Development Tools

A large amount of supplemental documentation available at www.microchip.com Sizable amount of development can be completed at home. MPASM - Assembler for PIC programs MPSIM - Simulator for PIC programs allows single-stepping. allows simulation of analog inputs. allows full evaluation of state. MPLAB - integrated hardware/software debugger front-end interface for MPASM and MPSIM congures MPLAD-ICD (hardware) allows for in-circuit testing.

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Reading and Exercises

16F877 data sheet - pages 1-18, 26, 137-144 Peatman book - Chapter 2. Exercises: MPASM - learn to assemble and simulate a demo program (today) MPLAB-ICD - learn to download, single-step, and debug a program.

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