List of M.Sc. by Research /Ph.D.

Course work that can be offered under Electrical Science

GROUP-I

05 EC 027

DESIGN OF VLSI SYSTEMS

VLSI System Design methodology: Structure Design, Strategy, Hierarchy, Regularity, Modularity, and Locality. System on Chip Design options: Programmable logic and structures, Programmable interconnect, programmable gate arrays, Sea of gate and gate array design, standard cell design, full custom mask design. Chip Design Methods: Behavioral synthesis, RTL synthesis, Logic optimization and structural tools layout synthesis, layout synthesis, EDA Tools for System Design capture tools: HDL Design, Schematic Design, Layout Design, Floor planning and Chip Composition. Design Verification Tools: Simulation Timing Verifiers, Net List Comparison Layout Extraction, Design Rule Verification. Data Path Sub System Design: Introduction, Addition, Subtraction, Comparators, Counters, Boolean logical operations, coding, shifters, Multiplication, Parallel Prefix computations Array Subsystem Design: SRAM, Special purpose RAMs, DRAM, Read only memory, Content Addressable memory, Programmable logic arrays. Control Unit Design: Finite State Machine (FSM) Design, Control Logic Implementation: PLA control implementation, ROM control implementation. Special purpose Subsystems: Packaging, power distribution, I/O, Clock, Transconductance amplifier, follower integrated circuits, etc Design Economics: Nonrecurring and recurring engineering Costs, Fixed Costs, Schedule, Person power, example VLSI System Testing & Verification: Introduction, A walk through the Test Process, Reliability, Logic Verification Principles, Silicon Debug Principles, Manufacturing Test Principles, Design for Testability, Boundary Scan VLSI Applications Case Study: RISC microcontroller, ATM Switch, etc.

List of M.Sc. by Research /Ph.D. Course work that can be offered under Electrical Science

GROUP-I

TEXT BOOKS:
1.

Neil H.E. Weste, Davir Harris, CMOS VLSI Design: A Circuits and system

perspectives Addison Wesley - Pearson Education, 3rd Edition, 2004. 2. Wayne, Wolf, Modern VLSI design: System on Silicon Prentice Hall PTR/Pearson Education, Second Edition, 1998
3.

Douglas A Pucknell & Kamran Eshragian , Basic VLSI Design PHI 3 rd Edition

(original Edition 1994)

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GROUP 2

05 EC 078

TESTING AND VERIFICATION OF VLSI CIRCUITS

Scope of testing and verification in VLSI design process; Issues in test and verification of complex chips; embedded cores and SOCs Fundamentals of VLSI testing, Fault models. Automatic test pattern generation, Design for testability, Scan design, Test interface and boundary scan, System testing and test for SOCs, Iddq testing, Delay fault testing, BIST for testing of logic and memories, Test automation. Design verification techniques based on simulation, analytical and formal approaches, Functional verification, Timing verification, Formal verification, Basics of equivalence checking and model checking, Hardware emulation. TEXT BOOKS: 1. M. Abramovici, M. A. Breuer and A. D. Friedman, "Digital Systems Testing and Testable Design", IEEE Press, 1990.( Available as JAICO Publication) 2. M. Bushnell and V. D. Agarwal, "Essentials of Electronic Testing for Digital, Memory and MixedSignal VLSI Circuits", Kluwer Academic Publishers, 2000 3. T.Kropf, "Introduction to Formal Hardware Verification", Springer Verlag, 2000. REFERENCE BOOKS: 1. P. Rashinkar, Paterson and L. Singh, "System-on-a-Chip Verification-Methodology and Techniques", Kluwer Academic Publishers, 2001. 2. 3. 4. 5. 6. M. Abramovici, M. A. Breuer, A. D. Friedman, Digital Systems Testing and Testable Design J.DiGiacomo, editor, VLSI Handbook, McGraw-Hill, 1989. Samiha Mourad and Yervant Zorian, Principles of Testing Electronic Systems, Wiley (2000). D. K. Pradhan (Editor). Fault-Tolerant Computing: Theory and Techniques, Prentice Hall, NJ, 1986. A. Miczo. Digital Logic Testing and Simulation , John Wiley & Sons, 1987 2 Piscataway, New Jersey: IEEE Press, 1994,

List of M.Sc. by Research /Ph.D. Course work that can be offered under Electrical Science GROUP-I 7. Barry Johnson. Design and Analysis of Fault-Tolerant Digital Systems, Addison Wesley, 1989.

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GROUP-3
05 EC 041 HARDWARE - SOFTWARE CO-DESIGN

Introduction: Motivation hardware & software co-design, system design consideration, research scope & overviews Hardware Software back ground: Embedded systems, models of design representation, the virtual machine hierarchy, the performance3 modeling, Hardware Software development, Hardware Software co-design research: An informal view of co-design, Hardware Software tradeoffs, crosses fertilization, typical co-design process, co-design environments, limitation of existing approaches, ADEPT modeling environment. Co-design concepts: Functions, functional decomposition, virtual machines, Hardware Software partitioning, Hardware Software partitions, Hardware Software alterations, Hardware Software trade offs, co-design. Methodology for co-design: Amount of unification, general consideration & basic philosophies, a framework for co-design Unified representation for Hardware & Software: Benefits of unified representation, modeling concepts An abstract Hardware & Software model: Requirement & applications of the models, models of Hardware Software system, an abstract Hardware Software models, generality of the model Performance evaluation: Application of t he abstract Hardware & Software model, examples of performance evaluation Object oriented techniques in hardware design: Motivation for object oriented technique, data types, modeling hardware components as classes, designing specialized components, data decomposition, Processor example. TEXT BOOKS: 1. Sanjaya Kumar, James H. Ayler The Co-design of Embedded Systems: A Unified Hardware Software Representation, Kluwer Academic Publisher, 2002 2. Gomaa, Software Design Methods for Concurrent and Real-time Systems, Addison-Wesley, 1993. 3. H. Kopetz, Real-time Systems, Kluwer, 1997. 4. R. Gupta, Co-synthesis of Hardware and Software for Embedded Systems, Kluwer 1995. REFERENCE BOOKS: 1. S. Allworth, Introduction to Real-time Software Design, Springer-Verlag, 1984.

List of M.Sc. by Research /Ph.D. Course work that can be offered under Electrical Science 2. C. M. Krishna, K. Shin, Real-time Systems, Mc-Graw Hill, 1997. 3. Publishers, 1995. 4. Additional reading from selected journal papers.

GROUP-I

Peter Marwedel, G. Goosens, Code Generation for Embedded Processors, Kluwer Academic

05 EC 093

HIGH SPEED VLSI DESIGN

Clocked Logic Styles, Single-Rail Domino Logic Styles, Dual-Rail Domino Structures, Latched Domino Structures, Clocked Pass Gate Logic Non-Clocked Logic Styles, Static CMOS, DCVS Logic, Non-Clocked Pass Gate Families. Circuit Design Margining, Design Induced Variations, Process Induced Variations, Application Induced Variations, Noise. Latching Strategies, Basic Latch Design, and Latching single-ended logic, Latching Differential Logic Race Free Latches for Pre-charged Logic Asynchronous Latch Techniques. Signaling Standards, Chip-to-Chip Communication Networks, ESD Protection Clocking Styles, Clock Jitter, Clock Skew, Clock Generation, Clock Distribution, Asynchronous Clocking Techniques Skew Tolerant Design TEXT BOOKS: 1. Kerry Bernstein & et. al., High Speed CMOS Design Styles, Kluwer, 1999. 2. Evan Sutherland, Bob stroll, David Harris, Logical Efforts, Designing Fast CMOS Circuits, Kluwer, 1999. 3. David Harris, Skew Tolerant Domino Design.

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05 EC0 83 VLSI TECHNOLOGY

Environment for VLSI Technology: Clean room and safety requirements. Wafer cleaning processes and wet chemical etching techniques. Impurity incorporation: Solid State diffusion modeling and technology; Ion Implantation modeling, technology and damage annealing; characterization of Impurity profiles. Oxidation: Kinetics of Silicon dioxide growth both for thick, thin and ultra thin films. Oxidation technologies in VLSI and ULSI; Characterization of oxide films; High k and low k dielectrics for ULSI. Lithography: Photolithography, E-beam lithography and newer lithography techniques for VLSI/ULSI; Mask generation.

List of M.Sc. by Research /Ph.D. Course work that can be offered under Electrical Science

GROUP-I

Chemical Vapour Deposition techniques: CVD techniques for deposition of polysilicon, silicon dioxide, silicon nitride and metal films; Epitaxial growth of silicon; modeling and technology. Metal film deposition: Evaporation and sputtering techniques. Failure mechanisms in metal interconnects; Multi-level metallization schemes. Plasma and Rapid Thermal Processing: PECVD, Plasma etching and RIE techniques; RTP techniques for annealing, growth and deposition of various films for use in ULSI. Process integration for NMOS, CMOS and Bipolar circuits; Advanced MOS technologies TEXT BOOKS: 1. C.Y. Chang and S.M.Sze (Ed), ULSI Technology, McGraw Hill Companies Inc, 1996. 2. S.K. Gandhi, VLSI Fabrication Principles, John Wiley Inc., New York, 1983. 3. S.M. Sze (Ed), VLSI Technology, 2nd Edition, McGraw Hill, 1988. REFERENCE BOOKS: 1. Stephena, Campbell, the Science and Engineering of Microelectronic Fabrication, Second Edition, Oxford University Press, 2005 2. Yuan Taur, Tak. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 2003.

05 EC047

LOW POWER VLSI DESIGN

Need for low power VLSI chips, Sources of power dissipation on Digital Integrated circuits. Emerging Low power approaches, Physics of power dissipation in CMOS devices. Device & Technology Impact on Low Power: Dynamic dissipation in CMOS, Transistor sizing & gate oxide thickness, Impact of technology Scaling, Technology & Device innovation Power estimation, Simulation Power analysis: SPICE circuit simulators, gate level logic simulation, capacitive power estimation, static state power, gate level capacitance estimation, architecture level analysis, data correlation analysis in DSP systems, Monte Carlo simulation. Probabilistic power analysis: Random logic signals, probability & frequency, probabilistic power analysis techniques, signal entropy. Low Power Design Circuit level: Power consumption in circuits. Flip Flops & Latches design, high capacitance nodes, low power digital cells library Logic level: Gate reorganization, signal gating, logic encoding, state machine encoding, precomputation logic

List of M.Sc. by Research /Ph.D. Course work that can be offered under Electrical Science

GROUP-I

Low power Architecture & Systems: Power & performance management, switching activity reduction, parallel architecture with voltage reduction, flow graph transformation, low power arithmetic components, low power memory design. Low power Clock Distribution: Power dissipation in clock distribution, single driver Vs distributed buffers, Zero skew Vs tolerable skew, chip & package co design of clock network Algorithm & architectural level methodologies: Introduction, design flow, Algorithmic level analysis & optimization, Architectural level estimation & synthesis. TEXT BOOKS: 1. 2. Gary K. Yeap, Practical Low Power Digital VLSI Design, KAP, 2002 Rabaey, Pedram, Low power design methodologies Kluwer Academic, 1997 Kaushik Roy, Sharat Prasad, Low-Power CMOS VLSI Circuit Design Wiley, 2000

05 EC077

SYNTHESIS AND OPTIMIZATION OF DIGITAL CIRCUITS

Introduction: Microelectronics, semiconductor technologies and circuit taxonomy, Microelectronic design styles, computer aided synthesis and optimization. Graphs: Notation, undirected graphs, directed graphs, combinatorial optimization, Algorithms, tractable and intractable problems, algorithms for linear and integer programs, graph optimization problems and algorithms, Boolean algebra and Applications. Hardware Modeling: Hardware Modeling Languages, distinctive features, structural hardware language, Behavioral hardware language, HDLs used in synthesis, abstract models, structures logic networks, state diagrams, data flow and sequencing graphs, compilation and optimization techniques. Two level combinational logic optimization: Logic optimization, principles, operation on two level logic covers, algorithms for logic minimization, symbolic minimization and encoding property, minimization of Boolean relations. Multiple level combinational optimizations: Models and transformations for combinational networks, algebraic model, Synthesis of testable network, algorithm for delay evaluation and optimization, rule based system for logic optimization. Sequential circuit optimization: Sequential circuit optimization using state based models, sequential circuit optimization using network models. Schedule Algorithms: A model for scheduling problems, Scheduling with resource and without resource constraints, Scheduling algorithms for extended sequencing models, Scheduling Pipe lined circuits.

List of M.Sc. by Research /Ph.D. Course work that can be offered under Electrical Science

GROUP-I

Cell library binding: Problem formulation and analysis, algorithms for library binding, specific problems and algorithms for library binding (lookup table F.P.G.As and Antifuse based F.P.G.As), rule based library binding. Testing: Simulation, Types of simulators, basic components of a simulator, fault simulation Techniques, Automatic test pattern generation methods (ATPG), design for Testability (DFT) Techniques. TEXT BOOKS: 1. Giovanni De Micheli, Synthesis and Optimization of Digital Circuits," Tata McGraw-Hill, 2003. 2. Srinivas Devadas, Abhijit Ghosh, and Kurt Keutzer, Logic Synthesis, McGraw-Hill, USA, 1994.
3.

Neil Weste and K. Eshragian,Principles of CMOS VLSI Design: A System Perspective,2 nd

edition, Pearson Education, 2000. 4. Kevin Skahill, VHDL for Programmable Logic, Pearson Education, 2000.
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