Summer 2011 CME 2006 - CPU Design Project

A CPU which is similar to Manos Basic Computer is to be designed, verified using Max Plus II or Quartus II software from Altera (Bonus (+10): implementation on the DE0 FPGA board). The project is given as four assignments. It is advised that you read problem definitions of all of them before actually starting with assignment-1, i.e., Common Bus and Registers. Please submit zipped All Files (dont forget to submit wave format of the results) of the simulations for all assignments. ASSIGNMENT I

Common Bus System (Reference to Figure 5-4)

Memory 32x8
Code Segment (16x8) Address Range: : 0-15 Data Segment (8x8) Address Range: 16-23 Stack Segment (8x8) Address Range 24-31

s2 s0 s1

Bus

m 1m 0

ReadWrite PC (4-bits)

LD

INR

CLR

SP(3-bits) LD LD INR DCR AR(3-bits) INR CLR CLR

1 4 3 5 6
Clock

DR (4-bits) LD INR IR (8-bits) LD AC (4-bits) LD INR CLR CLR

4-bit common bus

Figure-1 Basic Computer Common-Bus System

Data[4 bits]
LD INR CLR DCR ReadWrite [m1m0 ] CLK
[r2 r1r0] [r2 r1r0] ] 2 r1r0] [r

Data[4 bits]

Common_Bus_System

S0

S1 S2

Figure-2 Block-Diagram of Common-Bus System, where r2r1r0 refers to register selection index, m1m0 refers to segment selection index

You are expected to implement the common bus architecture designed in Figure 1 in Altera and save it as a block diagram (symbol file) with the name, Common_Bus_System as shown in Figure 2. Finally test and simulate your implementation by loading (transferring) data from Program memory and Data memory to registers and applying INR and CLR operations on them. Details are listed below;

There is one memory unit consisting of Code Segment, Data Segment and Stack Segment. Unit selections are as follows

S2S1S0 000

m1m0 00 01 10

Register / Memory Segment

001 010 011 100 101 110

Code segment Data segment Stack segment SP PC DR AR IR AC

Each bus control inputs of the bus block diagram (figure-2) indicated by r2r1r0 are encoded same as unit selections. That is, LD [r2r1r0 = 1] indicates SP s LD input LD [r2r1r0 = 2] indicates PC s LD input

.
CLR [r2r1r0 = 1] indicates SP s CLR input CLR [r2r1r0 = 2] indicates PC s CLR input

.
INR [r2r1r0 = 1] indicates SP s INR input INR [r2r1r0 = 2] indicates PC s INR input

.
DCR applies only to SP. ReadWrite and m1m0 applies only to memory unit
Registers have 5 inputs which are data inputs, load input, clear input, clock input and increment input (additionally decrement in SP) Register sizes are given on the figure. IR has 8 data bits. So system bus must have 4 data bits. Memory is 32x8 bits consisting of Code Segment 16x8 bits with the address range [0-15], Data segment 8x8 bits with the address range [16-23] and Stack Segment 8x8 bits with the address range [24-31].. Memory unit must be initialized with pre loaded test image (memory.mif). The image file is also included in memory.zip file. When you open the gdf file, you have to configure memory component to load initial values from image file. This can be done by Edit Ports/Parameters command from Utilities menu or right click menu. You have to configure LPM_FILE parameter to point the initialization image file. ! Your project will be tested using this image file, so do not change it !