HOMEWORK 5 Solution

ICS 151 Digital Logic Design

Spring 2004 1. Sequential Circuit Analysis [T Flip-Flop] [25 points]

Derive the state table and state diagram of the sequential circuit shown in figure below. Explain the function that the circuit performs.

We start by writing the logic equation for TA and TB: TA = A + B TB = A + B Based on these formulas we can reach to transition table:

Present State A B 0 0 0 1 1 0 1 1

Flip-Flop inputs TA TB 0 1 1 1 1 0 1 1

Next State A(next) B(next) 0 1 1 0 0 0 0 0

In above table, whenever the TA (TB) is 1 then next state is toggled and when it is 0 it is hold. We can reach to this table using the characteristic equation for T flip-flop also, we know that Q(next)= TQ+TQ so: The corresponding next-state equations are: A(next) = TAA + TAA = (A + B)A + (A + B)A

= ABA + AA + AB = 0 + 0 + AB = AB B(next) = = = = = The next-state table is: TBB + TBB (A + B)B + (A + B)B ABB + AB + BB 0 + AB + 0 AB

PRESENT STATE AB 0 0 0 1 1 0 1 1

NEXT STATE A(next) B(next) 0 1 1 0 0 0 0 0

Based on present state and next state we can reach to state diagram:

This is a modulo-3 counter.

2. Sequential Circuit Analysis [JK Flip-Flop]

[25 points]

Derive the state table and state diagram of the sequential circuit shown in figure below.

The excitation equations are: J1 = K1 = J2 = K2 = xY2 x x x + Y1

And output is : Z = xY1Y2

Present state Y1 0 0 0 0 1 1 1 1 Y2 0 0 1 1 0 0 1 1

Input x 0 1 0 1 0 1 0 1

Flip-Flop 1 inputs J1 K1 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 0

Flip-Flop 2 inputs J2 K2 0 1 1 1 0 1 1 1 0 1 1 0 0 1 1 0

Next State Y1(next) Y2(next) 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 1

Output Z 0 0 0 0 0 0 0 1

We can use characteristic equation also to reach to this table: y1(next) = J1y1 + K1y1 = xy2y1 + (x)y1 = xy2y1 + xy1 y2(next) = J2y2 + K2y2 = xy2 + (x + y1)y2 = xy2 + xy1y2 PRESENT STATE y1 y2 0 0 1 1 0 1 0 1 NEXT STATE / OUTPUT y1(next) y2(next) / z x = 0 x = 1 0 0 / 0 0 1 / 0 0 0 / 0 1 0 / 0 0 0 / 0 1 1 / 0 0 0 / 0 1 1 / 1

The state diagram is:

3. State table reduction [25 points] Reduce the number of states in the following state table and tabulate the reduced state table: Next State Present state A B C D E F G H X=0 F D F G D F G G X=1 B C E A C B H A X=0 0 0 0 1 0 1 0 1 Output X=1 0 0 0 0 0 1 1 0

Two states are equivalent if they have the same output for all inputs, and if they transition to equivalent states on all inputs. To minimize an FSM, we group its states into equivalence classes, where all states in an equivalence class are equivalent to one another. The first step in determining which states are equivalent is to group them based on their outputs, such that no two states are in the same group unless their outputs are the same for all inputs. To make this step simple, we will first extract the output values from the state table.

X = 0 X = 1

A 0 0

B 0 0

C 0 0

D 1 0

E 0 0

F 1 1

G 0 1

H 1 0

Output values

There are four different sets of output that occur: 00, 01, 10, and 11. So, we will group the states with like output together, then determine whether all of the states in each group transition to equivalent states for all inputs.

X = 0 X = 1

G0 = { A, B, C, E } G3G2G3G2 G0G0G0G0

G1 = { G } G1 G2

G2 = { D, H } G1G1 G0G0

G3 = { F } G3 G0

Next states

From the table above, we see that the states in G2 (D and H) are equivalent, since they transition to equivalent states for all inputs. G1 and G3 are obviously equivalence classes, since they contain only one state each. G0, however, is not an equivalence class, since states A and C transition to G3 on an input of 0, while states

B and E transition to G2 on the same input. So, we must split G0 into two separate groups and repeat the process of determining whether the groups are all equivalence classes.

X = 0 X = 1

G0 = { A, C } G4G4 G1G1

G1 = { B, E } G3G3 G0G0

G2 = { G } G2 G3

G3 = { D, H } G2G2 G0G0

G4 = { F } G4 G1

Next states

Now all five groups contain equivalent states, so they are all equivalence classes. Therefore, we can build a new FSM in which each state represents one of the equivalence classes from the original FSM. We will name the states in this new FSM s0, s1, s2, s3, and s4, corresponding to the equivalence classes G0, G1, G2, G3, and G4, respectively.

The next-state/output table for the minimized FSM is: NEXT STATE X=0 X=1 s4 s1 s3 s0 s2 s3 s2 s0 s4 s1 OUTPUT X=0 X=1 0 0 0 0 0 1 1 0 1 1

PRESENT STATE s0 s1 s2 s3 s4

Alternatively, the state reduction can be performed using an implication table as follows. We will begin by building a table containing one entry for each pair of states in the original FSM. We will then put an into every cell that corresponds to a pair of states that do not have like output for all inputs.

B C D E F G H A B C D E F G

For each of the above pairs of states that is not marked with an , we determine which pairs of states must be equivalent in order for the unmarked pair to be equivalent. We indicate these pairs in angle brackets in the unmarked cells.

B C D E F G H

<D, F> <B, C> <B, E> <D, F> <C, E>

<D, F> <B, C>

<D, F>

For each cell c with pairs of states listed in angle brackets, we will check the corresponding cell in the implication table to see if it is marked with an . If it is, the two states are already known not to be equivalent, so we will mark c with an . Following this process for every cell in the table, our implication table will now look like this:

B C D E F G H

<D, F> <B, C> <B, E> <D, F> <C, E>

<D, F> <B, C>

<D, F>

Since at least one cell has been marked with an during this process, we will perform the process again, continuing to perform it until no new cells are marked with an . The second time through the process, no new cells are marked with an , so the above implication table is the final implication table for the original FSM. Now we know that states A and C are equivalent, B and E are equivalent, and D and H are equivalent. Here are equivalence classes: G0 = { A, C } G1 = { B, E } G2 = { G } G3 = { D, H } G4 = { F } Given that these equivalence classes are the same as the ones we obtained during the previous solution to the problem, the next state and output table is the same also. Both methods of state minimization arrived at the same answer.

The next-state/output table for the minimized FSM is: NEXT STATE X=0 X=1 s4 s1 s3 s0 s2 s3 s2 s0 s4 s1 OUTPUT X=0 X=1 0 0 0 0 0 1 1 0 1 1

PRESENT STATE s0 s1 s2 s3 s4

4. Sequential Circuit Design [25 points] Derive the state diagram for a serial 2s complementer. The circuit has one input and one output and accepts a string of bits from input and generates the 2s complement at the output.

We know that we can reach to 2s complement of a binary number by investigating the bits from LSB one bit by one bit and skip the 0s and first 1 and then start inverting the bits, for example the 2s complement of 1010 1000, will be: 0101 1000 So we can reach to the state diagram of the 2s complementer circuit based on this simple observation. x is input and z is output. Imagine that in a way (by using Asynchronous Clear) we will start in state 0:

This is a Moore machine, because the output depends only on present state. If we want to design a Mealy machine it will be like this: