PGP COLLEGE OF ENGINEERING AND TECHNOLOGY DEPARTMENT OF ELECTRONICS AND INSTRUMENTATION ENGINEERING

ACADEMIC YEAR:2011-2012 VLSI DESIGN QUESTION BANK UNIT-1

2MARKS: 1. Define threshold voltage. 2. Give the different modes of operations of MOS transistor. 3. What are the different regions of operations of MOS transistor? 4. Give the expression for drain current for different modes of operation of MOS transistor? 5. Plot the current voltage characteristics of a N-MOS transistor. 6. What are the different fabrication processes available to CMOS technology? 7. What is body effect ? 8. Draw the circuit of a N-MOS inverter. 9. Give the expression for pull-up to pull-down ratio (Z pu/Z pd) for an N-MOS inverter driven by another N-MOS inverter. 10. Draw the circuit of a CMOS inverter. 11. Define rise time . 12. Define fall time 13. Define delay time. 14. What are the various silicon wafer preparation? 15. Give the fabrication steps for IC fabrication 16. Different types of oxidation . 17. What is enhancement mode transistor? 18. What is depletion mode device ? 19. When the channel is said to be pinched off? 20. What are the transistor CMOS technology provides? 21. What is the special feature of Twin-Tub process? 16 Marks 1. Draw and explain the nMos process. 2. Explain the twintub process with neat diagram. 3. Draw and explain briefly the n-well CMOS processes. 4. Derive the expression for the drain to source current in the non saturated region of operation of nMOS transistor. 5. Explain the CMOS inverter dc characteristics. 6. Explain the modes of operations of MOS transistor. 7. Explain the silicon on insulator process. 8. Derive the pull up and pull down ratio of an inverter driven by another inverter.

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PGP COLLEGE OF ENGINEERING AND TECHNOLOGY DEPARTMENT OF ELECTRONICS AND INSTRUMENTATION ENGINEERING
ACADEMIC YEAR:2011-2012 VLSI DESIGN QUESTION BANK UNIT-2 2MARKS : 1. List out the MOS layers. 2. What is stick diagram? 3. Why design rules in CMOS design? 4. Explain the design rules of layout diagram. 5. Write about the lambda besed design rule. 6. Draw the encodings of a simple single metal nMOS process. 7. Illustrate with example of CMOS stick layout design style. 8. Define Pass transistor 9. Draw and define Transmission gate. 10. Define Multiplexer 11. Draw 2:1 Mux using transmission gate. 12. Define gate logic. 13. Difference between combinational and sequential logic circuits. 14. Define fan-in and fan-out in CMOS logic design. 15. Define switch logic 16. Which MOS can pass logic 1 and logic 0 strongly? 17. What is super buffer? 18. Draw the circuit diagram for the following Boolean expression using MOS transistor a. y = (a +b) 20. Draw the stick layout for CMOS NAND gate 16 MARKS: 1.
2. Briefly explain the following terms
(i) Design of switches with MOSFETs,

BATCH:IV/VII SEM

(ii) Transmission gate, (iii) Muxs using TG.

3. Design a full adder by cascading two half adders

4.

PGP COLLEGE OF ENGINEERING AND TECHNOLOGY DEPARTMENT OF ELECTRONICS AND INSTRUMENTATION ENGINEERING
ACADEMIC YEAR:2011-2012 VLSI DESIGN QUESTION BANK UNIT-3 2MARKS : 1. Define FSM.
2. What do you mean by Data flow model? 3. Define Mealy network. 4. What are the methods for programming the PALs? 5. What are all the types of programming PALs? 6. Draw the basic PLA. 7. Differentiate the PLA from the PAL. 8.

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Part-b 1. With neat diagram explain finite state machine PLA.