Dynamic Combinational Circuits

Dynamic circuits
Charge sharing, charge redistribution

Domino logic np-CMOS (zipper CMOS)

Krish Chakrabarty

Dynamic Logic
Dynamic gates uses a clocked pMOS pullup Two modes: precharge and evaluate
A 2 1 Static
Y
Krish Chakrabarty

Y A

2/3 4/3

1 1

Pseudo-nMOS
Precharge

Dynamic
Evaluate Precharge

The Foot
What if pulldown network is ON during precharge? Use series evaluation transistor to prevent fight.
A foot
footed unfooted

precharge transistor Y

inputs f

inputs f

Krish Chakrabarty

Dynamic Logic
VDD Mp In1 In2 In3 VDD Me Out CL PDN

In1 In2 In3

PUN Out Mp p network CL

Me n network

2 phase operation:

Precharge Evaluation
Krish Chakrabarty

Logical Effort
Inverter NAND2
1 2 2 gd pd = 2/3 = 3/3 A

NOR2

unfooted

1 1

Y gd pd = 1/3 = 2/3

A B

1 Y B 1 gd pd = 1/3 = 3/3

1 2 2

1 3 3 3

Y A

footed

Y gd pd = 2/3 = 3/3

A B

gd pd = 3/3 = 4/3 2

1 Y B 2 2 gd pd = 2/3 = 5/3

Krish Chakrabarty

Dynamic Logic
N+2 transistors for N-input function
Better than 2N transistors for complementary static CMOS Comparable to N+1 for ratio-ed logic

No static power dissipation

Better than ratio-ed logic

Careful design, clock signal needed

Krish Chakrabarty

Dynamic Logic: Principles

VDD Mp

Precharge
Out CL

= 0, Out is precharged to VDD by Mp. Me is turned off, no dc current flows (regardless of input values)

In1 In2 In3

PDN

Evaluation
= 1, Me is turned on, Mp is turned off. Output is pulled down to zero depending on the values on the inputs. If not, precharged value remains on CL.

Me

Important: Once Out is discharged, it cannot be charged again! Gate input can make only one transition during evaluation Minimum clock frequency must be maintained Can Me be eliminated?
Krish Chakrabarty 7

Example
VDD

Mp Out Ratio le s s No Static Po we r Cons umptio n

A C B

Nois e Marg ins s mall (NML) Requires Cloc k

Me

Krish Chakrabarty

Dynamic 4 Input NAND Gate

VDD Out
In1 In2 In3 In4

GND

Krish Chakrabarty

Cascading Dynamic Gates

VDD Mp Out1 VDD V

In Out1

Mp Out2

In Out2

VTn

Me

Me

Internal nodes can only make 0-1 transitions during evaluation period
Krish Chakrabarty 10

Monotonicity
Dynamic gates require monotonically rising inputs during evaluation
0 -> 0 0 -> 1 1 -> 1 But not 1 -> 0
A

violates monotonicity during evaluation A Y Output should rise but does not Precharge Evaluate Precharge

Krish Chakrabarty

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Monotonicity Woes
But dynamic gates produce monotonically falling outputs during evaluation Illegal for one dynamic gate to drive another!
A=1 A X X X monotonically falls during evaluation Y Y should rise but cannot Precharge Evaluate Precharge

Krish Chakrabarty

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Reliability Problems Charge Leakage

VDD

Mp Out (1) CL

A (2)

t Vout precharge evaluate

A=0
Me (b) Effect on waveforms t

(a) Leakage sources

(1) Leakage through reverse-biased diode of the diffusion area (2) Subthreshold current from drain to source
Minimum Clock Frequenc y: > 1 MHz
Krish Chakrabarty 13

Leakage
Dynamic node floats high during evaluation
Transistors are leaky (IOFF 0) Dynamic value will leak away over time Formerly miliseconds, now nanoseconds!

Use keeper to hold dynamic node

Must be weak enough not to fight evaluation
weak keeper A 1 k 2 2 X H Y

Krish Chakrabarty

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Charge Sharing (redistribution)

VDD Mp Out CL X B=0 Mb Ca Cb CLVDD = CL Vout(t) + CaVX VX = VDD - Vt, therefore Vout(t) = Vout(t) - VDD = Ca (VDD-Vt) CL

Assume: during precharge, A and B are 0, Ca is discharged During evaluation, B remains 0 and A rises to 1 Charge stored on CL is now redistributed over CL and Ca

Ma

Me

Desirable to keep the voltage drop below threshold of pMOS transistor (why?) Ca/CL < 0.2

Krish Chakrabarty

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Charge Sharing
Dynamic gates suffer from charge sharing

A B=0 x Cx Y CY
A Y Charge sharing noise x

Vx = VY =

CY VDD C x + CY
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Krish Chakrabarty

Charge Redistribution - Solutions

VDD Mp Mbl Out A B Ma Mb Me A B Ma Mb Me VDD Mp Out Mbl

(a) Static bleeder

(b) Precharge of internal nodes

Krish Chakrabarty 17

Secondary Precharge
Solution: add secondary precharge transistors
Typically need to precharge every other node

Big load capacitance CY helps as well

Y A B x secondary precharge transistor

Krish Chakrabarty

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Domino Logic
VDD Mp Out1 VDD VDD Mp Mr Out2 In1 In2 In3 PDN In4 PDN Static Inverter with Level Restorer

Me

Static inverters between dynamic stages

Me

Krish Chakrabarty

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Domino Gates
Follow dynamic stage with inverting static gate
Dynamic / static pair is called domino gate Produces monotonic outputs
Precharge Evaluate Precharge

domino AND

W A B

X C

X Y Z

dynamic static NAND inverter

A B

W H C X

Y H Z = A B

X C

Krish Chakrabarty

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Domino Logic - Characteristics

Only non-inverting logic Very fast - Only 1->0 transitions at input of inverter Precharging makes pull-up very fast Adding level restorer reduces leakage and charge redistribution problems Optimize inverter for fan-out

Krish Chakrabarty

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Domino Optimizations
Each domino gate triggers next one, like a string of dominos toppling over Gates evaluate sequentially but precharge in parallel Thus evaluation is more critical than precharge HI-skewed static stages can perform logic
S0 D0 S1 D1 S2 D2 S3 D3 H S4 D4 S5 D5 S6 D6 S7 D7 Y

Krish Chakrabarty

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Dual-Rail Domino
Domino only performs noninverting functions:
AND, OR but not NAND, NOR, or XOR

Dual-rail domino solves this problem

Takes true and complementary inputs Produces true and complementary outputs
sig_h 0 0 1 1 sig_l 0 1 0 1 Meaning Precharged 0 1 invalid
Krish Chakrabarty 23
Y_l inputs f f Y_h

Example: AND/NAND
Given A_h, A_l, B_h, B_l Compute Y_h = A * B, Y_l = ~(A * B) Pulldown networks are conduction complements
Y_l = A*B A_l B_l Y_h = A*B

A_h B_h

Krish Chakrabarty

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Example: XOR/XNOR
Sometimes possible to share transistors
Y_l = A xnor B A_h A_l B_l Y_h A_l B_h A_h = A xor B

Krish Chakrabarty

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Domino Summary
Domino logic is attractive for high-speed circuits
1.5 2x faster than static CMOS But many challenges: Monotonicity Leakage Charge sharing Noise

Widely used in high-performance microprocessors

Krish Chakrabarty 26

np-CMOS (Zipper CMOS)

VDD Mp Out1 VDD Me

In1 In2 In3

PDN

In4

PUN Out2

Me

Mp

Only 1-0 transitions allowed at inputs of PUN Used a lot in the Alpha design
Krish Chakrabarty 27

np CMOS Adder
VDD A1 VDD A0 A0 Ci0 Carry Path B0 B0 Ci1 A0 B0 Ci0 B1 B1 A1 Ci2 A1 VDD VD D Ci1 Ci1 A1 B1 VDD VDD B0 A0 Ci0 VD D S1

B1

S0

Krish Chakrabarty

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CMOS Circuit Styles - Summary

Krish Chakrabarty

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