Code No: 54105/MT

NR
M.Tech. – I Semester Supplementary Examinations,
September, 2008

VLSI TECHNOLOGY & DESIGN

(Common to Embedded Systems/ Digital Systems & Computer
Electronics/ VLSI System Design/ Communication Systems)

Time: 3hours Max. Marks:60

Answer any FIVE questions

All questions carry equal marks
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1.a) What are the various processes of CMOS fabrication? Illustrate the
main steps in a typical n-well process.
b) Tabulate the comparism between CMOS and Bipolar Technologies.

2.a) Determine the Pull-up to Pull-down ratio for an nMOS inverter

driven through one or more pass transistors.
b) Draw a simple BiCMOS inverter circuit diagram and explain its
operation.

3.a) Explain about scalable Design rules related to NMOS and CMOS
Technologies.
b) With suitable diagrams explain some switch logic arrangements.

4.a) With neat sketches describe the various Layout Design methods.
b) Explain the clocking Analysis related to sequential systems.

5.a) With relevant diagrams explain about various Floorplanning

methods used in Layout design.
b) Explain the design Methodology for IBM ASICs.

6.a) Give the device structure for CMOS inverter and explain the same.
b) Draw Latch-up circuit model and explain its operation.

7.a) Briefly explain an important issues in system-on-chip design.

b) Write notes on Architecture Testing related Architecture VLSI
Design.

8. Write notes on any Two of the following:

a) Wires and Vias
b) Design validation and Testing.
c) The Integrated circuit (IC) Era.

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