Abstract This paper proposes a new arrangement to

implement the dc voltage sources of hybrid multilevel inverters

in active power transfer applications, using only uncontrolled
rectifiers and phase-shifted secondary windings. As each cell of
a hybrid multilevel inverter usually processes distinct power
levels, this paper then proposes a new design methodology to
determine the phase shifts among the secondaries of the input
isolation transformer, even when the active power levels
processed by the uncontrolled rectifiers are unequal. A set of
phase angles is obtained to minimize, and even to eliminate,
desired low-order harmonics of the input current, in particular
the fifth harmonic, since this harmonic component presents an
amplitude considerably higher than the amplitude of the other
harmonics. In consequence, the proposed design methodology
increases the input power factor and reduces the input current
THD. Simulation and experimental results are presented to
demonstrate the feasibility of the proposed structure.
I. INTRODUCTION
Voltage-source multilevel converters have been used in
active power transfer applications, such as medium-voltage
adjustable speed drives (ASDs), because low voltage levels
are imposed to power devices and voltage change rates are
lower than those obtained with two-level converters.
Multilevel ASDs also synthesize waveforms with reduced
harmonic content and present increased efficiency, because
they usually operate with low switching frequency [1], [2].
Among several multilevel topologies, asymmetrical
inverters with series-connected cells are receiving special
attention, mainly because they can synthesize voltage
waveforms with reduced harmonic content even using few
cells [3], [4]. This advantage is achieved by using distinct
voltage levels in the different cells, being able to create more
levels in the output voltage and minimizing the output
voltage THD (Total Harmonic Distortion). Moreover, a
hybrid modulation strategy can be used so that higher power
cells operate at low frequency and only the lowest power cell
operates at high frequency, obtaining a high-voltage high-
quality waveform [5][7]. On the other hand, as each cell
usually processes unequal power levels, the implementation
of the dc voltage sources for applications with active power
flow is still little discussed.
In applications with active power transfer, the H-bridge
(single-phase full-bridge inverter) cells must be connected to
a power supply system, such as batteries [1], or the utility
grid [2]. One of the simplest methods of obtaining a dc
voltage source from the utility grid is to employ an
uncontrolled six-pulse rectifier. This rectifier is basically
composed of a three-phase diode bridge and a filter
capacitor to reduce the dc bus voltage ripple. However, the
line currents drawn from the utility grid present high THD
when ac or dc filter inductances are not large enough to
minimize the harmonic currents [8], [9].
On the other hand, as it is necessary to employ an
isolation transformer with several secondary windings to
implement the isolated dc voltage sources, it is possible to
eliminate some harmonic components of the input currents
with multipulse connection of rectifiers [10][12].
Designing adequate phase shifts among the secondaries, the
harmonic currents generated by one rectifier can be
cancelled by harmonics produced by others rectifiers.
Nevertheless, by using the symmetrical design methodology
to compute the phase shifts, certain low frequency harmonics
of the input currents will be eliminated only when the active
power levels processed by rectifiers and their impedances
(filter inductances and dc bus capacitors) are equal. Hence,
for applications in which the rectifiers usually process
distinct power levels, such as asymmetrical and hybrid
multilevel converters, the line currents will present some
undesired harmonics by using symmetrical phase shifts
among the secondary windings [13].
To overcome this lack, this paper proposes a new
arrangement for multipulse connection of asymmetrically-
loaded rectifiers. This arrangement is particularly suitable
for implementing the dc voltage sources of hybrid multilevel
inverters applied to medium voltage ASDs, as illustrated in
Fig. 1. A new design methodology is proposed to compute
the phase shifts among the secondary windings of the
isolation transformer, even when the active power levels
processed by rectifiers and their impedances are unequal. A
set of phase shifts is obtained to minimize, and even to
eliminate, desired low-order harmonics of the input current,
in particular the fifth harmonic, since this harmonic
component presents an amplitude considerably higher than
the amplitude of other harmonics [8], [9]. Consequently, the
proposed design methodology increases the input power
factor and reduces the input current THD.
This paper is organized as follows: Section II describes
some basic assumptions adopted to analyze the performance
of multipulse connection of rectifiers. Section III introduces
the symmetrical design methodology to compute the phase
shifts among the secondaries, and Section IV proposes a new
asymmetrical design methodology, which can be applied
even when the rectifiers process unequal power levels.
Section V applies this design methodology to the input
rectifier stage of hybrid multilevel converters and presents
experimental results to validate the theoretical analysis.

Line Current Harmonics Reduction in Hybrid Multilevel
Converters Using Phase-Shifting Transformers

C. Rech, J. R. Pinheiro
Power Electronics and Control Research Group
Federal University of Santa Maria, Brazil
Email: cassiano@ieee.org, renes@ctlab.ufsm.br; URL: http://www.ufsm.br/gepoc
2004 35th Annual IEEE Power Electronics Specialists Conference Aachen, Germany, 2004
0-7803-8399-0/04/$20.00 2004 IEEE. 2565
II. BASIC ASSUMPTIONS
The following analyses assume, unless stated otherwise,
that the j
th
six-pulse diode rectifier (j = 1, 2, , n) is
supplied by a balanced three-phase power supply,
represented by a sinusoidal phase-to-neutral voltage V
s,j
and
an inductance L
s,j
, as shown in Fig. 2. Considering that this
rectifier composes the input stage of a high-power ASD, the
equivalent series resistances are small and they are therefore
neglected hereafter. Moreover, the rectifier output filter is
only composed of a capacitor C
b,j
, because the inclusion of a
dc filter inductance would add more weight, volume and cost
to each rectifier. The dc bus capacitor C
b,j
produces a dc
voltage V
dc,j
with low frequency ripple, and the dc current
source I
dc,j
models the rectifier load.
In addition, it is interesting to normalize all variables and
system parameters so that the results obtained in harmonic
analyses are independent from voltage and current levels.
Hence, voltage and current base values are defined as:
, , base j s j
V V = and
, ,
,
, 1,
3 cos
dc j dc j
base j
s j j
V I
I
V
=

(1)
where
1,j
is the angle between the phase-to-neutral voltage
and the fundamental component of its respective line current.
After defining these base values, it is possible to obtain the
normalized input reactance X
L,j
and the normalized reactance
X
C,j
of the dc bus capacitor. It is well known that the input
current harmonics decrease sensibly for higher values of X
L,j
.
Furthermore, fifth and seventh harmonics present the highest
amplitudes [8], [9]. Then, these two harmonics should be
eliminated or minimized to reduce the input current THD.
III. MULTIPULSE CONNECTION OF RECTIFIERS:
SYMMETRICAL DESIGN METHODOLOGY
As multilevel inverters with series-connected cells should
employ an input transformer to implement the isolated
voltage sources, it is possible to reduce the harmonic content
of the input currents by using multipulse converters
[10][12], which use the phase shifts among the secondaries
to cancel certain harmonic currents. Therefore, besides the
galvanic isolation among the dc voltage sources and voltage
matching among ac and dc sources, the input transformer
can be also employed to minimize the harmonic content of
the input currents.
Fig. 3 illustrates the input equivalent circuit of a multilevel
inverter, which supplies a balanced three-phase load, with n
series-connected cells per phase. Although different
transformer configurations can be used, this isolation
transformer has one delta-connected primary winding and star-
type (wye and zig-zag connections) secondaries. It is also
important to emphasize that, due to the fact that each cell can
present unequal voltage and current ratings, each rectifier has
its own voltage (V
base,j
) and current base values (I
base,j
).
The j
th
secondary line current can be expressed as:
( )
, , ,
1,5,7,...
( ) 2 sin
S j h j j h j
h
i t I h t

=

= + +

(2)
where
j
is the angle between the j
th
secondary line voltage
and primary line voltage, and I
h,j
and
h,j
are, respectively,
the rms value and phase (considering
j
= 0) of the h
th

current harmonic drawn by the j
th
six-pulse diode rectifier.
All positive-sequence current components (I
1,j
, I
7,j
, I
13,j
, ...)

Fig. 1 Proposed hybrid multilevel ASD.

Fig. 2 Equivalent circuit of the j
th
six-pulse diode rectifier.
2004 35th Annual IEEE Power Electronics Specialists Conference Aachen, Germany, 2004
2566
of the primary line current lag their corresponding positive-
sequence components in the secondary line current by a
phase angle
j
. On the other hand, all negative-sequence
current components (I
5,j
, I
11,j
, I
17,j
, ...) of the primary line
current lead their corresponding harmonic components in
the secondary line current by the same angle
j
[11].
Consequently, the corresponding primary line current is:
( ) ( )
( )
1, 1, , ,
5,11,... ,
1,2,...
, ,
7,13,...
sin sin
2
( )
sin
j j h j j j h j
n
h L j
P
j P
h j j j h j
h
I t I h t
V
i t
V
I h t

=
=


+ + + + + +



=

+ + +

(3)
where V
P
is the primary line voltage and V
L,j
is the line voltage
of the j
th
secondary winding.
Therefore, from (3) and considering that the impedances
and active power levels processed by all rectifiers are equal,
it is possible to demonstrate that the minimum phase shift
(
min
) among the secondary windings to cancel dominant
input current harmonics can be obtained as:
min
60 n = (degrees). (4)
Fig. 4 shows simulation results of a multipulse connection
with three identical rectifiers, which process the same power
levels and have the same impedances. The phase shifts among
the secondaries are obtained from (4), so that:
1
= 20,

2
= -20 and
3
= 0. Although secondary line currents
present high THD, Fig. 4(a) illustrates that primary current has
a reduced harmonic content (THD = 6%), even with small
input reactances (X
L,j
= 0.01 p.u.
j
), mainly because 5
th
, 7
th
, 11
th

and 13
th
harmonics are eliminated, as shown in Fig. 4(b).
On the other hand, Fig. 5 presents simulation results of a
multipulse configuration with three rectifiers processing
unequal power levels, but maintaining the symmetrical phase
shifts. In this case, the dominant harmonics of the primary
line current (Fig. 5(a)) are not eliminated, as can be seen in
Fig. 5(b), resulting in a higher THD (16.2%).
An alternative method for improving the input harmonic
performance has been presented in [13] for asymmetrically-
loaded rectifiers. This method employs six-pulse rectifiers
connected in parallel and/or in series for each output cell, so
that all secondaries process equal power levels. Thus, it is
possible to cancel the dominant current harmonics, even using
the phase shifts computed from (4). However, it is necessary

Fig. 3 Equivalent circuit of the input rectifier stage of a multilevel
inverter with n series-connected cells per phase.

(a)

(b)
Fig. 4 Symmetrical multipulse connection of rectifiers with equal power
levels (Xc,j = 0.1 p.u.j, XL,j = 0.01 p.u.j, VL,j = VP, Idc,j = 15 A). (a) Primary
line current waveform. (b) Harmonic spectrum.

(a)

(b)
Fig. 5 Symmetrical multipulse connection of rectifiers with unequal power
levels (Xc,j = 0.1 p.u.j, XL,j = 0.01 p.u.j, VL,j = VP, Idc,1 = 10 A, Idc,2 = 15 A,
Idc,3 = 20 A). (a) Primary line current waveform. (b) Harmonic spectrum.
2004 35th Annual IEEE Power Electronics Specialists Conference Aachen, Germany, 2004
2567
to use several rectifiers for highly asymmetric loads,
increasing complexity and cost of the overall system.
Another option is to modify the phase shifts among the
secondaries in order to reduce the input current THD without
increase the number of rectifiers. A new design methodology
is developed in the next section to compute these phase shifts,
considering the active power level processed by each rectifier.
IV. MULTIPULSE CONNECTION OF RECTIFIERS:
ASYMMETRICAL DESIGN METHODOLOGY
As the fifth harmonic typically presents the highest
amplitude, it would be desirable to eliminate it, even when
the rectifiers process unequal active power levels. From (3)
and considering that
n
is the reference angle, the fifth
harmonic amplitude can be given as:
( ) ( )
( ) ( )
2
,1 ,
5,1 1 5,1 5, 5,
5,
2
,1 ,
5,1 1 5,1 5, 5,
cos 6 ... cos
sin 6 ... sin
L L n
n n
P P
P
L L n
n n
P P
V V
I I
V V
I
V V
I I
V V

+ + + +


=

+ + +



(5)
It can be seen that the fifth harmonic amplitude depends
on these phase shifts, that is, I
5,p
= f(
1
,
2
, ,
n1
).
Assuming that this function has at least one minimum point,
the following conditions must be satisfied to obtain a set of
phase shifts that minimize I
5,P
[14]:
1 2 1
... 0
n
f f f

= = = =


(6)
2 2 2
2 2 2
1 2 1
0 or 0 or ... or 0
n
f f f

| |
> > >
|

\ .
.
(7)
A global minimum point presents the second derivative with
the highest amplitude among the points that satisfy (6) and (7).
Consequently, from primary and secondary line voltages and
from fifth harmonic of the current drawn by six-pulse rectifiers
[8], [9], it is possible to determine a set of phase shifts among
the secondaries, using (5)(7), to minimize, or even to
eliminate, the fifth harmonic of the primary line currents.
Depending on the number of secondaries and the power
levels processed by the rectifiers, there are several solutions
to eliminate the fifth harmonic. The advantage of being able
to find more than one solution means that it increases the
possibility of finding a set of phase shifts that could also
achieve secondary objectives. One secondary objective
could be the reduction of THD, another could be the
minimization of other low-order harmonics.
Fig. 6 shows the fifth harmonic amplitude of the primary
line current, by varying the phase shifts among the
secondary windings of a multipulse connection with three
rectifiers processing unequal power levels and with same
normalized impedances. In this case, when the active power
processed by the second rectifier is 50% greater than the
power of the first cell and the active power processed by the
third rectifier is two times greater than the active power of
the first rectifier, the fifth harmonic of the primary current
has minimum points when
1
= -22.2 and
2
= +25.2,
or
1
= +22.2 and
2
= -25.2. The fifth harmonic is
cancelled by using one of these sets, as can be verified in
Fig. 7(b). In consequence, the THD of the input current
decreases from 16.2% (Fig. 5(a)) to 8.8% (Fig. 7(a)).
On the other hand, there are some applications in which
the fifth harmonic of the input current cannot be eliminated,
because the fifth harmonic produced by one rectifier is
larger than the fifth harmonic produced by all other
rectifiers. For instance, in a multipulse connection of n
rectifiers with same normalized impedances, when the n
th

rectifier processes more than 50% of the total output active
power, it is only possible to minimize the fifth harmonic of
the input current when
1
=
2
= ... =
n-1
= 30.
In this case, an alternative method to eliminate the fifth

Fig. 6 Fifth harmonic amplitude of the primary current versus phase
shifts. Unequal power levels (P2 = 1.5P1 and P3 = 2P1).

(a)

(b)
Fig. 7 Asymmetrical multipulse connection of rectifiers with unequal
power levels (Xc,j = 0.1 p.u.j, XL,j = 0.01 p.u.j, VL,j = VP, Idc,1 = 10 A,
Idc,2 = 15 A, Idc,3 = 20 A, 1 = 22.2 and 2 = -25.2). (a) Primary line
current. (b) Harmonic spectrum.
2004 35th Annual IEEE Power Electronics Specialists Conference Aachen, Germany, 2004
2568
harmonic from the input current is to connect two rectifiers in
parallel or in series only for the highest power cell. Hence,
each of these two series- or parallel-connected rectifiers
processes half power and, then, there is no rectifier that
processes more than 50% of the total output active power.
With this, there are n output cells and n+1 rectifiers.
Then, as these phase shifts are computed even with rectifiers
processing unequal power levels, this design methodology can
be applied to the input stage of hybrid multilevel inverters.
V. MULTIPULSE CONNECTION OF RECTIFIERS APPLIED TO
HYBRID MULTILEVEL CONVERTERS
Hybrid multilevel converters are systems composed of
several cells connected in series or in parallel, which present
distinct topologies, voltage/current levels, modulation
strategies and/or semiconductors technologies, so that it is
possible to obtain waveforms with reduced harmonic content
and to optimize the power processing of the overall system.
A. Basic description of hybrid multilevel inverters
If at least one of the dc voltage sources differs from the
others, the multilevel inverter shown in Fig. 1 can be called
asymmetrical multilevel inverter. Considering that the lowest
dc voltage source (V
dc,1
) is chosen as base value for the p.u.
notation of the inverter, the normalized values of all dc
sources (V
j
) must be natural numbers and respect the following
relation to obtain uniform step multilevel waveforms [3]:
1
1
1
1 2
j
j j k
k
V V V

=
+

, j = 2, 3, ..., n.
(8)
Thus, the maximum number of levels of an output phase-
to-neutral voltage waveform can be given as:
1
1 2
n
j
j
m V
=
= +

.
(9)
It can be seen that, for the same number of cells,
asymmetrical inverters can generate a larger number of
levels than those obtained by using equal dc voltage sources.
However, the power devices of different cells are subjected
to distinct voltage levels. Then, a hybrid approach has been
proposed in [5], [6], called hybrid multilevel inverter, which
uses a synergistic approach that combines the fast switching
ability of IGBTs or MOSFETs and large voltage blocking
capability of IGCTs or GTOs. Therefore, a generalized
modulation strategy has been presented in [6], which uses
stepped voltage waveform synthesis in higher power H-
bridge cells in conjunction with high-frequency pulse width
modulation (PWM) in the lowest power cell. However, with
this modulation strategy, the dc voltage sources must satisfy
the following equation to synthesize a voltage waveform
modulated at high frequency among all adjacent steps:
1
1
2
j
j k
k
V V

, j = 2, 3, ..., n. (10)
When (10) is satisfied, the spectral response of the output
voltage depends on the switching frequency of the lowest
power cell, while the power processing depends basically on
the inverter with the highest dc voltage source.
B. Design methodology of the hybrid multilevel inverter
There are several possibilities for setting the value of the
dc voltage source of each cell to obtain the same number of
levels, mainly when this number of levels increases.
Although distinct configurations of dc sources can result in
the same number of levels, the power processing of the
hybrid multilevel inverter differs from one configuration to
another. It is then important to employ a methodology to
define the number of cells and the dc voltage levels [7].
The definition of the number of cells and the dc voltage
levels of each cell must consider the topologies employed to
implement these sources. Assuming that all dc voltage
sources are implemented with diode rectifiers, then it is not
possible to regenerate energy from load to source. For this
case, Fig. 8 presents the normalized values of the dc sources
that ensure that all H-bridge cells will not regenerate energy
in motor mode for any value of m
a
(amplitude modulation
index) without penalizing the output voltage THD.

Fig. 8 Normalized dc voltage sources of the H-bridge cells.
C. Simulation results
Table I gives the main parameters of the hybrid multilevel
system used in computer simulations. With these dc voltage
sources (V
1
= V
2
= 1 p.u., V
3
= 2 p.u.), it is possible to
synthesize phase-to-neutral voltages with nine levels and all
H-bridge cells will not regenerate energy in motor mode for
any value of m
a
(Fig. 8). Consequently, the dc voltage
sources of all cells can be implemented with six-pulse diode
rectifiers. Furthermore, with these voltage levels and with a
hybrid modulation strategy, in which only the lowest power
cell operates at high frequency, the third H-bridge cell
(highest power cell) processes 63.7% of the output phase
power (P
o
) whereas the second cell processes 23% and the
first cell (lowest power cell) processes 13.3% of P
o
.
In this case, it would not be possible to eliminate the fifth
harmonic from primary currents, because the highest power
cell processes more active power than the other two cells
together. Thus, using the configuration illustrated in Fig. 3, it
TABLE I SYSTEM PARAMETERS.
AC input line voltage VP = 380 VRMS
Input frequency f = 60 Hz
Nominal output power Po = 1 kW
DC bus voltages Vdc,1 = 85 V, Vdc,2 = 85 V, Vdc,3 = 170 V
Normalized reactances XL,j = 0.01 p.u.j, XC,j = 0.1 p.u.j
2004 35th Annual IEEE Power Electronics Specialists Conference Aachen, Germany, 2004
2569
is only possible to minimize the fifth harmonic when, for
instance,
1
= 30,
2
= -30 and
3
= 0, as presented
in Table II, which gives the phase shifts among the
secondary windings for distinct multipulse configurations.
The symmetrical phase shifts are those computed from (4) and
the asymmetrical phase shifts are those obtained to minimize
or even to eliminate the fifth harmonic from input currents.
As discussed in the previous section, an alternative
approach to eliminate the fifth harmonic is to use two
rectifiers in series for the highest power cell, as shown in
Fig. 9. Each of these two rectifiers will process half power
(31.85%) and, consequently, it will be possible to eliminate
the fifth harmonic from primary currents. From the active
power levels processed by each rectifier and using (5)(7), it
is possible to demonstrate that a set of phase shifts among
the secondaries that eliminates the fifth harmonic is given
by:
1
= 13.9,
2
= -16.3 and
3
= 27.1.
Fig. 10(a) presents a phase-to-neutral voltage and its
respective primary line current (THD = 5.2%) when two
rectifiers are connected in series for the highest power cell.
The secondary windings are phase-shifted to eliminate the
fifth harmonic, even with these asymmetrically-loaded
rectifiers. As expected, Fig. 10(b) shows that the fifth
harmonic is eliminated with this set of phase shifts.
Table III compares the THD of primary line currents for
distinct multipulse configurations, which have three, four or
even five six-pulse diode rectifiers and use different sets of
phase shifts. This table shows that the input harmonic
performance is significantly improved by phase-shifting the
secondary windings. This harmonic performance is even
better when more rectifiers are utilized to reduce the power
asymmetry among the rectifiers, and when the phase shifts
are computed to minimize, or even to cancel, the fifth
harmonic. However, the THD decreases only from 5.2% to
3.7% when three rectifiers are used in the highest power cell,
increasing the cost and complexity of the system without
improving significantly the harmonic performance.
D. Experimental results
A simplified diagram of the experimental setup with 4
asymmetrically-loaded rectifiers is shown in Fig. 9, and the
parameters are the same used in computer simulations (Tables
I and II), where the secondaries are phase-shifted among them
to eliminate the fifth harmonic from primary currents.
TABLE II PHASE SHIFTS AMONG THE SECONDARY WINDINGS.
Number of
rectifiers
Rectifier loads
Symmetrical
phase shifts
Asymmetrical
phase shifts
3
P1 = 133W
P2 = 230W
P3 = 637W
1 = 20
2 = 20
3 = 0
1 = 30
2 = 30
3 = 0
4
(1)
P1 = 133W
P2 = 230W
P3 = 318.5W
P4 = 318.5W
1 = 15
2 = 15
3 = 30
4 = 0
1 = 13.9
2 = 16.3
3 = 27.1
4 = 0
5
(2)
P1 = 133W
P2 = 230W
P3 = 213.3W
P4 = 213.3W
P5 = 213.3W
1 = 12
2 = 12
3 = 24
4 = 24
5 = 0
1 = 11.8
2 = 11.6
3 = 21.7
4 = 26.6
5 = 0
(1) Two series-connected rectifiers for the highest power cell.
(2) Three series-connected rectifiers for the highest power cell.

Fig. 9 Simplified diagram of an input rectifier stage proposed for the
hybrid 9-level inverter.

(a)

(b)
Fig. 10 Simulation result: Fifth harmonic elimination with multipulse
connection of rectifiers applied to a 9-level hybrid inverter (1 = 13.9,
2 = -16.3, 3 = 27.1, 4 = 0). (a) Primary line current and phase-to-
neutral voltage. (b) Harmonic spectrum.
TABLE III THD OF PRIMARY LINE CURRENTS.
Number of
rectifiers
Without phase
shifts
Symmetrical
phase shifts
Asymmetrical
phase shifts
3 81.3% 36.5% 24.1%
4 81.3% 9.3% 5.2%
5 81.3% 7.7% 3.7%

2004 35th Annual IEEE Power Electronics Specialists Conference Aachen, Germany, 2004
2570
Fig. 11(a) shows the phase-shifted secondary line a
currents and Fig. 11(b) presents the low-distortion primary
line currents. Fig. 11(c) illustrates the primary line a
current (THD = 4.2%) with its respective phase-to-neutral
voltage waveform, indicating a close-to-unity input power
factor (PF = 0.99). It is possible to observe that fifth
harmonic is practically eliminated by using the phase shifts
computed from the proposed design methodology.

(a)

(b)

(c)

(d)
Fig. 11 Experimental results. (a) Secondary line a currents (5A/div).
(b) Primary line currents (2A/div) (b) Primary line a current (2A/div) and
phase-to-neutral voltage. (c) Harmonic spectrum of primary line a current.
VI. CONCLUSION
Input harmonic performance of multipulse configurations
of asymmetrically-loaded uncontrolled rectifiers can be
improved by connecting some rectifiers in series and/or in
parallel to reduce the power asymmetry among the
secondary windings. However, it would be necessary to use
several rectifiers for highly asymmetric loads, increasing
considerably the complexity and cost of the overall system.
Therefore, to overcome this problem, this paper proposed a
new arrangement to reduce the line current harmonics in
multipulse connection of asymmetrically-loaded diode
rectifiers. A new design methodology is proposed to determine
a set of phase shifts among the secondaries of the input
isolation transformer, to minimize, and even to eliminate,
desired low-order harmonics of input currents even when the
active power levels processed by rectifiers are unequal.
Consequently, this design methodology can be employed to
design multipulse connection of rectifiers for the input stage of
hybrid multilevel inverters, since the series-connected cells
usually process distinct active power levels. Simulation and
experimental results demonstrated that this new arrangement
can be employed to obtain a close-to-unity input power factor
and to reduce the input current THD.
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