LAB MANUAL

FOR

SPARTAN-3 INTERFACING MODULE MODEL : MXS3FK-PQ208-IM Rev : 003

MECHATRONICS TEST EQUIPMENT (I) PVT.LTD. B-3,MAYUR COMPLEX, OPP. BHELKE NAGAR, NEAR YASHAVANTRAO CHAVAN NATYAGRUH, KOTHRUD, PUNE- 411038

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Table of contents

PREFACE......................................................................................................................................... 1 ABOUT THIS MANUAL................................................................................................................. 1 MANUAL CONTENTS................................................................................................................ 1 CHAPTER 1...................................................................................................................................... 2 STUDY OF SIMULATION TOOLS................................................................................................. 2 1.1SIMULATION USING XILINX HDL BENCHER..................................................................... 2 1.2 SIMULATION USING MODELSIM SIMULATOR............................................................... 11 CHAPTER 2.................................................................................................................................... 16 STUDY OF SYNTHESIS TOOLS................................................................................................ 16 CHAPTER 3.................................................................................................................................... 23 PLACE AND ROUTE AND BACK ANNOTATION FOR FPGA.................................................... 23 CHAPTER 4.................................................................................................................................... 26 STUDY OF DEVELOPMENT TOOL FOR FPGA FOR SCHEMATIC ENTRY............................. 26 CHAPTER 5.................................................................................................................................... 32 TRAFFIC LIGHT CONTROLLER USING FPGA.......................................................................... 5.1 DESIGN DESCRIPTION:-.................................................................................................. 5.2 EXPERIMENTAL SET UP:-................................................................................................ 5.3 COMPONENT DIAGRAM .............................................................................................. 32 32 35 36

CHAPTER 6.................................................................................................................................... 45 DESIGN AND SIMULATION OF PIPELINED SERIAL AND PARALLEL ADDER ....................... 45 6.1 DESIGN DESCRIPTION:-.................................................................................................. 45 6.2 PROCEDURE:-.................................................................................................................. 46 6.3 VHDL CODE FOR RIPPLE CARRY ADDER..................................................................... 48 CHAPTER 7.................................................................................................................................... 49 DESIGN AND SIMULATION OF SIGNED 8 BIT MULTIPLIER ................................................... 49 7.1 DESIGN DESCRIPTION:-.................................................................................................. 49 7.2 PROCEDURE:-.................................................................................................................. 50 CHAPTER 8.................................................................................................................................... 52 STUDY OF FPGA BOARD AND TESTING ON BOARD LED AND SWITCHES......................... 8.1 DIP SWITCHES ................................................................................................................ 8.2 KEY SWITCHES................................................................................................................ 8.3 LEDS.................................................................................................................................. 8.4 VHDL CODE FOR LEDS AND SWITCHES....................................................................... 52 52 52 52 52

CHAPTER 9.................................................................................................................................... 55 TESTING THE TRAFFIC CONTROLLER DESIGN ON THE FPGA BOARD.............................. 55

CHAPTER 10.................................................................................................................................. 61 REAL CLOCK TIMER.................................................................................................................. 61 10.1 DESCRIPTION FOR REAL CLOCK TIMER..................................................................... 61 10.2 VHDL CODE FOR REAL CLOCK TIMER........................................................................ 61

PREFACE
About This Manual
Manual Contents
This manual contains following chapters: Chapter 1, Study of Simulation using tools Chapter 2, Study of Synthesis tools Chapter 3, Place and Root and Back annotation for FPGAs Chapter 4, Study of development tool for FPGAs for schematic entry and vhdl Chapter 5, Design of traffic light controller using vhdl and above tools Chapter 6, Design and simulation of pipelined serial and parallel adder Chapter 7, Design and Simulation of Signed 8 bit Multiplier Chapter 8, Study of FPGA board and testing on board LEDs and switches Chapter 9, Testing the traffic controller design on the FPGA board Chapter 10, Design a Real Time Clock and its working on the FPGA board

CHAPTER 1
Study of Simulation Tools
Simulation is functional emulation of the circuit design through software programs that uses models to replicate how a system will perform in terms of timings and results. Xilinx ISE tool supports the following simulation tools: HDL Bencher is an automated test bench creation tool. It is fully integrated with Project Navigator. ModelSim from Model Technology, Inc, is integrated in Project Navigator to simulate the design at all steps (Functional and Timing). ModelSim XE, the Xilinx Edition of Model Technology, Inc.s ModelSim application, can be installed from the MTE CD included in your ISE Tool

1.1 Simulation using Xilinx HDL Bencher

[[

Step1:

Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Programs Xilinx ISE (8.2i).

E SOURC WINDO W

WORK SPACE

PROCESS WINDOW

TRANSCRIP T

Step2:

Create a new project Select File menu and then select New project.

Specify the project name and location in pop up window and click NEXT

Select Device. Select the required family, device, package, speed grade, Synthesis tool Simulator from new project wizard pop up window. Click NEXT. Project summary will be displayed.

Click FINISH to start Project.

Step 3:

To create new VHD file Right click on the device name and select NEW SOURCE

Select VHDL MODULE in NEW SOURCE WIZARD and give suitable name for the Project. Click NEXT for the DEFINE MODULE Window.

VHDL MODUL

Assign required ports in this Window. The direction

Step 4:

Write the Behavioural VHDL Code in VHDL Editor Sample code is given below for this experiment.

Step 5:

SIMULATION using ISE tool Creating a test bench file Verify the operation of your design before you implement it as hardware. Simulation can be done using ISE simulator. For this click on the symbol of FPGA device and then right click Click on new source Test Bench Waveform and give the name Select entityFinish.

The window to Select Clock, Duty Cycle will appear. Select required parameters and say FINISH

Step 6:

BEHAVIOURAL SIMULATION Select Behavioural Simulation from the scroll down list.

Step 7:

Give wave pattern on the input signals as required. Then double click on Simulate Behavioural Model for simulating.

The wave form according to the inputs given will appear in the window. The wave form can be analysed for the correctness of functionality.

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1.2 Simulation Using Modelsim Simulator

Step 1: Step 2: Repeat the steps for creating a design as in ISE HDL Bencher flow Click on the device name and go to properties. Select ModelSim VHDL in that.

Step 3:

Click on the device name and go to properties. Select ModelSim VHDL in that.

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Step 4:

Select Behavioural Simulation from the scroll down list. Double click on Simulate Behavioural Model to open Model Sim Simulator.

Step 5:

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Step 6:

Enlarged view of waveform.

Step 7:

POST TRANSLATE SIMULATION Similarly select Post-Translate Simulation and run Model Sim. The observed waveform is given below. The delay after Translating Behavioural Model to RTL Model can be observed.

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Step 8:

POST MAP SIMULATION Similarly select Post-MAP Simulation and run Model Sim. The observed waveform is given below. The Post Map Simulation shows the delay in output after mapping the signals into FPGA.

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Step 9:

POST ROUTE SIMULATION Similarly select Post-Route Simulation and run Model Sim. The Post Route Simulation shows the delay in output after Routing all the signals in FPGA, including Global Clock. This will be the maximum delay for getting the output. The observed waveform is given below.

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CHAPTER 2
Study of Synthesis Tools
Synthesis describes the process of transformation of the model of a design, from one level of abstraction in one domain [say HDL] to a lower level of abstraction in same or other domain. Step 1: Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Programs Xilinx ISE (8.2i).

E SOURC WINDO W

WORK SPACE

PROCESS WINDOW

TRANSCRIP T

16

Step 2:

Create a new project In the window go to FILE New project.

Specify the project name and location on window that appears and say NEXT

Select Device. Select the device, package and speed needed from choice given. Click in the field to access the pull-down list. The Simulator we like to select can be selected here. Click NEXT for next option.

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The Project Summary is displayed and we can verify it.

Say FINISH to start Project.

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Step 3:

To create new VHD file Right click on the device name and select NEW SOURCE

Select VHDL MODULE in NEW SOURCE WIZARD and give suitable name for the Project. Click NEXT for the DEFINE MODULE Window.

VHDL MODUL

Assign required ports in this Window. The direction

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Step 4:

Write the Behavioural VHDL Code in VHDL Editor Sample code is given below for this experiment.

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Check Syntax Run the Check syntax Process window synthesizecheck syntax >, and remove errors if present Step 5: Synthesize the design using XST. Translate your design into gates and optimize it for the target architecture. This is the synthesis phase. Again for synthesizing your design, from the source window selects synthesis/Implementation from the drop-down menu.

SYNTHESI S

Highlight file in the Sources in Project window. To run synthesis, right-click on Synthesize, and the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed. a red cross indicates an error was generated and a yellow exclamation ! mark indicates that a warning was generated. Check the synthesis report. If there are any errors correct it and rerun synthesis

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SYNTHESIS COMPLETED SUCCESSFULL

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CHAPTER 3
Place and Route and Back Annotation for FPGA
Back annotation is the translation of a routed or fitted design to a timing simulation netlist. To define the behavior of the FPGA, a hardware description language (HDL) or a schematic design methods are used. Common HDLs are VHDL and Verilog. Then, using an electronic design automation tool, a technology-mapped netlist is generated. The netlist can then be fitted to the actual FPGA architecture using a process called place-and-route, usually performed by the FPGA Companys proprietary place-and-route software. The user will validate the map, place and route results via timing analysis, simulation, and other verification methodologies. Once the design and validation process is complete, the binary file generated and is used to (re)configure the FPGA. In an attempt to reduce the complexity of designing in HDLs, which have been compared to the equivalent of assembly languages, there are moves to raise the abstraction level of the design. To simplify the design of complex systems in FPGAs, there exist libraries of predefined complex functions and circuits that have been tested and optimized to speed up the design process. These predefined circuits are commonly called IP cores, and are available from FPGA vendors and thirdparty IP suppliers. In a typical design flow, an FPGA application developer will simulate the design at multiple stages throughout the design process. Initially the RTL description in VHDL or Verilog is simulated by creating test benches to simulate the system and observe results. Then, after the synthesis engine has mapped the design to a netlist, the netlist is translated to a gate level description where simulation is repeated to confirm the synthesis proceeded without errors. Finally the design is laid out in the FPGA at which point propagation delays can be added and the simulation run again with these values back-annotated onto the netlist.

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After Synthesis, go to back annotate pin location in Implement Design and double click to start back annotation.

In back annotation the tool translates and routes the logic in FPGA and generates the constraint file such that minimum delay paths are included. This helps to make the design faster.

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Once back annotation is completed, constraint file is generated.

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CHAPTER 4
Study of Development Tool for FPGA for Schematic Entry
This topic gives the overview of schematic entry using ISE .The steps to generate a full adder is given in this chapter. We generate Truth Table for the required functionality. Solve the Equation and we get the gates required to implement the design.

1. Full Adder Truth Table

C 0 1 0 1 0 1 0 1
2. Solving Equation

Input A 0 0 1 1 0 0 1 1

Output B 0 0 0 0 1 1 1 1 S 0 1 1 0 1 0 0 1 C 0 0 0 1 0 1 1 1

S = A*B*C + AB*C* + A*BC* + ABC = (A XOR B) XOR C C1 = AB*C + ABC + ABC* + ABC = AB + (A XOR B) C

Once the schematic is finalised we can enter it to FPGA schematic editor and the steps are given below.

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Step 1:

Select SCHEMATIC from new source and assign name to the file.

Step 2:

From the Sources select LOGIC and from symbols we can pick and drop any gates we need. Selection of XOR gate is shown below.

Step 3:

Once the component is selected, for providing connection to other components or

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external input, we can use ADD WIRE option, as shown below.

ADD WIRE

For Assigning Entity, ie input or output signals, we can use ADD I/O MARKER

ADD I/O MARKER

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Double Click on the IO Marker and in the Pop up window assign name for the Signal.

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Step 4:

The Completed Schematics is given below

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Step 5:

After the schematic entry is completed go to the SOURCES and SYNTHESIS the design.

To view the VHF file generated Clock on View HDL functional model in design utilities

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CHAPTER 5
Traffic Light Controller using FPGA
Traffic Light controller is implemented on FPGA and verified using Traffic Light Interface Module. There are simple rules for traffic lights on one node, and complex ways of regulating a whole infrastructure of them. It is necessary to adjust general algorithms

5.1 Design Description: Initially all Red Lights will be ON (South, west, North, East, Pedestrian) Green Lights of will be ON, Right, Left & Straight paths are free for Traffic. Yellow Phase is split as yellow1 & yellow2. In yellow1 phase yellow lights will be on and respective left & pedestrian paths are free for traffic. In Yellow2 Phase only yellow lights will be ON Same flow is repeated for all four paths. (South, west, north, east).

Flowchart:-

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 To implement Traffic Light controller refer the waveform given below

Algorithm is implemented in VHDL with a 13 state Finite State Machine. Refer Fig Below.

Figure 1: State Diagram for Traffic Light Controller

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Abbreviation used:South PSG Pedestrian South Green PSR Pedestrian South Red RS Right South LS Left South SS Straight South YS Yellow South REDS Red South North PNR- Pedestrian North red PNG Pedestrian North green RN Right North LN Left North SN Straight North YN - Yellow North REDN Red North West PWR Pedestrian West Red PWG Pedestrian West Green RW Right West LW Left West SW South West YW Yellow West REDW Red West East PEG Pedestrian East green PER Pedestrian Ease Red RE Right East LE Left East SE Straight East YE Yellow East REDE Red East

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5.2 Experimental Set up:-

Figure 2: Traffic Light Interface to SPARTAN-3 FPGA

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5.3 Component Diagram

CONCLUSION:Design of Traffic Light Controller is implemented on FPGA and is verified using Traffic Light Interface Module according to the following Algorithm.

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5.4 VHDL Code for Traffic Light Controller

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ------------Uncomment the following library declaration if instantiating any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all;

entity traffic_fsm is Port ( clk,rst : in std_logic; ls,lw,ln,le: out std_logic; ss,sw,sn,se : out std_logic; rs,rw,rn,re : out std_logic; red_s,red_w,red_n,red_e : out std_logic; ys,yw,yn,ye : out std_logic; ps_r,pw_r,pn_r,pe_r : out std_logic; ps_g,pw_g,pn_g,pe_g : out std_logic); end traffic_fsm; architecture Behavioral of traffic_fsm is type state is (start,south_g,south_orange,south_r,west_g,west_orange, west_r,east_g,east_orange,east_r,north_g,north_orange,north_r); signal ps , ns : state; signal div : std_logic_vector(30 downto 0); signal clk_s : std_logic; signal cnt : std_logic_vector(3 downto 0) ; begin process(clk,rst) begin if(rst = '1') then div <= (others => '0'); elsif(clk'event and clk = '1') then div <= div + 1; end if; end process; clk_s <= div(21); process(clk_s ,rst) begin if(rst = '1') then cnt <= (others => '0'); elsif(clk_s'event and clk_s = '0') then cnt <= cnt + 1; end if; end process; process(clk_s,rst) begin if (rst = '1')then ps <= start; elsif(clk_s'event and clk_s = '1') then ps <= ns; end if; end process;

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process(ps) begin case ps is when start => ns <= south_g; when south_g => if(cnt = 10)then ns <= south_orange; else ns <= south_g; end if; when south_orange => if(cnt = 14) then ns <= south_r; else ns <= south_orange; end if; when south_r => if(cnt = 15)then ns <= west_g; else ns <= south_r; end if; when west_g => if(cnt = 10) then ns <= west_orange; else ns <= west_g; end if; when west_orange => if(cnt = 14) then ns <= west_r; else ns <= west_orange; end if; when west_r => if(cnt = 15 )then ns <= north_g; else ns <= west_r; end if; when north_g => if(cnt = 10)then ns <= north_orange; else ns <= north_g; end if; when north_orange => if(cnt = 14)then ns <= north_r; else ns <= north_orange; end if; when north_r => if(cnt = 15)then

38

else when

ns <= east_g;

when

when

when end case; end process; process(ps) begin

ns <= north_r; end if; east_g => if(cnt = 10)then ns <= east_orange; else ns <= east_g; end if; east_orange => if(cnt = 14)then ns <= east_r; else ns <= east_orange; end if; east_r => if(cnt = 15)then ns <= south_g; else ns <= east_r; end if; others => ns <= start;

red_s <= '0'; red_w <= '0'; red_n <= '0'; red_e <= '0'; rs <= '0'; rw <= '0'; rn <= '0'; re <= '0'; ss <= '0'; sw <= '0'; sn <= '0'; se <= '0'; ls <= '0'; lw <= '0'; ln <= '0'; le <= '0'; ps_g <= '0'; pw_g <= '0'; pn_g <= '0'; pe_g <= '0'; ys <= '0'; yw <= '0'; yn <= '0'; ye <= '0'; ps_r <= '0'; pw_r <= '0'; pn_r <= '0';

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pe_r <= '0'; case ps is when start => red_s red_w red_n red_e

<= <= <= <=

'1'; '1'; '1'; '1';

when south_g => ls <= '1'; rs <= '1'; ss <= '1'; le <= '1'; red_w <= '1'; red_n <= '1'; red_e <= '1'; ps_r <= '1'; pw_r <= '1'; pn_r <= '1'; pe_r <= '1'; when south_orange => pn_g <= '1'; le <= '1'; ls <= '1'; ys <= '1'; red_w <= '1'; red_n <= '1'; red_e <= '1'; ps_r <= '1'; pw_r <= '1'; pe_r <= '1'; when south_r => ls <= '1'; red_w <= '1'; red_n <= '1'; red_e <= '1'; ps_r <= '1'; pw_r <= '1'; pn_r <= '1'; pe_r <= '1'; when west_g => lw <= '1'; ls <= '1'; rw <= '1'; sw <= '1'; red_s <= '1'; red_n <= '1'; red_e <= '1'; ps_r <= '1'; pw_r <= '1'; pn_r <= '1'; pe_r <= '1'; when west_orange => lw <= '1'; ls <= '1'; pe_g <= '1';

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yw <= '1'; red_s <= '1'; red_n <= '1'; red_e <= '1'; ps_r <= '1'; pw_r <= '1'; pn_r <= '1'; when west_r => lw <= '1'; red_s <= '1'; red_n <= '1'; red_e <= '1'; ps_r <= '1'; pw_r <= '1'; pn_r <= '1'; pe_r <= '1'; when north_g => ln <= '1'; rn <= '1'; sn <= '1'; lw <= '1'; red_s <= '1'; red_w < = '1'; red_e <= '1'; ps_r <= '1'; pw_r <= '1'; pn_r <= '1'; pe_r <= '1'; when north_orange => ln <= '1'; lw <= '1'; ps_g <= '1'; yn <= '1'; red_s <= '1'; red_w <= '1'; red_e <= '1'; pw_r <= '1'; pn_r <= '1'; pe_r <= '1'; when north_r => ln <= '1'; red_s <= '1'; red_w <= '1'; red_e <= '1'; ps_r <= '1'; pw_r <= '1'; pn_r <= '1'; pe_r <= '1'; when east_g re <= se <= le <= ln <= red_s red_w => '1'; '1'; '1'; '1'; <= '1'; <= '1';

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red_n <= '1'; ps_r <= '1'; pw_r <= '1'; pn_r <= '1'; pe_r <= '1'; when east_orange => ln <= '1'; le <= '1'; pw_g <= '1'; ye <= '1'; red_s <= '1'; red_w <= '1'; red_n <= '1'; ps_r <= '1'; pn_r <= '1'; pe_r <= '1'; when east_r => le <= '1'; red_s <= '1'; red_w <= '1'; red_n <= '1'; ps_r <= '1'; pw_r <= '1'; pn_r <= '1'; pe_r <= '1'; when others => red_s <= '0'; red_w <= '0'; red_n <= '0'; red_e <= '0'; rs <= '0'; rw <= '0'; rn <= '0'; re <= '0'; ss <= '0'; sw <= '0'; sn <= '0'; se <= '0'; ls <= '0'; lw <= '0'; ln <= '0'; le <= '0'; ps_g <= '0'; pw_g <= '0'; pn_g <= '0'; pe_g <= '0'; ys <= '0'; yw <= '0'; yn <= '0'; ye <= '0'; ps_r <= '0'; pw_r <= '0'; pn_r <= '0'; pe_r <= '0'; end case;

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end process; end Behavioral;

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--****************************************************** Description of above Code:To Start the Traffic light controller 1. Initially the Red light of all the directions is ON. 2. Traffic starts from the South Direction; hence the green light of South direction goes ON. The signals that are ON, now are : ls ( left south ) 1. rs ( right south ) 1. ss ( straight south ) 1. le ( left east ) 1. red_w ( red west ) 1. red_n (red north ) 1. red_e (red east ) 1. ps_r ( pedestrian south red) 1. pw_r ( pedestrian west red) 1. pn_r ( pedestrian north red) 1. pe_r ( pedestrian east red) 1. Similarly when Orange light of South direction is ON then the signals that are ON, now are ls ( left south ) 1. ys ( yellow south ) 1. le ( left east ) 1. red_w ( red west ) 1. red_n (red north ) 1. red_e (red east ) 1. ps_r ( pedestrian south red) 1. pw_r ( pedestrian west red) 1. pn_r ( pedestrian north red) 1. pe_r ( pedestrian east red) 1. Similarly when Red light of South direction is ON then the signals that are ON, now are ls ( left south ) 1. red_w ( red west ) 1. red_n (red north ) 1. red_e (red east ) 1. ps_r ( pedestrian south red) 1. pw_r ( pedestrian west red) 1. pn_r ( pedestrian north red) 1. pe_r ( pedestrian east red) 1. During this time all ways are Blocked for 1 second except left south ( ls -1 ) and so on. After that it goes clockwise for all Direction (i.e.:- South then West then North then East) similarly.

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CHAPTER 6
Design and Simulation of Pipelined Serial and Parallel Adder
6.1 Design Description:The ripple carry adder is the basis of any other adder structures since it is simply composed of n-bit full adders that are connected in series. The functionality of a full adder can easily be obtained from its truth table, shown in Figure 6. (a), and from which we have the full adder gate level logic functions. For an n-bit ripple carry adder, the block diagram is shown below in Figure 6 (b)

A B

COUT

+
SUM

CIN

+
C OUT

C IN SUM

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C IN 0 1 0 1 0 1 0 1

Sum 0 1 1 0 1 0 0 1
Figure 6(a)

C OUT 0 0 0 1 0 1 1 1

Sum = A + B + CIN Cout = A.B + A.CIN + B.CIN

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Bn

An

B2

A2

B1

A1

B0

A0

Cn

FA
Sn

C3

FA
S2

C2

FA
S1

C1

FA
S0

C0

Figure 6(b) n-bit Ripple Carry Adder (RCA)

6.2 Procedure:Step 1: Step 2: Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Programs Xilinx ISE Project Navigator. In the Project Navigator window go on FILE New projectSelect Device.

Step 3:

Click on symbol of FPGA device and then right click Click on new source Verilog module and give name signed8bitDefine portsFinish. Generate the Behavioral Verilog Code for the multiplier. Check syntax, and remove errors if present. Synthesize the design using XST. Highlight vhd file in the Sources in Project window. To run synthesis, right-click on Synthesize, and choose the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed. A yellow exclamation mark indicates that a warning was generated, and a red cross

Step 4:

46

indicates an error was generated. Warnings are OK.

If there are any errors, you can View Synthesis Report by expanding Synthesis, right-click and choose the View option, otherwise continue on to the next step.

Step 5:

Write User Constraint file wherein the FPGA pins are locked as per the Spartan-II hardware. Running the Xilinx Implementation Tools. Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan2 200k), and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double leftclick on Implement Design. Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bitstream. Double click on Configure Device to download the bitstream. The output can be observed on the output LEDs.

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6.3 VHDL Code for Ripple Carry Adder

************************************************** -- * Pipelined adder structures -- * parameterized pipelining stage -- * ripple carry adder -- ************************************************** library ieee; use ieee.std_logic_1164.all; use work.iscas1.all; use work.par_pkg.all; use work.DFF.all; entity pipeline_rca is port( signal clock : in std_logic; a,b : in std_logic_vector(bit_width-1 downto 0); cin : in std_logic; sum : out std_logic_vector(bit_width-1 downto 0); cout : out std_logic); end pipeline_rca; architecture structural of pipeline_rca is type IARRAY is array (natural range <>) of integer; begin process(clock,a,b,cin) variable low_index, high_index, index : integer; variable temp_sum : std_logic_vector(sumrange); variable temp_cout, temp_cin, regout: std_logic; constant p_level : iarray(0 to 1) :=(4,4); begin temp_cin := cin; low_index := 0; if (clockevent and clock = 1) then for i in p_levellow to p_levelhigh loop index := p_level(i); high_index := (index-1)+low_index; ripple_adder(a(high_index downto low_index), b(high_index downto low_index), temp_cin, temp_sum(high_index downto low_index), temp_cout); reg(clock, temp_cout, regout); low_index := high_index + 1; temp_cin := regout; end loop; sum <= temp_sum; cout<= temp_cout; end if; end process; end structural;

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CHAPTER 7
Design and Simulation of Signed 8 bit Multiplier
7.1 Design Description:Booths algorithm is implemented for multiplying two signed 8-bit numbers. The easiest solution to signed multiplication is to make both the numbers positive and then complement the product. Current Bit 0 0 1 1 Previous Bit 0 1 0 1 ACTION No Arithmetic operation Add multiplicand to the left half of the product Subtract multiplicand from left half of the product No Arithmetic operation

Shift right after each operation. Assume that there is a 0 bit at the right of LSB. Multiply 2 X (- 3) i.e. 0010 X 1101 Iteration 0 1 2 3 4 Step (10) Prod = Prod Mcand Shift right Prod (01) Prod = Prod + Mcand Shift right Prod (10) Prod = Prod Mcand Shift right Prod (11) No operation Shift right Prod Multiplicand 0010 0010 0010 0010 0010 0010 0010 0010 0010 Product 000011010 111011010 111101101 000101101 000010110 111010110 111101011 111101011 111110101

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7.2 Procedure:Step 1: Step 2: Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Programs Xilinx ISE Project Navigator. In the Project Navigator window go on FILE New projectSelect Device.

Step 3:

Click on symbol of FPGA device and then right click Click on new source Verilog module and give name signed8bitDefine portsFinish. Generate the Behavioral Verilog Code for the multiplier. Check syntax, and remove errors if present. Synthesize the design using XST. Highlight signed8bit.v file in the Sources in Project window. To run synthesis, right-click on Synthesize, and choose the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a green check will appear next to Synthesize when it is successfully completed. A yellow exclamation mark indicates that a warning was generated, and a red cross indicates an error was generated. Warnings are OK.

Step 4:

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If there are any errors, you can View Synthesis Report by expanding Synthesis, right-click and choose the View option, otherwise continue on to the next step.

Step 5:

Write User Constraint file wherein the FPGA pins are locked as per the Spartan-II hardware. Running the Xilinx Implementation Tools. Once synthesis is complete, you can place and route your design to fit into a Xilinx device (Spartan2 200k), and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double leftclick on Implement Design.Right-click on Generate Programming File, and choose the Run option, or double left-click on Generate Programming File. This will generate the Bitstream. Double click on Configure Device to download the bitstream. The output can be observed on the output LEDs.

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CHAPTER 8
Study of FPGA Board and Testing on Board LED and Switches
8.1 DIP Switches
The switches connect to an associated FPGA. The switches are used to give input to the FPGA or the design implemented on FPGA. A 4.7K series resistor provides nominal input protection. When in the UP or ON position, a switch connects the FPGA pin to VCCO, a logic High. When DOWN or in the OFF position, the switch connects the FPGA pin to ground, a logic Low. The switches typically exhibit about 2 ms of mechanical bounce and there is no active debouncing circuitry, although such circuitry could easily be added to the FPGA design programmed on the board.

8.2 Key Switches

The Key switches can provide pulse input to the FPGA. The switches connect to an associated FPGA pin. Pressing a key generates logic High on the associated FPGA pin. There is no active debouncing circuitry on the key switches.

8.3 LEDS
Test LEDs are provided for mapping output of FPGA or tracking particular stage in the design. A series current limiting resistor of 270 is associated with every LED. To light an individual LED, drive the associated FPGA control signal High

8.4 VHDL Code for LEDs and Switches

Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity keydis is Port ( rst Clock : in std_logic; : in std_logic;

-- keyboard return and scan lines ret_lin : in std_logic_vector(3 downto 0); scan_lin : out std_logic_vector(3 downto 0); -- display i/os segments and display selects segments : out std_logic_vector(7 downto 0); dis_sel : out std_logic_vector(5 downto 0); -- Input switches and output leds IL : in std_logic_vector(15 downto 0); OL : out std_logic_vector(15 downto 0) ); end keydis; --------------------------------------------------------------architecture Behavioral of keydis is --------------------------------------------------------------signal Divider : std_logic_vector(20 downto 0); signal SClock, DClock, ORed, Interrupt : std_logic; signal Scan, Decoded : std_logic_vector(1 downto 0);

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signal SL_S,D,Display_s : std_logic_vector(3 downto 0); signal segments_s : std_logic_vector(7 downto 0); ---------------------------------------begin ---------Clock Divider---------process(rst, Clock) begin if(rst = '1')then Divider <= (others=>'0'); elsif(Clock'event and Clock = '1')then Divider <= Divider + 1; end if; end process; -----------------Scan & Debounce clock-------------SClock <= Divider(14); DClock <= Divider(11); ------------------Scan Counter---------------------process(SClock, Rst) begin if(Rst = '1')then Scan <= (others=>'0'); elsif(SClock'event and SClock='1')then Scan <= Scan + 1; end if; end process; SL_S <= "0111" "1011" "1101" "1110" when Scan = "00" else when Scan = "01" else when Scan = "10" else ;

scan_lin <= SL_S; ORed <= (not ret_lin(0)) or (not ret_lin(1)) or (not ret_lin(2)) or (not ret_lin(3)); process(Rst,DClock) begin if(Rst = '1')then D <=(others => '0'); elsif(DClock'event and DClock = '1')then D <= D(2 downto 0) & ORed; end if; end process; Interrupt <= '1' when(D = "1111")else '0'; Decoded <= "00" when (ret_lin = "0111") else "01" when (ret_lin = "1011") else "10" when (ret_lin = "1101") else "11"; process(Interrupt, Rst) begin if(Rst = '1')then

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Display_s <= (others=>'0'); elsif(Interrupt'event and Interrupt = '1')then Display_s <= Scan & Decoded; end if; end process; ---------------------------------------------------------------.a. -f| |b -.g. -e| |c -.d. -Segments_s dphgfedcba <= "01000000" when Display_s ="0000" else --0 "01111001" when Display_s ="0001" else --1 "00100100" when Display_s ="0010" else --2 "00110000" when Display_s ="0011" else --3 "00011001" when Display_s ="0100" else --4 "00010010" when Display_s ="0101" else --5 "00000010" when Display_s ="0110" else --6 "01111000" when Display_s ="0111" else --7 "00000000" when Display_s ="1000" else --8 "00010000" when Display_s ="1001" else --9 Display_s Display_s Display_s Display_s Display_s Display_s ="1010" ="1011" ="1100" ="1101" ="1110" ="1111" else else else else else else --A --B --C --D --E --F

"00001000" when "00000011" when "01000110" when "00100001" when "00000110" when "00001110" when "01000000"; Segments <= segments_s;

dis_sel <= (others=>'0'); -- test input switches and output leds OL <= IL;

end Behavioral;

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CHAPTER 9
Testing the Traffic Controller design on the FPGA board
The VHDL code for traffic Controller is as given in Chapter 5. Follow the steps given in chapter two and synthesis the design. Once design is synthesized successfully it is ready to be implemented on FPGA. Step 1: The first step for implementation is to generate constraint file. The constraint file specifies the FPGA pins used for accessing the design.

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Step 2:

To create new UCF file. Right click on the device name and select NEW SOURCE. Select IMPLEMENTATION CONSTRAINT FILE in NEW SOURCE WIZARD and give suitable name for the Project. Click NEXT for the DEFINE MODULE Window.

Implementation Constraints File

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Step 3:

Click on the UCF File (Traffic_Light.ucf) and Select the Edit Constraints (Text). Write the constraint file as shown in figure below.

For implementing your design, from the source window selects Generate Programming File from the drop-down menu.

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Step 4:

Procedure for downloading using iMPACT Boundary Scan Mode 1. Right click on Configure Device (iMPACT) -> and Say RUN or Double click on Configure Device (iMPACT). 2. Right click in workspace and say Initialize chain .The device is seen. 3. Right click on the device and say Program.

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59

If the device is programmed properly, it says Programming Succeeded or else. Programming Failed. The DONE Led glows green if programming succeeds. Note: Before downloading make sure that Protoboard is connected to PC's parallel port with the cable provided and power to the Protoboard is ON

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CHAPTER 10
Real Clock Timer
10.1 Description for Real Clock Timer
Real Clock timer consists of six character multiplexed display working on system clock of 4 MHz. Out of six displays first two (DIS -6 and DIS- 5) are used to display hours, next two (DIS-4 and DIS3) are used to display minutes and last two (DIS -2 and DIS-1) are used to display seconds status. Real time status is displayed on these seven segments by writing a HDL functionality of 6 counters cascaded with each other and decoding its output to seven segment equivalents. HDL functionality also offers a provision for loading the real clock timer with a new value using load signal, when high real clock timer is loaded with new value. Control signal is also provided to set 24 or 12 hour mode of operation, when high 24 hour mode is selected whereas low on control signal selects 12 hour mode of operation.

10.2 VHDL Code for Real Clock Timer

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; -----------------------------------------------------------------------------This is real time clock in this we use --4mhz clock -- to generate 1 sec clock we use enable signal high for last 1 count -- sec1 counter for reading sec -- sec2 counter for reading sec -- min1 counter for reading min -- min2 counter for reading min -- hr1 counter for reading hr -- hr2 counter for reading hr entity realclock is port(reset,clock,load,control:in std_logic; sgout_rg:out std_logic_vector(7 downto 0); dis:out std_logic_vector(5 downto 0)); end realclock; architecture Behavioral of realclock is signal tc,tc1,tc2,tc3,tc4,tc5,tc6,enable:std_logic; signal sec1,sec2,min1,min2,hr1,hr2: std_logic_vector(3 downto 0); signal sec1_rg:std_logic_vector(3 downto 0); signal sec2_rg:std_logic_vector(3 downto 0); signal min1_rg:std_logic_vector(3 downto 0); signal min2_rg:std_logic_vector(3 downto 0); signal hr1_rg:std_logic_vector(3 downto 0); signal hr2_rg:std_logic_vector(3 downto 0); signal pulsegen:std_logic_vector(21 downto 0);

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signal signal signal signal signal

sel:std_logic_vector(2 downto 0); mout:std_logic_vector(3 downto 0); sgout:std_logic_vector(7 downto 0); dis_sig:std_logic_vector(5 downto 0); cnk2:std_logic_vector(2 downto 0);

begin --*************************** Pulse Generator ****************** p0:process(reset,clock,pulsegen) begin if (reset = '1') then pulsegen <= "0000000000000000000000"; elsif rising_edge (clock) then if (pulsegen = "1111010000100100000000") then pulsegen <= "0000000000000000000000"; else pulsegen <= pulsegen + 1; end if; end if; end process; ---------- Enable signal to generate 1-sec pulse for sec1 counter enable <= '1' when pulsegen = "1111010000100100000000" else --enable signal for sec1 counter '0'; --************************ Second_cntr1 ************************* p1:process (reset,clock,sec1_rg,enable,load) begin if (reset = '1') then sec1_rg <= "0000"; elsif load = '1' then sec1_rg <= "0100"; elsif rising_edge(clock) then if (enable = '1') then if (sec1_rg = "1001")then sec1_rg <= "0000"; else sec1_rg <= sec1_rg + 1; end if; end if; end if; sec1 <= sec1_rg; end process ; ------------------tc signal to start sec2 counter--------------------------tc <= '1' when (sec1_rg = "1001") and counter '0'; (enable = '1') else --signal for sec2 --decade counter

--************************* Second_cntr2 *********************** p2:process (reset,clock,sec2_rg,tc,load) --sec2 counter for reading upto 59 sec

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begin if (reset = '1') then sec2_rg <= "0000"; elsif (load = '1') then sec2_rg <= "0100"; elsif rising_edge(clock) then if (tc = '1') then if (sec2_rg = "0101")then sec2_rg <= "0000"; else sec2_rg <= sec2_rg + 1; end if; end if; end if; sec2 <= sec2_rg; end process; -------------------------tc1 signal to start min1 counter------------------tc1 <= '1' when (sec2_rg = "0101") and (tc = '1') else '0' ; --************************ Minute_cntr1 ************************* p3:process(reset,clock,min1_rg,tc1,load) begin if (reset = '1') then min1_rg <= "0000"; elsif load = '1' then min1_rg <= "0100"; elsif rising_edge(clock) then if (tc1 = '1') then if (min1_rg = "1001")then min1_rg <= "0000"; else min1_rg <= min1_rg + 1; end if; end if; end if; min1 <= min1_rg; end process; ------------------------tc2 signal to start min2 counter-------------------tc2 <= '1' when (min1_rg ="1001") and (tc1 = '1') else --pulse for min2 counter '0'; --************************ Minute_cntr2 ************************* p4:process(reset,clock,min2_rg,tc2,load) begin if (reset = '1') then min2_rg <= "0000"; --min2 counter -- min1 counter

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elsif load = '1' then min2_rg <= "0100"; elsif rising_edge(clock) then if (tc2 = '1') then if (min2_rg = "0101")then min2_rg <= "0000"; else min2_rg <= min2_rg + 1; end if; end if; end if; min2 <= min2_rg; end process; --------------------tc3 signal to start hr1 counter------------------------tc3 <= '1' when (min2_rg ="0101") and (tc2 = '1') else '0'; --************************ Hour_cntr1 ************************* p5:process(reset,clock,hr1_rg,tc3,load,control,tc6,tc5) begin if (reset = '1') then hr1_rg <= "0000"; elsif (load = '1') then hr1_rg <= "0001"; elsif rising_edge(clock) then if control = '1' then if (tc5 = '1') then hr1_rg <= "0000"; else if (tc3 = '1') then if (hr1_rg = "1001")then hr1_rg <= "0000"; else hr1_rg <= hr1_rg + 1; end if; end if; end if; else if (tc6 = '1') then hr1_rg <= "0001"; else if (tc3 = '1') then if (hr1_rg = "1001")then hr1_rg <= "0000"; else hr1_rg <= hr1_rg + 1; --hr1 counter

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end if; end if; end if; end if; end if; hr1 <= hr1_rg; end process; ---------------------tc4 signal to start hr2 counter-------------------------tc4 <= '1' when (hr1_rg ="1001") and (tc3 = '1') else '0'; ------------------------tc5 signal to reset at 23:59:59-------------------------tc5 <= '1' when (hr2_rg ="0010")and (hr1_rg ="0011") and (tc3 = '1') else '0'; -----------------------------tc6 signal to reset at 11:59:59--------------tc6 <= '1' when (hr2_rg = "0001") and (hr1_rg = "0010") and (tc3 = '1') else '0'; --************************ Hour_cntr2 ************************* p6:process(reset,clock,hr2_rg,tc4,load,control) begin if (reset = '1') then hr2_rg <= "0000"; elsif load = '1' then hr2_rg <= "0000"; elsif rising_edge(clock) then if (control = '1') then if (tc5 = '1') then hr2_rg <="0000"; else if (tc4 = '1') then if (hr2_rg = "0010")then hr2_rg <= "0000"; else hr2_rg <= hr2_rg + 1; end if; end if; end if; else if (tc6 = '1') then hr2_rg <="0000"; else if (tc4 = '1') then if (hr2_rg = "0001")then hr2_rg <= "0000"; else hr2_rg <= hr2_rg + 1; end if; --hr2 counter

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end if; end if; end if; end if; hr2 <= hr2_rg; end process; p14:process(reset, pulsegen(9)) begin if (reset = '1') then cnk2 <= "000"; elsif rising_edge(pulsegen(9)) then if (cnk2 = "101") then cnk2 <= "000"; else cnk2 <= cnk2 + 1; end if; end if; end process; mout <= sec1 when cnk2 = "000" else sec2 when cnk2 = "001" else min1 when cnk2 = "010" else min2 when cnk2 = "011" else hr1 when cnk2 = "100" else hr2 when cnk2 = "101"; sgout <= "11000000" when mout = "0000" else "11111001" when mout = "0001" else "10100100" when mout = "0010" else "10110000" when mout = "0011" else "10011001" when mout = "0100" else "10010010" when mout = "0101" else "10000010" when mout = "0110" else "11111000" when mout = "0111" else "10000000" when mout = "1000" else "10011000" when mout = "1001" else "11111111" ; dis_sig <= "111110" "111101" "111011" "110111" "101111" "011111" when cnk2 = "000" else when cnk2 = "001" else when cnk2 = "010" else when cnk2 = "011" else when cnk2 = "100" else ;--when cnk2 = "101" ;

sgout_rg <= sgout; dis <= dis_sig; end Behavioral;

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