Thin Film Transistors (TFT)

Navakanta Bhat
Associate Professor ECE Department IISc., Bangalore

Dr. Navakanta Bhat, IISc

Poly-Si Thin Film Transistor

gate electrode poly-Si grains Grain boundary deposited gate oxide n+

n+

Glass / SiO2

ISSUES Deposited gate oxide quality and reliability Grain boundary traps in the channel
Dr. Navakanta Bhat, IISc

Active Matrix Liquid Crystal Display (AMLCD)

Xerox, PARC The substrate should be transparent : glass , quartz

Dr. Navakanta Bhat, IISc

Nickel mediated MILC

- Si deposition and island formation Cap - Si with deposited SiO2 Nickel SiO2 - Si

Open contact holes at the drain side Sputter deposit Nickel in contact holes MILC at 550oC for required time Ni and Si form silicide mix (NiSi2) NiSi2 lowers free energy for -Si to c-Si conversion at NiSi2: -Si interface

c - Si

Dr. Navakanta Bhat, IISc

Hydrogenation to passivate traps

Min Cao, Ph.D. thesis, Stanford Hydrogen plasma or Hydrogen ion implantation can be used Device trans-conductance and current improves significantly
Dr. Navakanta Bhat, IISc

Reliability issue with hydrogenation

N. Bhat, Ph.D. thesis, Stanford Electrons can gain sufficient energy under moderate field Energetic electrons break Si-H bonds, the atomic H results in secondary damage by reacting with Si-H bonds The long term reliabilty degrades with higher hydrogen content
Dr. Navakanta Bhat, IISc

Solid phase re-crystallization

Y. Uemoto, IEEE TED, 1992 CVD amorphous Si deposition at ~ 500oC Re-crystallization anneal at 600oC for 20+ hours Fewer nucleation sites and lower grain boundary traps
Dr. Navakanta Bhat, IISc

CMP of as deposited poly-Si

Surface roughness of as deposited poly-Si

CMP TFT results in performance comparable to SPC TFT with lower thermal budget

Min Cao, Ph.D. thesis, Stanford

Surface roughness after CMP process
Dr. Navakanta Bhat, IISc

Laser recrystallization

Min Cao, Ph.D. thesis, Stanford XeCl laser re-crystallization at low temperature -Si is melted using laser, and is re-grown into poly-Si Low thermal budget, but low throughput
Dr. Navakanta Bhat, IISc

Metal Induced Lateral Crystallization (MILC)

W

n+ gate

Tox
n+ source

Oxide
n+ drain

L
p substrate

current flow from source to drain Can we have a single grain from source drain?
Dr. Navakanta Bhat, IISc

MILC device performance - I

IEEE TED June 2001 Very good electron and hole mobility are obtained
Dr. Navakanta Bhat, IISc

MILC device performance - II

IEEE TED July 2001 MILC device (top) performance with post-MILC anneal at 900oC is comparable to the c-Si SOI device (bottom)
Dr. Navakanta Bhat, IISc

3-D Integrated Circuits

SRAM cell with poly-Si pull up transistor Repeaters for global interconnects using MILC devices Complex logic blocks in 3-D using MILC devices

Dr. Navakanta Bhat, IISc

Interconnect delay in DSM technology

Intrinsic gate delay

Delay

Interconnect delay

0.18

0.25

0.35

0.5

Technology node (m)

Gate delay decreases due to decrease in gate capacitance Interconnect delay increases due to decreasing metal line width and increasing intra-metal coupling capacitance Interconnects are no longer afterthought in DSM technology
Dr. Navakanta Bhat, IISc

Repeaters on multiple layers

Interconnect delay = 0.35 * r * c * L2 r = Resistance per unit length of interconnect c = Capacitance per unit length of interconnect L = Length of the interconnect line 0.35 * r * c * L2 0.35 * r * c * L2/ 4 Repeater
Dr. Navakanta Bhat, IISc

0.35 * r * c * L2 / 4

Complex logic blocks in 3-D

SiO2 First layer SiO2 Silicon Open issues Process: Impact of thermal budget of higher layer device processing on the devices underneath Device: Layout strategy and interconnect routing Circuit: Noise coupling through back gate effect
Dr. Navakanta Bhat, IISc

Second layer

Conclusions
SOI devices are desirable for mainstream VLSI applications SOI wafer cost needs to be decreased New device and circuit design strategies are required to overcome DC floating body effects SOI devices are indispensable in display applications Low thermal budget processes are required to be able to use low cost glass substrates (low strain point glass) Gate oxide and poly-Si substrate quality needs improvement MILC is a promising technique for single grain transistor 3-D VLSI circuits could become reality, provided the process, device, and circuit issues are addressed
Dr. Navakanta Bhat, IISc