7.

Best Practices for the Quartus II TimeQuest Timing Analyzer

December 2010 QII53024-10.1.0 QII53024-10.1.0

Timing constraints and exceptions are vital to all designs that target FPGAs because they allow designers to specify requirements and verify timing of their systems or FPGAs. Constraints and exceptions allow the Fitter to spend more time fitting the critical paths in your design and reduce the amount of time spent on noncritical parts of the design. This chapter provides recommendations on how to fully constrain an FPGA design with the Quartus II TimeQuest Timing Analyzer. The sections are ordered in the recommended flow for applying timing constraints and exceptions in the TimeQuest analyzer. f For more information about interactive timing analysis, refer to the TimeQuest Timing Analyzer Quick Start Tutorial. f For more information about Altera resources available for the TimeQuest analyzer, refer to the TimeQuest Timing Analyzer Resource Center of the Altera website. f For more information about constraining circuits and reporting timing analysis results in the TimeQuest analyzer, including examples, refer to the TimeQuest Design Examples page of the Altera website and the Quartus II TimeQuest Timing Analyzer Cookbook. f For more information about constraints and exceptions supported by the TimeQuest analyzer, refer to the Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II Handbook. h For more information about TimeQuest analyzer Tcl commands and a complete list of commands, refer to ::quartus::sta in Quartus II Help. For more information about standard SDC commands and a complete list of commands, refer to ::quartus::sdc in Quartus II Help. For more information about Altera extensions of SDC commands and a complete list of commands, refer to ::quartus::sdc_ext in Quartus II Help. This chapter contains the following sections:

Creating Clock Requirements on page 72 Creating I/O Requirements on page 75 Creating Timing Exceptions on page 77

2010 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Alteras standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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Chapter 7: Best Practices for the Quartus II TimeQuest Timing Analyzer Creating Clock Requirements

Creating Clock Requirements

The TimeQuest analyzer supports the following types of clocks:

Base clocks Derived clocks Virtual clocks

Clocks are used to specify register-to-register requirements for synchronous transfers and guide the Fitter optimization algorithms to achieve the best possible placement for your design. Specify clock constraints first in Synopsys Design Constraint Files (.sdc) because other constraints may reference previously defined clocks. The TimeQuest analyzer reads SDC constraints and exceptions from top to bottom in the file. f For more information about creating clocks and clock constraints, refer to the Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II Handbook.

Base Clocks
Base clocks are the primary input clocks to the FPGA. Unlike clocks from phase-locked loops (PLLs) that are derived within the FPGA, base clocks are usually generated in off-chip oscillators or forwarded from an external device. Define base clocks first because derived clocks and other constraints can reference the base clocks. Use the create_clock command to constrain all primary input clocks. The target for the create_clock command is usually an FPGA device pin. To specify the FPGA device pin as the target, use the get_ports command. Example 71 shows how to specify a 100-MHz requirement on a clk_sys input clock port.
Example 71. create_clock Command
create_clock -period 10 -name clk_sys [get_ports clk_sys]

You can apply multiple clocks on the same clock node with the -add option. Example 72 shows how to specify that two oscillators drive the same clock port on the FPGA.
Example 72. Two Oscillators Driving the Same Clock Port
create_clock -period 10 -name clk_100 [get_ports clk_sys] create_clock -period 5 -name clk_200 [get_ports clk_sys] -add

h For more information about the create_clock and get_ports commandsincluding full syntax information, options, and example usagerefer to create_clock and get_ports in Quartus II Help.

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Derived Clocks
Derived clocks are generated in the FPGA when you modify the properties, including phase, frequency, offset, and duty cycle, of a source clock signal. Derived clocks, which are PLLs or register clock dividers, are constrained after all base clocks are constrained in the .sdc. Derived clocks capture all clock delays and clock latency where the derived clock target is defined, ensuring that all base clock properties are accounted for in the derived clock. You can use the create_generated_clock command to constrain all generated clocks in your design. The source of the create_generated_clock command should be a node in your design and not a previously constrained clock. Example 73 shows a divide-by-two clock divider.
Example 73. Clock Divider
create_clock -period 10 -name clk_sys [get_ports clk_sys] create_generated_clock -name clk_div_2 -divide_by 2 -source [get_pins reg|clk] [get_pins reg|regout]

Use the create_generated_clock command with the -source option when you specify multiple clock constraints for the same pin in a design. When you use the create_generated_clock command, the -source option should refer to the nearest clock pin of the specified target. Do not use the clock port as the source for a generated clock, because multiple source clocks can feed the clock port. In Example 73, the -source option assigns the clock pin of the register as the source for the generated clock instead of the clock port clk feeding the registers reg clock pin. The TimeQuest analyzer provides the derive_pll_clocks command to automatically generate derived clocks for all PLL clock outputs. The properties of the generated clocks on the PLL outputs match the properties defined for the PLL. h For more information about the create_generated_clock and derive_pll_clocks commandsincluding for full syntax information, options, and example usagerefer to create_generate_clock and derive_pll_clocks in Quartus II Help.

Virtual Clocks
A virtual clock does not have a real source in your design and does not interact directly with your design. You can create virtual clocks with the create_clock command, with no targets specified. Example 74 shows how to create a 10 ns virtual clock.
Example 74. Create Virtual Clock
create_clock -period 10 -name my_virt_clk

If you use the derive_clock_uncertainty command for your design, use virtual clocks with the set_input_delay and set_output_delay commands. It is important to use virtual clocks to allow the TimeQuest analyzer to calculate clock uncertainty separately for I/O interfaces and internal register-to-register paths.

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If an FPGA interfaces with an external device, and both the FPGA and external device have different clock sources, you should model the clock source for the external device with a virtual clock. h For more information about the set_input_delay, set_output_delay, and derive_clock_uncertainty commandsincluding full syntax information, options, and example usagerefer to set_input_delay, set_output_delay, and derive_clock_uncertainty in Quartus II Help. Figure 71 shows a typical I/O interface that contains an FPGA that interfaces with an external device and also shows a virtual clock. Example 75 shows how to create an equivalent virtual clock for each clock in your design that feeds an input or output port.
Figure 71. Design with Virtual Clock
External Device
D reg1 Q

Altera FPGA data_in

D reg1 Q

clk_in

100 MHz

Example 75. Commands to Create Clocks

# Create the base clock for the clock port create_clock period 10 name clk_in [get_ports clk_in] # Create a virtual clock with the same properties of the base clock # driving the source register create_clock period 10 name virt_clk_in # Create the input delay referencing the virtual clock and not the base # clock # DO NOT use set_input_delay clock clk_in <delay_value> # [get_ports data_in] set_input_delay clock virt_clk_in <delay value> [get_ports data_in]

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Figure 72 shows a design that contains an FPGA that interfaces with an external device and also shows the base clock and the virtual clock. Example 76 shows how to create virtual clock for the design.
Figure 72. Design with Base Clock and Virtual Clock
External Device
Dreg1Q

Altera FPGA data_out data_in

Dreg1Q

clk_in

Virtual Clock 50 MHz 100 MHz

Base Clock

Example 76. Commands to Create Clocks

#create base clock for the design create_clock -period 10 -name clk_in [get_ports clk_in] #create the virtual clock for the external register create_clock -period 20 -name virt_clk -waveform {0 10} #set the output delay referencing the virtual clock set_output_delay -clock virt_clk -max 1.5 [get_ports data_out]

Creating I/O Requirements

You should specify timing requirements, including internal and external timing requirements, before you fully analyze a design. With external timing requirements specified, the TimeQuest analyzer verifies the I/O interface, or periphery of the FPGA, against any system specification. The TimeQuest analyzer supports input and output external delay modeling. You should specify I/O requirements after you constrain all clocks in your design. When specifying I/O requirements, reference a virtual clock in the constraints. f For more information about specifying I/O interface requirements and uncertainty, refer to the Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II Handbook.

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Input Constraints
Input constraints allow you to specify all the external delays feeding into the FPGA. Specify input requirements for all input ports in your design. You can use the set_input_delay command to specify external input delay requirements. Use the -clock option to reference a virtual clock. Using a virtual clock allows the TimeQuest analyzer to correctly derive clock uncertainties for interclock and intraclock transfers. The virtual clock defines the launching clock for the input port. The TimeQuest analyzer automatically determines the latching clock inside the device that captures the input data, because all clocks in the device are defined. Figure 73 shows an example of an input delay referencing a virtual clock.
Figure 73. Input Delay
External Device Altera Device

dd tco_ext

cd_ext

Oscillator

cd_altr

Equation 71 shows a typical input delay calculation.

Equation 71. Input Delay Calculation
input delay MAX = cd_ext MIN cd_altr MAX + tco_ext MAX + dd MAX input delay MIN = cd_extMAX cd_altr MIN + tco_ext MIN + dd MIN

Output Constraints
Output constraints allow you to specify all external delays from the FPGA for all output ports in your design. You can use the set_output_delay command to specify external output delay requirements. Use the -clock option to reference a virtual clock. The virtual clock defines the latching clock for the output port. The TimeQuest analyzer automatically determines the launching clock inside the device that launches the output data, because all clocks in the device are defined. Figure 74 shows an example of an output delay referencing a virtual clock.
Figure 74. Output Delay
Altera Device External Device dd cd_ext Oscillator cd_altr

tsu_ext/th_ext

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Equation 72 shows a typical output delay calculation.

Equation 72. output Delay Calculation
input delay MAX = dd MAX tsu_ext + cd_altr MIN cd_ext MAX input delay MIN = ddMIN th_ext + cd_altr MAX cd_ext MIN

h For more information about the set_input_delay and set_output_delay commandsincluding full syntax information, options, and example usagerefer to set_input_delay and set_output_delay in Quartus II Help.

Creating Timing Exceptions

Timing exceptions in the TimeQuest analyzer provide a way to modify the default timing analysis behavior to match the analysis required by your design. Specify timing exceptions after clocks and input and output delay constraints because timing exceptions can modify the default analysis. The TimeQuest analyzer supports the following three major categories of timing exceptions:

False paths Minimum and maximum delays Multicycle paths

f For more information about creating timing exceptions, refer to the Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II Handbook.

False Paths
Specifying a false path in your design removes the path from timing analysis. Use the set_false_path command to specify false paths in your design. You can specify either a point-to-point or clock-to-clock path as a false path. For example, a path you should specify as false path is a static configuration register that is written once during power-up initialization, but does not change state again. Although signals from static configuration registers often cross clock domains, you may not want to make false path exceptions to a clock-to-clock path, because some data may transfer across clock domains. However, you can selectively make false path exceptions from the static configuration register to all endpoints. Example 77 shows how to make false path exceptions from all registers beginning with A to all registers beginning with B.
Example 77. False Path
set_false_path -from [get_pins A*] -to [get_pins B*]

The TimeQuest analyzer assumes all clocks are related unless you specify otherwise. You can use clock groups to make false path exceptions for clock-to-clock timing relationships in your design. Clock groups are a more efficient way to make false path exceptions between clocks, compared to writing multiple set_false_path exceptions between every clock transfer you want to eliminate.

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The TimeQuest analyzer runs more efficiently with clock groups rather than individual false path assignments. Use the set_clock_groups command to collect groups of signals related to each other, and use the -asynchronous option to specify that each group of clocks is asynchronous with each other. If you apply multiple clocks to the same port, use the set_clock_groups command with the -exclusive option to place the clocks into separate groups and declare that the clocks are mutually exclusive. The clocks cannot physically exist in your design at the same time.

h For more information about the set_clock_groups and set_false_path commands including full syntax information, options, and example usagerefer to set_clock_groups and set_false_path in Quartus II Help.

Minimum and Maximum Delays

Specifying minimum and maximum delay constraints in your design creates a bounded minimum and maximum path delay. Use the set_min_delay and set_max_delay commands to create constraints for asynchronous signals that do not have a specific clock relationship in your design, but require a minimum and maximum path delay. You can create minimum and maximum delay exceptions for port-to-port paths through the FPGA without a register stage in the path. If you use minimum and maximum delay exceptions to constrain the path delay, specify both the minimum and maximum delay of the path; do not constrain only the minimum or maximum value. You can also use the set_net_delay command to specify the minimum delay, maximum delay, or skew for any edge in your design when no clock relationships are defined or required. h For more information about the set_min_delay, set_max_delay, and set_net_delay commandsincluding full syntax information, options, and example usagerefer to set_min_delay, set_max_delay, and set_net_delay in Quartus II Help.

Creating Multicycle Exceptions

By default, the TimeQuest analyzer uses single-cycle path analysis. The TimeQuest Timing Analyzer examines all register-to-register paths and performs setup and hold check analysis on those paths. The setup and hold check analysis evaluates the launch and latch edge relationships. When analyzing a path, the TimeQuest analyzer determines the setup launch and latch edge times by finding the closest two active edges in the respective waveforms. When analyzing setup and hold relationships, the TimeQuest analyzer analyzes the path against two timing conditions for every possible setup relationship, not just the worst-case setup relationship; therefore, the hold launch and latch times may be unrelated to the setup launch and latch edges. The TimeQuest analyzer does not report negative setup or hold relationships. When either a negative setup or a negative hold relationship is calculated, the TimeQuest analyzer moves both the launch and latch edges such that the setup and hold relationship becomes positive.

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Multicycle exceptions relax the timing requirements for a register-to-register path, allowing the Fitter to optimally place and route a design in an FPGA. Multicycle exceptions also can reduce compilation time and increase the quality of results. For example, if your design contains a long combinational path in which the latching register does not require data stability on every clock edge, but only on every second clock edge, you can assign a multicycle exception to the path. The multicycle path is dependent on the endpoint registers use of the clock signal. Example 78 shows how to create a multicycle path for the combinational path where the data is stable at the endpoint every two clock cycles of the endpoint latch clock.
Example 78. Multicycle Path
set_multicycle_path -setup 2

If you specify a multicycle path, define both the setup and hold multicycle relationships. For the preceding example, setting data at the endpoint can take two clock cycles and the minimum hold time relationship is defined with a multicycle exception as well. Use the set_multicycle_path command with the -hold option to define the hold relationship. The value of the -hold option is (N 1), where N is equal to the multicycle setup assignment value for a register-to-register path in the same clock domain. However, if data crosses different clock domains, the phase and period of the launch and latch clock may change the default multicycle setup and hold values. If you use multicycle paths that cross different clock domains, you must carefully examine the timing paths in the TimeQuest analyzer before and after applying the multicycle exception to determine if the launch and latch clock edges function as you intend. h For more information about the set_multicycle_path command, including full syntax information, options, and example usage, refer to set_multicycle_path in Quartus II Help.

Multicycle Clock Setup Check and Hold Check Analysis

You can modify the setup and hold relationship when you apply a multicycle exception to a register-to-register path. Figure 75 shows a register-to-register path with various timing parameters labeled.
Figure 75. Register-to-Register Path
REG1
D

REG2
Combinational Logic Tdata
D

SET

SET

Tclk1
CLR

CLR

TCO

Tclk2

TSU / TH

CLK

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Multicycle constraints adjust setup or hold relationships by the specified number of clock cycles based on the source (-start) or destination (-end) clock. An end multicycle setup constraint of two extends the worst-case setup latch edge by one destination clock period. Hold multicycle constraints are based on the hold positionthe default hold position is zero. An end multicycle hold constraint of one effectively subtracts one destination clock period from the default hold latch edge. To specify the multicycle constraints in your design, use the set_multicycle_path command. h For more information about the set_multicycle_path command, including full syntax information, options, and example usage, refer to set_multicycle_path in Quartus II Help. If you specify a multicycle constraint between timing nodes, the multicycle constraint applies only to the path between the two nodes. If you specify a multicycle constraint for a clock, the multicycle constraint applies to all paths where the source node (-from) or destination node (-to) is clocked by the clock. Table 71 summarizes commonly used multicycle assignments.
Table 71. Common Multicycle Assignments Type End Multicycle Setup End Multicycle Hold Start Multicycle Setup Start Multicycle Hold Clock Destination Destination Source Source Timing Check Setup Hold Setup Hold SDC Command set_multicycle_path end setup set_multicycle_path end hold set_multicycle_path start setup set_multicycle_path start -hold

Multicycle Clock Setup

The setup relationship is defined as the number of clock periods between the latch edge and the launch edge. By default, the TimeQuest analyzer performs a single-cycle path analysis, which results in the setup relationship being equal to one clock period (latch edge launch edge). When analyzing a path, the TimeQuest analyzer determines the setup launch and latch edge times by finding the closest two active edges in the respective waveforms. Applying a multicycle setup assignment, increasesor relaxesthe setup relationship by the multicycle setup value.

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For every register-to-register path, the TimeQuest analyzer calculates the setup slack for the path. Equation 73 shows the setup slack calculation.
Equation 73. Setup Slack (1) (2) (3) (4) (5) (6)
setup slack

= = =

data required time data arrival time latch edge + t clk2 t SU launch edge + t clk1 + t CO + t data latch edge launch edge + t clk2 t clk1 t CO + t data + t SU

Notes to Equation 73:

(1) tclk1 = the propagation delay from clock source to clock input on source register (2) tclk2 = the propagation delay from clock source to clock input on destination register (3) tdata = the propagation delay from source register to data input on destination register (4) tCO = the clock to output delay of source register (5) tSU = the setup requirement of destination register (6) tH = the hold requirement of destination register

An end multicycle setup assignment modifies the latch edge of the destination clock by moving the latch edge the specified number of clock periods to the right of the determined default latch edge. Figure 76 shows various values of the end multicycle setup assignment and the resulting latch edge.
Figure 76. End Multicycle Setup Values
-10 0 10 20

REG1.CLK EMS = 3 EMS = 2

EMS = 1 (default)

REG2.CLK

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A start multicycle setup assignment modifies the launch edge of the source clock by moving the launch edge the specified number of clock periods to the left of the determined default launch edge. Figure 77 shows various values of the start multicycle setup assignment and the resulting launch edge.
Figure 77. Start Multicycle Setup Values
-20 -10 0 10 20

Source Clock SMS = 2 SMS = 3 Destination Clock SMS = 1 (default)

Figure 78 shows the setup relationship reported by the TimeQuest analyzer for the negative setup relationship shown in Figure 77.
Figure 78. Start Multicycle Setup Values Reported by the TimeQuest Analyzer
-10 0 10 20

Source Clock

SMS = 1 (default) SMS = 2

SMS = 3

Destination Clock

Multicycle Clock Hold

The hold relationship is defined as the number of clock periods between the launch edge and the latch edge. By default, the TimeQuest analyzer performs a single-cycle path analysis, which results in the hold relationship being equal to one clock period (launch edge latch edge). When analyzing a path, the TimeQuest analyzer performs two hold checks. The first hold check determines that the data launched by the current launch edge is not captured by the previous latch edge. The second hold check determines that the data launched by the next launch edge is not captured by the current latch edge. The TimeQuest analyzer reports only the most restrictive hold check. Equation 74 shows the calculation that the TimeQuest analyzer performs to determine the hold check.
Equation 74. Hold Check
hold check 1 = current launch edge previous latch edge hold check 2 = next launch edge current latch edge

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If a hold check overlaps a setup check, the hold check is ignored. Applying a multicycle hold assignment, increasesor relaxesthe hold slack equation by the number of specified clock cycles. For every register-to-register path, the TimeQuest analyzer calculates the hold slack for the path. Equation 75 shows the hold slack calculation.
Equation 75. Hold Slack (1) (2) (3) (4) (5) (6)
hold slack = data arrival time data required time

= launch edge + t clk1 + t CO + t data latch edge + t clk2 t H = launch edge latch edge t clk2 t clk1 + t CO + t data t H
Notes to Equation 75:
(1) tclk1 = the propagation delay from clock source to clock input on source register (2) tclk2 = the propagation delay from clock source to clock input on destination register (3) tdata = the propagation delay from source register to data input on destination register (4) tCO = the clock to output delay of source register (5) tSU = the setup requirement of destination register (6) tH = the hold requirement of destination register

A start multicycle hold assignment modifies the launch edge of the destination clock by moving the latch edge the specified number of clock periods to the right of the determined default launch edge. Figure 79 shows various values of the start multicycle hold assignment and the resulting launch edge.
Figure 79. Start Multicycle Hold Values
-10 0 10 20

Source Clock

SMH = 0 (default)

SMH = 1

SMH = 1

Destination Clock

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An end multicycle hold assignment modifies the latch edge of the destination clock by moving the latch edge the specific ed number of clock periods to the left of the determined default latch edge. Figure 710 shows various values of the end multicycle hold assignment and the resulting latch edge.
Figure 710. End Multicycle Hold Values
-20 -10 EMH = 2 Source Clock EMH= 0 (default) 0 10 20

EMH = 1 Destination Clock

Figure 711 shows the hold relationship reported by the TimeQuest analyzer for the negative hold relationship shown in Figure 710.
Figure 711. End Multicycle Hold Values Reported by the TimeQuest Analyzer
-10 0 10 20

Source Clock

EMH = 0 default)

EMH = 2

EMH = 1 Destination Clock

Examples of Basic Multicycle Exceptions

This section describes the following examples of combinations of multicycle exceptions:

Default Settings on page 715 End Multicycle Setup = 2 and End Multicycle Hold = 0 on page 717 End Multicycle Setup = 1 and End Multicycle Hold = 1 on page 720 End Multicycle Setup = 2 and End Multicycle Hold = 1 on page 723 Start Multicycle Setup = 2 and Start Multicycle Hold = 0 on page 726 Start Multicycle Setup = 1 and Start Multicycle Hold = 1 on page 729 Start Multicycle Setup = 2 and Start Multicycle Hold = 1 on page 732

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Each example explains how the multicycle exceptions affect the default setup and hold analysis in the TimeQuest analyzer. The multicycle exceptions are applied to a simple register-to-register circuit. Both the source and destination clocks are set to 10 ns.

Default Settings
By default, the TimeQuest analyzer performs a single-cycle analysis to determine the setup and hold checks. Also, by default, the TimeQuest Timing Analyzer sets the end multicycle setup assignment value to one and the end multicycle hold assignment value to zero. Figure 712 shows the source and the destination timing waveform for the source register and destination register, respectively.
Figure 712. Default Timing Diagram
-10 0 Current Launch REG1.CLK 10 20

HC1

SC

HC2

REG2.CLK

1 Current Latch

Equation 76 shows the calculation that the TimeQuest analyzer performs to determine the setup check.
Equation 76. Setup Check
setup check = current latch edge closest previous launch edge

= 10ns 0ns = 10ns

The most restrictive setup relationship with the default single-cycle analysis, that is, a setup relationship with an end multicycle setup assignment of one, is 10 ns.

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Figure 713 shows the setup report for the default setup in the TimeQuest analyzer with the launch and latch edges highlighted.
Figure 713. Setup Report

Equation 77 shows the calculation that the TimeQuest analyzer performs to determine the hold check. Both hold checks are equivalent.
Equation 77. Hold Check
hold check 1 = next launch edge current latch edge

= 0ns 0ns = 0ns

hold check 2 = 10 ns 10 ns

= 0 ns

The most restrictive hold relationship with the default single-cycle analysis, that a hold relationship with an end multicycle hold assignment of zero, is 0 ns.

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Figure 714 shows the hold report for the default setup in the TimeQuest analyzer with the launch and latch edges highlighted.
Figure 714. Hold Report

End Multicycle Setup = 2 and End Multicycle Hold = 0

In this example, the end multicycle setup assignment value is two, and the end multicycle hold assignment value is zero. Example 79 shows the multicycle exceptions applied to the register-to-register design for this example.
Example 79. Multicycle Exceptions
set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_\ dst] -setup -end 2

An end multicycle hold value is not required because the default end multicycle hold value is zero. In this example, the setup relationship is relaxed by a full clock period by moving the latch edge to the next latch edge. The hold analysis is unchanged from the default settings.

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Figure 715 shows the setup timing diagram. The latch edge is a clock cycle later than in the default single-cycle analysis.
Figure 715. Setup Timing Diagram
-10 0 Current Launch REG1.CLK 10 20

SC

REG2.CLK Current Latch

Equation 78 shows the calculation that the TimeQuest analyzer performs to determine the setup check.
Equation 78. Setup Check
setup check = current latch edge closest previous launch edge

= 20 ns 0 ns = 20 ns

The most restrictive setup relationship with an end multicycle setup assignment of two is 20 ns. Figure 716 shows the setup report in the TimeQuest analyzer with the launch and latch edges highlighted.
Figure 716. Setup Report

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Because the multicycle hold latch and launch edges are the same as the results of hold analysis with the default settings, the multicycle hold analysis in this example is equivalent to the single-cycle hold analysis. Figure 717 shows the timing diagram for the hold checks for this example. The hold checks are relative to the setup check. Usually, the TimeQuest analyzer performs hold checks on every possible setup check, not only on the most restrictive setup check edges.
Figure 717. Hold Timing DIagram
-10 0 Current Launch REG1.CLK 10 20

Data

HC1

SC

HC2

REG2.CLK Current Latch

Equation 79 shows the calculation that the TimeQuest analyzer performs to determine the hold check. Both hold checks are equivalent.
Equation 79. Hold Check
hold check 1 = current launch edge previous latch edge

= 0 ns 10 ns = 10 ns
hold check 2 = next launch edge current latch edge

= 10 ns 20 ns = 10 ns

The most restrictive hold relationship with an end multicycle setup assignment value of two and an end multicycle hold assignment value of zero is 10 ns.

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Figure 718 shows the hold report for this example in the TimeQuest analyzer with the launch and latch edges highlighted.
Figure 718. Hold Report

End Multicycle Setup = 1 and End Multicycle Hold = 1

In this example, the end multicycle setup assignment value is one, and the end multicycle hold assignment value is one. Example 710 shows the multicycle exceptions applied to the register-to-register design for this example.
Example 710. Multicycle Exceptions
set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_\ dst] -hold -end 1

An end multicycle setup value is not required because the default end multicycle setup value is one. In this example, the hold relationship is relaxed by one clock period by moving the latch edge to the previous latch edge. The setup analysis is unchanged from the default settings.

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Figure 719 shows the setup timing diagram. The latch edge is the same as the default single-cycle analysis.
Figure 719. Setup Timing Diagram
-10 0 Current Launch 10 20

SRC.CLK

HC1

SC HC2

DST.CLK Current Latch

Equation 710 shows the calculation that the TimeQuest analyzer performs to determine the setup check.
Equation 710. Setup Check
setup check = current latch edge closest previous launch edge

= 10 ns 0 ns = 10 ns

The most restrictive setup relationship with an end multicycle setup assignment of one is 10 ns.

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Figure 720 shows the setup report in the TimeQuest analyzer with the launch and latch edges highlighted.
Figure 720. Setup Report

Figure 721 shows the timing diagram for the hold checks for this example. The hold checks are relative to the setup check.
Figure 721. Hold Timing Diagram
-10 0 Current Launch 10 20

SRC.CLK

HC1

SC HC2

DST.CLK Current Latch

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Equation 711 shows the calculation that the TimeQuest analyzer performs to determine the hold check. Both hold checks are equivalent.
Equation 711. Hold Check
hold check 1 = current launch edge previous latch edge

= 0 ns 10 ns = 10 ns
hold check 2 = next launch edge current latch edge

= 10 ns 0 ns = 10 ns

The most restrictive hold relationship with an end multicycle setup assignment value of one and an end multicycle hold assignment value of one is 10 ns. Figure 722 shows the hold report for this example in the TimeQuest analyzer with the launch and latch edges highlighted.
Figure 722. Hold Report

End Multicycle Setup = 2 and End Multicycle Hold = 1

In this example, the end multicycle setup assignment value is two, and the end multicycle hold assignment value is one. Example 711 shows the multicycle exceptions applied to the register-to-register design for this example.
Example 711. Multicycle Exceptions
set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_dst] -setup -end 2 set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_dst] -hold -end 1

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In this example, the setup relationship is relaxed by two clock periods by moving the latch edge to the left two clock periods. The hold relationship is relaxed by a full period by moving the latch edge to the previous latch edge. Figure 723 shows the setup timing diagram.
Figure 723. Setup Timing Diagram
-10 0 Current Launch 10 20

SRC.CLK

SC

DST.CLK

2 Current Latch

Equation 712 shows the calculation that the TimeQuest analyzer performs to determine the setup check.
Equation 712. Setup Check
setup check = current latch edge closest previous launch edge

= 20 ns 0 ns = 20 ns

The most restrictive hold relationship with an end multicycle setup assignment value of two is 20 ns.

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Figure 724 shows the setup report for this example in the TimeQuest analyzer with the launch and latch edges highlighted.
Figure 724. Setup Report

Figure 725 shows the timing diagram for the hold checks for this example. The hold checks are relative to the setup check.
Figure 725. Hold Timing Diagram
-10 0 Current Launch 10 20

SRC.CLK SC HC1 HC2

DST.CLK Current Latch

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Equation 713 shows the calculation that the TimeQuest analyzer performs to determine the hold check. Both hold checks are equivalent.
Equation 713. Hold Check
hold check 1 = current launch edge previous latch edge

= 0 ns 0 ns = 0 ns
hold check 2 = next launch edge current latch edge

= 10 ns 10 ns = 0 ns

The most restrictive hold relationship with an end multicycle setup assignment value of two and an end multicycle hold assignment value of one is 0 ns. Figure 726 shows the hold report for this example in the TimeQuest analyzer with the launch and latch edges highlighted.
Figure 726. Hold Report

Start Multicycle Setup = 2 and Start Multicycle Hold = 0

In this example, the start multicycle setup assignment value is two, and the start multicycle hold assignment value is zero. Example 712 shows the multicycle exceptions applied to the register-to-register design for this example.
Example 712. Multicycle Exceptions
set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_\ dst] -setup -start 2

A start multicycle hold value is not required because the default start multicycle hold value is zero.

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In this example, the setup relationship is relaxed by moving the latch edge to the left two clock periods. Hold analysis is unchanged from the default settings. Figure 727 shows the setup timing diagram.
Figure 727. Setup TIming Diagram
-10 Current Launch REG1.CLK 2 0 10 20

SC

REG2.CLK Current Latch

Equation 714 shows the calculation that the TimeQuest analyzer performs to determine the setup check.
Equation 714. Setup Check
setup check = current latch edge closest previous launch edge

= 10 ns 10 ns = 20 ns

The most restrictive hold relationship with a start multicycle setup assignment value of two is 20 ns.

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Figure 728 shows the setup report for this example in the TimeQuest analyzer with the launch and latch edges highlighted.
Figure 728. Setup Report

Because the multicycle hold latch and launch edges are the same as the results of hold analysis with the default settings, the multicycle hold analysis in this example is equivalent to the single-cycle hold analysis. Figure 729 shows the timing diagram for the hold checks for this example.
Figure 729. Hold TIming Diagram
-10 Current Launch REG1.CLK 0 10 20

HC1

SC

HC2

REG2.CLK Current Latch

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Equation 715 shows the calculation that the TimeQuest analyzer performs to determine the hold check. Both hold checks are equivalent.
Equation 715. Hold Check
hold check 1 = current launch edge previous latch edge

= 0 ns 10 ns = 10 ns
hold check 2 = next launch edge current latch edge

= 10 ns 0 ns = 10 ns

The most restrictive hold relationship with a start multicycle setup assignment value of two and a start multicycle hold assignment value of zero is 10 ns. Figure 730 shows the hold report for this example in the TimeQuest analyzer with the launch and latch edges highlighted.
Figure 730. Hold Report

Start Multicycle Setup = 1 and Start Multicycle Hold = 1

In this example, the start multicycle setup assignment value is one, and the start multicycle hold assignment value is one. Example 713 shows the multicycle exceptions applied to the register-to-register design for this example.
Example 713. Multicycle Exceptions
set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_\ dst] -hold -start 1

A start multicycle setup value is not required, because the default start multicycle hold value is one.

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In this example, the hold relationship is relaxed by one clock period by moving the launch edge to the left. Figure 731 shows the setup timing diagram.
Figure 731. Setup Timing Diagram
-10 0 Current Launch 1 10 20

REG1.CLK

SC

REG2.CLK Current Latch

Equation 716 shows the calculation that the TimeQuest analyzer performs to determine the setup check.
Equation 716. Setup Check
setup check = current latch edge closest previous launch edge

= 10 ns 0 ns = 10 ns

The most restrictive setup relationship with a start multicycle setup assignment of one is 10 ns. Figure 732 shows the setup report in the TimeQuest analyzer with the launch and latch edges highlighted.
Figure 732. Setup Report

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Figure 733 shows the timing diagram for the hold checks for this example. The hold checks are relative to the setup check.
Figure 733. Hold Timing Diagram
-10 Current Launch REG1.CLK 0 10 20

HC1

SC

HC2

REG2.CLK Current Latch

Equation 717 shows the calculation that the TimeQuest analyzer performs to determine the hold check. Both hold checks are equivalent.
Equation 717. Hold Check
hold check 1 = current launch edge previous latch edge

= 10 ns 0 ns = 10 ns
hold check 2 = next launch edge current latch edge

= 20 ns 10 ns = 10 ns

The most restrictive hold relationship with a start multicycle setup assignment value of one and a start multicycle hold assignment value of one is 10 ns.

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Figure 734 shows the hold report for this example in the TimeQuest analyzer with the launch and latch edges highlighted.
Figure 734. Hold Report

Start Multicycle Setup = 2 and Start Multicycle Hold = 1

In this example, the start multicycle setup assignment value is two, and the start multicycle hold assignment value is one. Example 714 shows the multicycle exceptions applied to the register-to-register design for this example.
Example 714. Multicycle Exceptions
set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_dst] -setup -start 2 set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_dst] -hold -start 1

In this example, the setup relationship is relaxed by two clock periods by moving the launch edge to the left two clock periods. Figure 735 shows the setup timing diagram.
Figure 735. Setup Timing Diagram
-10 0 10 20

SRC.CLK

SC (default) (

Data

SC

DST.CLK

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Equation 718 shows the calculation that the TimeQuest analyzer performs to determine the setup check.
Equation 718. Setup Check
setup check = current latch edge closest previous launch edge

= 10 ns 10 ns = 20 ns

The most restrictive hold relationship with a start multicycle setup assignment value of two is 20 ns. Figure 736 shows the setup report for this example in the TimeQuest analyzer with the launch and latch edges highlighted.
Figure 736. Setup Report

Figure 737 shows the timing diagram for the hold checks for this example. The hold checks are relative to the setup check.
Figure 737. Hold Timing Diagram
-10 0 Current Launch 10 20

SRC.CLK HC1 SC HC2

DST.CLK Current Latch

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Equation 719 shows the calculation that the TimeQuest analyzer performs to determine the hold check. Both hold checks are equivalent.
Equation 719. Hold Check
hold check 1 = current launch edge previous latch edge

= 0 ns 0 ns = 0 ns
hold check 2 = next launch edge current latch edge

= 10 ns 10 ns = 0 ns

The most restrictive hold relationship with a start multicycle setup assignment value of two and a start multicycle hold assignment value of one is 0 ns. Figure 738 shows the hold report for this example in the TimeQuest analyzer with the launch and latch edges highlighted.
Figure 738. Hold Report

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Application of Multicycle Exceptions

This section shows the following examples of applications of multicycle exceptions:

Same Frequency Clocks with Destination Clock Offset on page 735 The Destination Clock Frequency is a Multiple of the Source Clock Frequency on page 737 The Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset on page 740 The Source Clock Frequency is a Multiple of the Destination Clock Frequency on page 742 The Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset on page 745

Each example explains how the multicycle exceptions affect the default setup and hold analysis in the TimeQuest analyzer. All of the examples are between related clock domains. If your design contains related clocks, such as PLL clocks, and paths between related clock domains, you can apply multicycle constraints.

Same Frequency Clocks with Destination Clock Offset

In this example, the source and destination clocks have the same frequency, but the destination clock is offset with a positive phase shift. Both the source and destination clocks have a period of 10 ns. The destination clock has a positive phase shift of 2 ns with respect to the source clock. Figure 739 shows an example of a design with same frequency clocks and a destination clock offset.
Figure 739. Same Frequency Clocks with Destination Clock Offset
REG1 In clk0 clk1
D

REG2
Combinational Logic
D

SET

SET

Out

CLR

CLR

Figure 740 shows the timing diagram for default setup check analysis performed by the TimeQuest analyzer.
Figure 740. Setup Timing Diagram
-10 0 Launch 10 20

REG1.CLK

SC REG2.CLK 1 Latch 2

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Equation 720 shows the calculation that the TimeQuest analyzer performs to determine the setup check.
Equation 720. Setup Check
setup check = current latch edge closest previous launch edge

= 2 ns 0 ns = 2 ns

The setup relationship shown in Figure 740 is too pessimistic and is not the setup relationship required for typical designs. To correct the default analysis, you must use an end multicycle setup exception of two. Example 715 shows the multicycle exception used to correct the default analysis in this example.
Example 715. Multicycle Exceptions
set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_dst] -setup -end 2

Figure 741 shows the timing diagram for the preferred setup relationship for this example.
.

Figure 741. Preferred Setup Relationship

-10 0 Launch 10 20

REG1.CLK

SC

REG2.CLK

2 Latch

Figure 742 shows the timing diagram for default hold check analysis performed by the TimeQuest analyzer with an end multicycle setup value of two.
Figure 742. Default Hold Check
-10 0 Current Launch 10 20

REG1.CLK

HC1

SC

HC2

REG2.CLK Current Latch

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Equation 721 shows the calculation that the TimeQuest analyzer performs to determine the hold check.
Equation 721. Hold Check
hold check 1 = current launch edge previous latch edge

= 0 ns 2 ns = 2 ns
hold check 2 = next launch edge current latch edge

= 10 ns 12 ns = 2 ns

In this example, the default hold analysis returns the preferred hold requirements and no multicycle hold exceptions are required. Figure 743 shows the associated setup and hold analysis if the phase shift is 2 ns. In this example, the default hold analysis is correct for the negative phase shift of 2 ns, and no multicycle exceptions are required.
Figure 743. Negative Phase Shift
-10 0 Current Launch 10 20

REG1.CLK

HC1

SC

HC2

REG2.CLK Current Latch

The Destination Clock Frequency is a Multiple of the Source Clock Frequency

In this example, the destination clock frequency value of 5 ns is an integer multiple of the source clock frequency of 10 ns. The destination clock frequency can be an integer multiple of the source clock frequency when a PLL is used to generate both clocks with a phase shift applied to the destination clock. Figure 744 shows an example of a design where the destination clock frequency is a multiple of the source clock frequency.
Figure 744. Destination Clock is Multiple of Source Clock
REG1 In clk0 clk clk1
CLR CLR D

REG2
Combinational Logic
D

SET

SET

Out

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Figure 745 shows the timing diagram for default setup check analysis performed by the TimeQuest analyzer.
Figure 745. Setup Timing Diagram
-10 0 Launch REG1.CLK 10 20

SC

REG2.CLK

2 Latch

Equation 722 shows the calculation that the TimeQuest analyzer performs to determine the setup check.
Equation 722. Setup Check
setup check = current latch edge closest previous launch edge

= 5 ns 0 ns = 5 ns

The setup relationship shown in Figure 745 demonstrates that the data does not need to be captured at edge one, but can be captured at edge two; therefore, you can relax the setup requirement. To correct the default analysis, you must shift the latch edge by one clock period with an end multicycle setup exception of two. Example 716 shows the multicycle exception used to correct the default analysis in this example.
Example 716. Multicycle Exceptions
set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_dst] -setup -end 2

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Figure 746 shows the timing diagram for the preferred setup relationship for this example.
Figure 746. Preferred Setup Analysis
-10 0 Launch REG1.CLK 10 20

SC

REG2.CLK

2 Latch

Figure 747 shows the timing diagram for default hold check analysis performed by the TimeQuest analyzer with an end multicycle setup value of two.
Figure 747. Default Hold Check
-10 0 Current Launch 10 20

REG1.CLK

SC HC1

HC2

REG2.CLK Current Latch

Equation 723 shows the calculation that the TimeQuest analyzer performs to determine the hold check.
Equation 723. Hold Check
hold check 1 = current launch edge previous latch edge

= 0 ns 5 ns = 5 ns
hold check 2 = next launch edge current latch edge

= 10 ns 10 ns = 0 ns

In this example, hold check one is too restrictive. The data is launched by the edge at 0 ns and should check against the data captured by the previous latch edge at 0 ns, which does not occur in hold check one. To correct the default analysis, you must use an end multicycle hold exception of one.

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The Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset
This example is a combination of the previous two examples. The destination clock frequency is an integer multiple of the source clock frequency and the destination clock has a positive phase shift. The destination clock frequency is 5 ns and the source clock frequency is 10 ns. The destination clock also has a positive offset of 2 ns with respect to the source clock. The destination clock frequency can be an integer multiple of the source clock frequency with an offset when a PLL is used to generate both clocks with a phase shift applied to the destination clock. Figure 748 shows an example of a design in which the destination clock frequency is a multiple of the source clock frequency with an offset.
Figure 748. Destination Clock is Multiple of Source Clock with Offset
REG1 In clk0 clk clk1
CLR CLR D

REG2
Combinational Logic
D

SET

SET

Out

Figure 749 shows the timing diagram for default setup check analysis performed by the TimeQuest analyzer.
Figure 749. Setup Timing Diagram
-10 0 Launch REG1.CLK 10 20

SC

REG2.CLK

1 Latch

Equation 724 shows the calculation that the TimeQuest analyzer performs to determine the setup check.
.

Equation 724. Setup Check

setup check = current latch edge closest previous launch edge

= 2 ns 0 ns = 2 ns

The setup relationship shown in Figure 749 demonstrates that the data does not need to be captured at edge one, but can be captured at edge two; therefore, you can relax the setup requirement. To correct the default analysis, you must shift the latch edge by one clock period with an end multicycle setup exception of three.

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Example 717 shows the multicycle exception used to correct the default analysis in this example.
Example 717. Multicycle Exceptions
set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_dst] -setup -end 3

Figure 750 shows the timing diagram for the preferred setup relationship for this example.
Figure 750. Preferred Setup Analysis
-10 0 Launch REG1.CLK 10 20

SC

REG2.CLK

3 Latch

Figure 751 shows the timing diagram for default hold check analysis performed by the TimeQuest analyzer with an end multicycle setup value of three.
Figure 751. Default Hold Check
-10 0 Current Launch 10 20

REG1.CLK

SC HC1

HC2

REG2.CLK Current Latch

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Equation 725 shows the calculation that the TimeQuest analyzer performs to determine the hold check.
Equation 725. Hold Check
hold check 1 = current launch edge previous latch edge

= 0 ns 5 ns = 5 ns
hold check 2 = next launch edge current latch edge

= 10 ns 10 ns = 0 ns

In this example, hold check one is too restrictive. The data is launched by the edge at 0 ns and should check against the data captured by the previous latch edge at 2 ns, which does not occur in hold check one. To correct the default analysis, you must use an end multicycle hold exception of one.

The Source Clock Frequency is a Multiple of the Destination Clock Frequency

In this example, the source clock frequency value of 5 ns is an integer multiple of the destination clock frequency of 10 ns. The source clock frequency can be an integer multiple of the destination clock frequency when a PLL is used to generate both clocks and different multiplication and division factors are used. Figure 752 shows an example of a design where the source clock frequency is a multiple of the destination clock frequency.
Figure 752. Source Clock Frequency is Multiple of Destination Clock Frequency
REG1 In clk0 clk clk1
CLR CLR D

REG2
Combinational Logic
D

SET

SET

Out

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Figure 753 shows the timing diagram for default setup check analysis performed by the TimeQuest analyzer.
Figure 753. Default Setup Check Analysis
-10 0 Launch REG1.CLK 2 1 10 20

SC

REG2.CLK Latch

Equation 726 shows the calculation that the TimeQuest analyzer performs to determine the setup check.
Equation 726. Setup Check
setup check = current latch edge closest previous launch edge

= 10 ns 5 ns = 5 ns

The setup relationship shown in Figure 753 demonstrates that the data launched at edge one does not need to be captured, and the data launched at edge two must be captured; therefore, you can relax the setup requirement. To correct the default analysis, you must shift the launch edge by one clock period with a start multicycle setup exception of two. Example 718 shows the multicycle exception used to correct the default analysis in this example.
Example 718. Multicycle Exceptions
set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_dst] -setup -start 2

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Figure 754 shows the timing diagram for the preferred setup relationship for this example.
Figure 754. Preferred Setup Check Analysis
-10 0 Launch REG1.CLK 2 1 10 20

SC

REG2.CLK Latch

Figure 755 shows the timing diagram for default hold check analysis performed by the TimeQuest analyzer with a start multicycle setup value of two.
Figure 755. Default Hold Check
-10 0 Current Launch 10 20

REG1.CLK

HC1

SC

HC2

REG2.CLK Current Latch

Equation 727 shows the calculation that the TimeQuest analyzer performs to determine the hold check.
.

Equation 727. Hold Check

hold check 1 = current launch edge previous latch edge

= 0 ns 0 ns = 0 ns
hold check 2 = next launch edge current latch edge

= 5 ns 10 ns = 5 ns

In this example, hold check two is too restrictive. The data is launched next by the edge at 10 ns and should check against the data captured by the current latch edge at 10 ns, which does not occur in hold check two. To correct the default analysis, you must use a start multicycle hold exception of one.

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The Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
In this example, the source clock frequency is an integer multiple of the destination clock frequency and the destination clock has a positive phase offset. The source clock frequency is 5 ns and destination clock frequency is 10 ns. The destination clock also has a positive offset of 2 ns with respect to the source clock. The source clock frequency can be an integer multiple of the destination clock frequency with an offset when a PLL is used to generate both clocks, different multiplication and division factors are used, and a phase shift applied to the destination clock. Figure 756 shows an example of a design where the source clock frequency is a multiple of the destination clock frequency with an offset.
Figure 756. Source Clock Frequency is Multiple of Destination Clock Frequency with Offset
REG1 In clk0 clk clk1
CLR CLR D

REG2
Combinational Logic
D

SET

SET

Out

Figure 757 shows the timing diagram for default setup check analysis performed by the TimeQuest analyzer.
Figure 757. Setup Timing Diagram
-10 0 10 Launch REG1.CLK 3 2 1 20

REG2.CLK Latch

Equation 728 shows the calculation that the TimeQuest analyzer performs to determine the setup check.
.

Equation 728. setup Check

setup check = current latch edge closest previous launch edge

= 12 ns 10 ns = 2 ns

The setup relationship shown in Figure 757 demonstrates that the data is not launched at edge one, and the data that is launched at edge three must be captured; therefore, you can relax the setup requirement. To correct the default analysis, you must shift the launch edge by two clock periods with a start multicycle setup exception of three.

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Example 719 shows the multicycle exception used to correct the default analysis in this example.
Example 719. Multicycle Exceptions
set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_dst] -setup -start 3

Figure 758 shows the timing diagram for the preferred setup relationship for this example.
Figure 758. Preferred Setup Check Analysis
-10 0 Launch REG1.CLK 3 2 1 10 20

SC

REG2.CLK Latch

Figure 759 shows the timing diagram for default hold check analysis performed by the TimeQuest analyzer with a start multicycle setup value of three.
Figure 759. Default Hold Check Analysis
-10 0 Current Launch 10 20

REG1.CLK

HC2 HC1 SC

REG2.CLK Current Latch

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Equation 729 shows the calculation that the TimeQuest analyzer performs to determine the hold check.
Equation 729. Hold Check
hold check 1 = current launch edge previous latch edge

= 0 ns 2 ns = 2 ns
hold check 2 = next launch edge current latch edge

= 5 ns 12 ns = 7 ns

In this example, hold check two is too restrictive. The data is launched next by the edge at 10 ns and should check against the data captured by the current latch edge at 12 ns, which does not occur in hold check two. To correct the default analysis, you must use a start multicycle hold exception of one.

Document Revision History

Table 72 shows the revision history for this chapter.
Table 72. Document Revision History Date Version

Changes Changed to new document template. Edited document and linked to other resources. Added information that previously appeared in Application Note 481: Applying Multicycle Exceptions in the TimeQuest Timing Analyzer. Added example to Derived Clocks on page 73. Updated Base Clocks on page 72.

December 2010

10.1.0

July 2010 November 2009 March 2009

10.0.0 9.1.0 9.0.0

Minor editorial changes to document. No updates to technical content.

Initial release.

f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook Archive. f Take an online survey to provide feedback about this handbook chapter.

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