TLC555, TLC555Y LinCMOS TIMERS

SLFS043C SEPTEMBER 1983 REVISED SEPTEMBER 1997

D D D D D D D D D

Very Low Power Consumption 1 mW Typ at VDD = 5 V Capable of Operation in Astable Mode CMOS Output Capable of Swinging Rail to Rail High Output-Current Capability Sink 100 mA Typ Source 10 mA Typ Output Fully Compatible With CMOS, TTL, and MOS Low Supply Current Reduces Spikes During Output Transitions Single-Supply Operation From 2 V to 15 V Functionally Interchangeable With the NE555; Has Same Pinout ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015.2

D, DB, JG, P, OR PW PACKAGE (TOP VIEW)

GND TRIG OUT RESET

1 2 3 4

8 7 6 5

VDD DISCH THRES CONT

FK PACKAGE (TOP VIEW)

NC TRIG NC OUT NC

4 5 6 7 8

3 2 1 20 19 18 17 16 15 14 9 10 11 12 13

NC GND NC VDD NC NC DISCH NC THRES NC NC RESET NC

Copyright 1997, Texas Instruments Incorporated

description

The TLC555 is a monolithic timing circuit fabricated using the TI LinCMOS process. The NC No internal connection timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Because of its high input impedance, this device uses smaller timing capacitors than those used by the NE555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power supply voltage. Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and GND. All unused inputs should be tied to an appropriate logic level to prevent false triggering. While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC555 exhibits greatly reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling capacitors required by the NE555. The TLC555C is characterized for operation from 0C to 70C. The TLC555I is characterized for operation from 40C to 85C. The TLC555M is characterized for operation over the full military temperature range of 55C to 125C.

This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either supply voltage or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.

LinCMOS is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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CONT NC

TLC555, TLC555Y LinCMOS TIMERS

SLFS043C SEPTEMBER 1983 REVISED SEPTEMBER 1997

AVAILABLE OPTIONS PACKAGED DEVICES TA 0C to 70C 40C to 85C 55C to 125C VDD RANGE 2 V to 15 V 3 V to 15 V 5 V to 15 V SMALL OUTLINE (D) TLC555CD TLC555ID TLC555MD SSOP (DB) TLC555CDBLE CHIP CARRIER (FK) TLC555MFK CERAMIC DIP (JG) TLC555MJG PLASTIC DIP (P) TLC555CP TLC555IP TLC555MP TSSOP (PW) TLC555CPWLE TLC555Y CHIP FORM (Y)

The D package is available taped and reeled. Add the R suffix to device type (e.g., TLC555CDR). The DB and PW packages are only available left-end taped and reeled (indicated by the LE suffix on the device type; e.g., TLC555CDBLE). Chips are tested at 25C. FUNCTION TABLE RESET VOLTAGE <MIN >MAX >MAX >MAX TRIGGER VOLTAGE Irrelevant <MIN >MAX >MAX THRESHOLD VOLTAGE Irrelevant Irrelevant >MAX <MIN OUTPUT L H L DISCHARGE SWITCH On Off On

As previously established

For conditions shown as MIN or MAX, use the appropriate value specified under electrical characteristics.

functional block diagram

CONT 5 VDD 8 R THRES 6 R1 3 R S R 1 OUT RESET 4

TRIG

2 R 7 1 GND DISCH

Pin numbers are for all packages except the FK package. RESET can override TRIG, which can override THRES.

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SLFS043C SEPTEMBER 1983 REVISED SEPTEMBER 1997

TLC555Y chip information

This chip, when properly assembled, displays characteristics similar to the TLC555. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS CONT VDD (5) (8) THRES (6) R RESET (4)

R1 R S 1

(3)

OUT

50 (2)

R TRIG

R (1) GND 64

(7)

DISCH

RESET can override TRIG, which can override THRES. CHIP THICKNESS: 15 TYPICAL BONDING PADS: 4 4 MINIMUM TJmax = 150C TOLERANCES ARE 10%. ALL DIMENSIONS ARE IN MILS. PIN (1) IS INTERNALLY CONNECTED TO BACKSIDE OF CHIP.

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Template Release Date: 71194

TLC555, TLC555Y LinCMOS TIMERS

SLFS043C SEPTEMBER 1983 REVISED SEPTEMBER 1997

DISCH

V DD

COMPONENT COUNT

Transistors Resistors

39 5

OUT

GND TRIG RESET

equivalent schematic (each channel)

THRES

CONT

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TLC555, TLC555Y LinCMOS TIMERS

SLFS043C SEPTEMBER 1983 REVISED SEPTEMBER 1997

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 to VDD Sink current, discharge or output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA Source current, output, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA: C-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C I-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40C to 85C M-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55C to 125C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package . . . . . . . . . . . . . . . . . . . . 300C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, DB, P, or PW package . . . . . . . . 260C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to network GND. DISSIPATION RATING TABLE PACKAGE D DB FK JG P PW TA 25C POWER RATING 725 mW 525 mW 1375 mW 1050 mW 1000 mW 525 mW DERATING FACTOR ABOVE TA = 25C 5.8 mW/C 4.2 mW/C 11.0 mW/C 8.4 mW/C 8.0 mW/C 4.2 mW/C TA = 70C POWER RATING 464 mW 336 mW 880 mW 672 mW 640 mW 336 mW TA = 85C POWER RATING 377 mW 273 mW 715 mW 546 mW 520 mW 273 mW TA = 125C POWER RATING 145 mW 105 mW 275 mW 210 mW 200 mW 105 mW

recommended operating conditions

MIN Supply voltage, VDD TLC555C Operating free-air temperature range, TA TLC555I TLC555M 2 0 40 55 MAX 15 70 85 125 C UNIT V

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electrical characteristics at specified free-air temperature, VDD = 2 V for TLC555C, VDD = 3 V for TLC555I
PARAMETER VIT IIT VI(TRIG) II(TRIG) VI(RESET) II(RESET) Threshold voltage Threshold current Trigger voltage Trigger current Reset voltage Reset current Control voltage (open circuit) as a percentage of supply voltage Discharge switch on-stage g g voltage Discharge switch off-stage g g current VOH VOL IDD High-level High level output voltage Low-level Low level output voltage Supply current IOH = 300 A IOL = 1 mA See Note 2 IOL = 1 mA TEST CONDITIONS TA 25C Full range 25C MAX 25C Full range 25C MAX 25C Full range 25C MAX MAX 25C Full range 25C MAX 25C Full range 25C Full range 25C Full range 1.5 1.5 0.07 0.3 0.35 250 400 0.1 0.5 1.9 1.5 2.5 0.07 0.3 0.4 250 500 0.4 0.3 10 75 66.7% 0.03 0.2 0.25 0.1 120 1.9 0.4 0.3 10 75 1.1 1.5 2 0.4 0.3 10 150 66.7% 0.03 0.2 0.375 V nA V V A TLC555C MIN 0.95 0.85 10 75 0.67 0.95 1.05 0.71 0.61 10 150 1.1 1.5 1.8 TYP 1.33 MAX 1.65 1.75 MIN 1.6 1.5 10 150 1 1.29 1.39 TLC555I TYP MAX 2.4 2.5 UNIT V pA V pA V pA

Full range is 0C to 70C for the TLC555C and 40C to 85C for the TLC555I. For conditions shown as MAX, use the appropriate value specified in the recommended operating conditions table. NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.

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electrical characteristics at specified free-air temperature, VDD = 5 V

PARAMETER TEST CONDITIONS TA 25C Full range Threshold current 25C MAX Trigger voltage 25C Full range Trigger current 25C MAX Reset voltage 25C Full range Reset current Control voltage (open circuit) as a percentage of supply voltage Discharge switch g on-state voltage Discharge switch g off-state current VOH High-level output g voltage IOH = 1 mA IOL = 10 mA 25C MAX 0.4 0.3 10 75 1.36 1.26 10 75 1.1 1.5 1.8 0.4 0.3 10 150 TLC555C MIN 2.8 2.7 10 75 1.66 1.96 2.06 1.36 1.26 10 150 1.1 1.5 1.8 0.4 0.3 10 5000 TYP 3.3 MAX 3.8 3.9 MIN 2.8 2.7 10 150 1.66 1.96 2.06 1.36 1.26 10 5000 1.1 1.5 1.8 pA V TLC555I TYP 3.3 MAX 3.8 3.9 MIN 2.8 2.7 10 5000 1.66 1.96 2.06 pA V TLC555M TYP 3.3 MAX 3.8 3.9 pA UNIT

VIT
IIT VI(TRIG)

Threshold voltage

II(TRIG)

VI(RESET)

II(RESET)

MAX

66.7%

66.7%

66.7%

25C Full range 25C MAX 25C Full range 25C Full range 25C Full range 25C Full range 25C Full range 4.1 4.1

0.14

0.5 0.6

0.14

0.5 0.6

0.14

0.5 0.6

0.1 0.5 4.8 4.1 4.1 0.21 0.4 0.5 0.13 0.3 0.4 0.08 0.3 0.35 170 350 500

0.1 120 4.8 4.1 4.1 0.21 0.4 0.5 0.13 0.3 0.4 0.08 0.3 0.35 170 350 600

0.1 120 4.8

nA

V 0.4 0.6

IOL = 8 mA Low-level output voltage

0.21

VOL

IOL = 5 mA

0.13

0.3 0.45

IOL = 3 2 mA 3.2

0.08

0.3 0.4

IDD

Supply current

See Note 2

170

350 700

Full range is 0C to 70C the for TLC555C, 40C to 85C for the TLC555I, and 55C to 125C for the TLC555M. For conditions shown as MAX, use the appropriate value specified in the recommended operating conditions table. NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG.

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SLFS043C SEPTEMBER 1983 REVISED SEPTEMBER 1997

electrical characteristics at specified free-air temperature, VDD = 15 V

PARAMETER TEST CONDITIONS TA 25C Full range Threshold current 25C MAX Trigger voltage 25C Full range Trigger current 25C MAX Reset voltage 25C Full range Reset current Control voltage (open circuit) as a percentage of supply voltage Discharge switch g on-state voltage Discharge switch g off-state current IOH = 10 mA VOH High-level output g voltage IOH = 5 mA IOH = 1 mA IOL = 100 mA VOL Low-level output voltage IOL = 50 mA IOL = 10 mA IDD Supply current See Note 2 IOL = 100 mA 25C MAX 0.4 0.3 10 75 4.65 4.55 10 75 1.1 1.5 1.8 0.4 0.3 10 150 TLC555C MIN 9.45 9.35 10 75 5 5.35 5.45 4.65 4.55 10 150 1.1 1.5 1.8 0.4 0.3 10 5000 TYP 10 MAX 10.55 10.65 MIN 9.45 9.35 10 150 5 5.35 5.45 4.65 4.55 10 5000 1.1 1.5 1.8 pA V TLC555I TYP 10 MAX 10.55 10.65 MIN 9.45 9.35 10 5000 5 5.35 5.45 pA V TLC555M TYP 10 MAX 10.55 10.65 pA V UNIT

VIT IIT VI(TRIG) II(TRIG) VI(RESET) II(RESET)

Threshold voltage

MAX 25C Full range 25C MAX 25C Full range 25C Full range 25C Full range 25C Full range 25C Full range 25C Full range 25C Full range 12.5 12.5 13.5 13.5 14.2 14.2

66.7%

66.7%

66.7%

0.77

1.7 1.8

0.77

1.7 1.8

0.77

1.7 1.8

0.1 0.5 14.2 12.5 12.5 14.6 13.5 13.5 14.9 14.2 14.2 1.28 3.2 3.6 0.63 1 1.3 0.12 0.3 0.4 360 600 800

0.1 120 14.2 12.5 12.5 14.6 13.5 13.5 14.9 14.2 14.2 1.28 3.2 3.7 0.63 1 1.4 0.12 0.3 0.4 360 600 900

0.1 120 14.2

nA

14.6

14.9

1.28

3.2 3.8

0.63

1 1.5

0.12

0.3 0.45

360

600 1000

Full range is 0C to 70C for TLC555C, 40C to 85C for TLC555I, and 55C to 125C for TLC555M. For conditions shown as MAX, use the appropriate value specified in the recommended operating conditions table. NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG.

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SLFS043C SEPTEMBER 1983 REVISED SEPTEMBER 1997

operating characteristics, VDD = 5 V, TA = 25C (unless otherwise noted)

PARAMETER Initial error of timing interval Supply voltage sensistivity of timing interval tr tf fmax Output pulse rise time Output pulse fall time Maximum frequency in astable mode TEST CONDITIONS VDD = 5 V to 15 V, , CT = 0.1 F, RL = 10 M, M RA = 470 , CT = 200 pF, RA = RB = 1 k to 100 k, , See Note 3 CL = 10 pF RB = 200 , See Note 3 1.2 MIN TYP 1% 0.1 20 15 2.1 MAX 3% 0.5 75 60 %/ V ns MHz UNIT

Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process run. NOTE 3: RA, RB, and CT are as defined in Figure 1.

electrical characteristics at VDD = 5 V, TA = 25C

PARAMETER VIT IIT VI(TRIG) II(TRIG) VI(RESET) II(RESET) Threshold voltage Threshold current Trigger voltage Trigger current Reset voltage Reset current Control voltage (open circuit) as a percentage of supply voltage Discharge switch on-state voltage Discharge switch off-state current VOH VOL High-level output voltage Low-level output voltage IOH = 1 mA IOL = 8 mA IOL = 5 mA IOL = 3.2 mA 4.1 IOL = 10 mA 0.4 1.36 TEST CONDITIONS MIN 2.8 TYP 3.3 10 1.66 10 1.1 10 66.7% 0.14 0.1 4.8 0.21 0.13 0.08 0.4 0.3 0.3 A V 0.5 V nA V 1.5 1.96 MAX 3.8 UNIT V pA V pA V pA

IDD Supply current See Note 2 170 350 NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG.

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TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIMES TO DISCHARGE OUTPUT FROM TRIGGER AND THRESHOLD SHORTED TOGETHER vs SUPPLY VOLTAGE
600 t PHL , t PLH Propagation Delay Times ns VDD = 2 V, IO = 1 mA IO(on) 1 mA CL 0 TA = 25C

DISCHARGE SWITCH ON-STATE RESISTANCE vs FREE-AIR TEMPERATURE

100 70 Discharge Switch On-State Resistance 40 VDD = 5 V, IO = 10 mA VDD = 15 V, IO = 100 mA

500

20 10 7 4

400

300

200

tPHL tPLH

2 1 75 50

100

0 25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16 18 20 TA Free-Air Temperature C VDD Supply Voltage V The effects of the load resistance on these values must be taken into account separately.

Figure 1

Figure 2

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APPLICATION INFORMATION
0.1 F RA 0.1 F 4 7 RB 6 THRES 2 CT TRIG GND 1 GND tPLH TRIGGER AND THRESHOLD VOLTAGE WAVEFORM VDD tPHL RL 3 Output CL 1/3 VDD 2/3 VDD tc(L)

tc(H)

5 8 CONT VDD RESET TLC555 DISCH OUT

Pin numbers shown are for all packages except the FK package. CIRCUIT

Figure 3. Astable Operation Connecting TRIG to THRES, as shown in Figure 3, causes the timer to run as a multivibrator. The capacitor CT charges through RA and RB to the threshold voltage level (approximately 0.67 VDD) and then discharges through RB only to the value of the trigger voltage level (approximately 0.33 VDD). The output is high during the charging cycle (tc(H)) and low during the discharge cycle (tc(L)). The duty cycle is controlled by the values of RA, RB, and CT as shown in the equations below. t c(H) t c(L) Period

[ CT (RA ) RB) In 2 (In 2 + 0.693) [ CT RB In 2 + tc(H) ) tc(L) [ CT (RA ) 2RB) In 2 t R c(L) Output driver duty cycle + [ 1 R )B2R t ) tc(L) c(H) A B +t
t c(H) c(H) t

Output waveform duty cycle

c(L)

R [ R )B2R A B

The 0.1-F capacitor at CONT in Figure 3 decreases the period by about 10%. The formulas shown above do not allow for any propagation delay times from the TRIG and THRES inputs to DISCH. These delay times add directly to the period and create differences between calculated and actual values that increase with frequency. In addition, the internal on-state resistance ron during discharge adds to RB to provide another source of timing error in the calculation when RB is very low or ron is very high.

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APPLICATION INFORMATION
The equations below provide better agreement with measured values. t

c(H)

+ CT (RA ) RB) In

t 3 exp C T (R

PLH

) ron)

) tPHL ) tPLH

+ CT (RB ) ron) In c(L)

t 3 exp C T (R

PHL

) RB)

These equations and those given earlier are similar in that a time constant is multiplied by the logarithm of a number or function. The limit values of the logarithmic terms must be between In 2 at low frequencies and In 3 at extremely high frequencies. For a duty cycle close to 50%, an appropriate constant for the logarithmic terms can be substituted t t c(H) with good results. Duty cycles less than 50% require that c(H) < 1 and possibly RA ron. These t t t c(H) c(L) c(L) conditions can be difficult to obtain.

In monostable applications, the trip point on TRIG can be set by a voltage applied to CONT. An input voltage between 10% and 80% of the supply voltage from a resistor divider with at least 500-A bias provides good results.

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MECHANICAL DATA
D (R-PDSO-G**)
14 PIN SHOWN PINS ** DIM 0.020 (0,51) 0.014 (0,35) 14 8 A MIN 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) 0.008 (0,20) NOM 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) 0.010 (0,25) M A MAX

PLASTIC SMALL-OUTLINE PACKAGE

0.050 (1,27)

8 0.197 (5,00)

14 0.344 (8,75)

16 0.394 (10,00)

1 A

Gage Plane

0.010 (0,25) 0 8 0.044 (1,12) 0.016 (0,40)

Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10) 4040047 / D 10/96 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012

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MECHANICAL INFORMATION
DB (R-PDSO-G**)
28 PIN SHOWN 0,65 28 0,38 0,22 15 0,15 M

PLASTIC SMALL-OUTLINE PACKAGE

0,15 NOM 5,60 5,00 8,20 7,40

Gage Plane 1 A 14 0 8 0,25 1,03 0,63

Seating Plane 2,00 MAX 0,05 MIN 0,10

PINS ** DIM A MAX

14

16

20

24

28

30

38

3,30

6,50

6,50

7,50

8,50

10,50

10,50

12,90

A MIN

2,70

5,90

5,90

6,90

7,90

9,90

9,90

12,30 4040065 / C 10/95

NOTES: A. B. C. D.

All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150

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MECHANICAL INFORMATION
FK (S-CQCC-N**)
28 TERMINAL SHOWN

LEADLESS CERAMIC CHIP CARRIER

18

17

16

15

14

13

12

NO. OF TERMINALS ** 11 10 28 9 8 7 6 68 5 84 44 52 20

A MIN 0.342 (8,69) 0.442 (11,23) 0.640 (16,26) 0.739 (18,78) 0.938 (23,83) 1.141 (28,99) MAX 0.358 (9,09) 0.458 (11,63) 0.660 (16,76) 0.761 (19,32) 0.962 (24,43) 1.165 (29,59) MIN 0.307 (7,80) 0.406 (10,31) 0.495 (12,58) 0.495 (12,58) 0.850 (21,6) 1.047 (26,6)

B MAX 0.358 (9,09) 0.458 (11,63) 0.560 (14,22) 0.560 (14,22) 0.858 (21,8) 1.063 (27,0)

19 20 21 B SQ 22 A SQ 23 24 25

26

27

28

4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25)

0.020 (0,51) 0.010 (0,25)

0.055 (1,40) 0.045 (1,14)

0.045 (1,14) 0.035 (0,89)

0.028 (0,71) 0.022 (0,54) 0.050 (1,27)

0.045 (1,14) 0.035 (0,89)

4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004

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MECHANICAL INFORMATION
JG (R-GDIP-T8)
0.400 (10,20) 0.355 (9,00) 8 5

CERAMIC DUAL-IN-LINE PACKAGE

0.280 (7,11) 0.245 (6,22)

4 0.065 (1,65) 0.045 (1,14)

0.020 (0,51) MIN

0.310 (7,87) 0.290 (7,37)

0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN

0.063 (1,60) 0.015 (0,38) 0.100 (2,54)

0.023 (0,58) 0.015 (0,38) 0.014 (0,36) 0.008 (0,20)

015

4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only. Falls within MIL-STD-1835 GDIP1-T8

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TLC555, TLC555Y LinCMOS TIMERS

SLFS043C SEPTEMBER 1983 REVISED SEPTEMBER 1997

MECHANICAL DATA
P (R-PDIP-T8)
0.400 (10,60) 0.355 (9,02) 8 5

PLASTIC DUAL-IN-LINE PACKAGE

0.260 (6,60) 0.240 (6,10)

4 0.070 (1,78) MAX 0.020 (0,51) MIN 0.310 (7,87) 0.290 (7,37)

0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN

0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 0.010 (0,25) NOM

0 15

4040082 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

17

TLC555, TLC555Y LinCMOS TIMERS

SLFS043C SEPTEMBER 1983 REVISED SEPTEMBER 1997

MECHANICAL INFORMATION
PW (R-PDSO-G**)
14 PIN SHOWN 0,30 0,19 14 8

PLASTIC SMALL-OUTLINE PACKAGE

0,65

0,10 M

0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0 8 0,75 0,50

Seating Plane 1,20 MAX 0,05 MIN 0,10

PINS ** DIM A MAX 8 14 16 20 24 28

3,10

5,10

5,10

6,60

7,90

9,80

A MIN

2,90

4,90

4,90

6,40

7,70

9,60 4040064 / E 08/96

NOTES: A. B. C. D.

All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153

18

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

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