Design Flow Implementation

This document covers the RTL to GDSII implementation of a test design counter. It covers the design flow steps with explanations. Design flow is a sequence of steps that converts the Chip RTL(register transfer level) specification into a Signoff GDSII which is sent to foundry for fabrication. The very basic steps involved in design flow are shown in the diagram below.

CHIP SPECIFICATION The requirements of a customer are captured in form of a HDL (Hardware Description Language), which is a Programming Language that can describe the functionality and timing of hardware circuits. HDL is used for representing functionality of a block because: It defines parallelism inherent to hardware blocks It defines time sequenced (digital blocks with clock) Two widely used HDLs are Verilog VHDL

The Program describing the functionality and timing written in HDL is called RTL (Register Transfer Logic). It represents the functionality of the block in terms of the registers and the combinational logic. E.g The code : Y = !A : Represents an inverter in actual Hardware Y = !A after 5 ns : Represents an inverter with Delay of 5 ns. CHIP SYNTHESIS Synthesis is a process to realize the functionality described in the RTL model code, through a library of tested standard gates. Input to a synthesis tool is a Hardware description of each logic block in terms of HDL and synthesis is done with an aim to: Map the design on to a library Create a gate level netlist : list of components and their instantiation. Logic Synthesis = Optimisation + Mapping Design Optimisation is done for : Area : Design must fir in a maximum area Power : Design must consume less than a maximum power Speed : Design must run at a given clock speed Mapping translates the HDL into standard cells from the target library

To Understand RTL and Gate Level Netlist after Synthesis, lets take an example of Clock Divider module divide_by_2 ( Q, ck,reset ); input ck, reset ; output Q; reg Q; // The Procedural assignments start here always @ (posedge ck ) begin if (reset) Q<=0; else Q <= !Q; End endmodule cp reset D Q

Divide By Two Ckt

After Synthesis The Gate Level Netlist for the above ckt is : module divide_by_2 ( Q_int, Q, ck, D, reset); input D, ck, reset; output Q, Q_int; wire net1; FD2QLLP DFF (.CD(reset), .D(Q), .CP(ck), .Q(net1)); IVLL INV1 (.A(net1), .Z(Q)); endmodule

LAB1 : Synthesis Lets take an Example of an 8-bit counter. Step 1. Write the RTL Step 2. Synthsize it to obtain Gate Level netlist.

For the Complete flow, we will work on cmos090 Platform. The Design Package used is : Name :C090LP_7M2t_50A_2VT_SNPS-ASTRO Version : 4.2 Make a Working Area Copy files : 1. .synopsys_dc.setup 2. COUNTER_rtl.v 3. synth_commands from /home/vineetg1/TRAINING/Synthesis In the working Type following commands s /sw/cshrc/solaris/synps_v-2004.06-sp2-5 dc_shell-t A command window will open Type the commands specified in the synth_commands file one by one and analyse the results. The Output Obtained after Synthesis will be: 1. COUNTER.ref.v -> gate level netlist 2. COUNTER.sdc -> constraints file

Synthesis Flow The diagram lists down the basic command and flow for synthesis using Design Compiler.For more details about the command refer user manual for Design Compiler.

Defining constraints for the design

Physical Implementation Flow Phsyical implementation involves converting a gate level level verilog netlist into layout. Most widely used AVANT! Flow for physical implementation is described below

LAB2 : Physical Implementation Create an Environment to execute the Remaining Steps of RTL2GDS Flow 1. mkdir workspace 2. inside workspace create two directories SETUP and LIBRARIES 3.copy seed.tcl, .ucdprod and setup.csh from /home/vineetg1/TRAINING/inputs in the SETUP directory. 4. Inside LIBRARIES directory type following command ln -s /home/stcv/areas/stdm/prods/CORE90LPHVT_SNPS-AVT@2.1@20041011.0 CORE90LPHVT 5. Inside SETUP directory type command setenv G_WORKSPACE <here specify the path upto workspace directory> source setup.csh avtGenerateTasks 6. Copy Project Variables from /home/vineetg1/TRAINING/inputs directory into workspace/AVANTI/PLACEANDROUTE directory, Overwrite the Project Variables if they are already present. This will create the directory structure as desired with the relevant files.

Import Design The purpose of this step is to Import the Netlist and sdc obtained after Synthesis in Astro for creation of Milkyway Database which will be used by Astro for performing complete PnR ( Placement and Routing). In the workspace/AVANTI/IMPORT Copy COUNTER.ref.v and COUNTER.sdc obtained after Synthesis. Copy COUNTER.clock.attx from /home/vineetg1/TRAINING/inputs Go to AVANTI/PLACEANDROUTE Type-> Astro & This will open Astro GUI In the GUI go to adv_flow->DataPrep , A form will open ie.

Here specify COUNTER.ref.v and COUNTER.attx and unselect the remaining files, Next click on Files Editor, this will open a form ie.

Here as shown select all the fields except PostCtS and Exceptions, and specify the path of COUNTER.sdc in all the fields as shown and click OK. Then click OK on DataPrep Form. This will make some settings which will be used later in the Flow. Next Go to adv_flow -> Import Design and click OK. This will Import the verilog and constraints file and change the verilog into CEL view , which will be used for Placement and Routing. The CEL view will look like:

Fig 1.1 The Red rectangle is the core region where std_cells will be placed, outside the Red region is the Boundary. The std_cells are shown on the right hand side.

Import design involves following steps in Astro, refer Astro User guide to know more details.

FLOORPLAN/POWER PLAN Floorplan is the design elements positioning in a given area. Floorplanning is the exercise of arranging blocks of layout within a chip to minimize area or maximize speed.It can be also called as a allotment of silicon real estate to different blocks in the design.The input to the floorplanning is typically the dimensions of the chip i.e. the area constraint. Floorplan involves positioning of the hard macros in the design for ex : analog blocks like PLL are sensitive to electromagnetic environment and should be positioned near to IO ring. It also involves Power planning with ffg main goals: Supply every single transistor with less voltage/current drop Dedicated IO Pads bring power supply to the circuit Standard Cells are given power through standard cell rails in the design Lets continue with the lab to floorplan the design counter LAB 2 contd Next step is to Modify the Width and Height of Boundary and Core region, so to have all the std_cells placed with 80% utilization. For that Go to : Design Setup-> Set Up Fllorplan A window will be open as shown:

Here Modify the Core Utilization, Core To Left, Core To Right, Core To Bottom and Core To Top to the values as shown in the Figure above. For details please refer to help menu in the Floor Planner form. After Modification press OK. The Cell view will change and will look like as shown:

Go To adv_flow-> FloorPlan : here unselect Add IO Fillers . The Form will look like:

Here it will add PG Grid and std_cell Rails. The Clik OK. The cell will look like as shown:

Here as it can be seen The Power Planning is done, The vdd (Power) and gnd (Ground) Rails in M6 (Orange colour) Vertical and gnd Rail in M7 (Violet colour) Horizontal has been created which are connetcted to std_cell rails M1(blue colour) Horizontal. Also The timing driven pin Placement has been done automatically. The Width of the vdd and gnd Rails and spacing attributes are specified in The Project Varibles inside workspace/AVANTI/PLACEANDROUTE Directory. On page 4, in step 6 we have copied Project variables as they have modified, the modification done was to reduce the width and spacing of vdd and gnd rails as our design size is small and with the default width and spacing we were not able to accommodate both the rails. The parameters which have been modified are : Initial Values: define STM_powerVertStripes '("vdd" 6.66 31.36 "M6" 15.68) define STM_groundVertStripes '("gnd" 6.66 31.36 "M6" 15.68) define STM_powerHorizStripes '("vdd" 6.66 31.36 "M7" 15.68) define STM_groundHorizStripes '("gnd" 6.66 31.36 "M7" 15.68) define STM_topPowerVertStripes '("vdd" 6.66 31.36 "M7" 15.68) define STM_topGroundVertStripes '("gnd" 6.66 31.36 "M7" 15.68) Modified Valuse : define STM_powerVertStripes '("vdd" 3 20 "M6" 10) define STM_groundVertStripes '("gnd" 3 20 "M6" 10) define STM_powerHorizStripes '("vdd" 3 20 "M7" 10)

define STM_groundHorizStripes '("gnd" 3 20 "M7" 10) define STM_topPowerVertStripes '("vdd" 3 20 "M7" 10) define STM_topGroundVertStripes '("gnd" 4 31.36 "M7" 10) ie. Width have been changed from 6.66 to 3 and spacing have been modified from 31.36 to 20. For Details about Other Parameters of Project Variables, Refer to AvantiKit.pdf. The Path is : /work/upt/prods/AvantiKit@2.3.5.2@20050224.1/doc/UserManual/AvantiKit.pdf Once the Power Planning and Pin Placement is done we can start with the placement: Floorplanning steps are

To refer the details refer to Astro User Guide

PLACEMENT Placement is the task of placing logic cells or gates in some pre allocated rows to minimize area or cycle time.Cells are placed adjacent to each other to minimize interconnections.It involves automatic placement of standard cells within the rows optimizing the connection length.

LAB 2 contd.. Go to adv_flow-> Place Design. The Form will look like:

Here the Options Selected are std_cells Placement, where the Placement will be timing Driven. If Timing Driven mode is not selected the Placement will be Congestion Driven. Also PrePlacement Optimization and Post Placement Optimization options are selected, here the tool will do Otimization to meet timing, max transition and max capacitance violation by Upsizing or adding buffers in the path. Press OK. The Design will Look like as shown:

Now as shown the std cells are placed inside the rows. Rows can be seen by clicing of the

Window option and then select the rows. All std cells should be placed on the Rows. As specifed early while Modifying the Width and Height of the Boundary and core region in Fig 1.1 , we started with 80% utilization. Now we can check the utilization after placement, for that go to Query-> List PR Summary and Press OK . This will Open a form showing the Design Summary. It is mandatory to ensure that after each and every step the utilization should not cross 100%. Placement flow using Astro is as shown below, for details refer the astro user guide.

CLOCK TREE SYNTHESIS CTS method constructs a tree of clock buffers with some suitable geometry such that modules that communicate with each other recive well-defined clocks. Clock constraints required for CTS are: Min & max insertion delay Clock transition Buffers and Inverters to be used for CTS Max skew

LAB 2 contd.. Go to adv_flow -> Tree Synthesis. Here unselect create High Fanout Net Trees. The Form will look as:

This will Preform the Tree Synthesis, Buffers and Invertors are added as specified in the COUNTER.clock.attx file present in the workspace/AVANTI/IMPORT Directory. The files to be checked After Tree Syntheis are present in workspace/AVANTI/PLACEANDROUTE/CLK_REPORT Here Open each and every file and see the contents. Check the Global Skew, min Insertion Delay (Shortest Path delay) and max Insertion Delay (Longest path Delay) in the file clk.clocks.best.skew.postct and clk.clocks.worst.skew.postcts. Open the COUNTER.clock.attx in the workspace/AVANTI/IMPORT directory and verify whether the skew and insertion delay are coming as desired. Check the Timing report in workspace/AVANTI/PLACEANDROUTE/REPORT/timing.ClockTree.rpt and check if there is ant Setup and Hold Violation. Next Step is Routing:

Above is the Tree synthesis flow for CTS , refer astro guide for details

ROUTING A router takes a module placement and a list of connections and connect the module with wires Global Routing: Maps general pathways through the design for each unrouted net. The global router uses a twodimensional array of GR cells to model the demand & capacity of Global Routing Detail Routing: Uses the general pathway suggested by Global routing & track assignments to place paths & contacts in order to route the nets

Clock Tree Routing should be done in the way that all the flops in the clock tree receive the clock at the same time.Routing results in a placed netlist in which all the clock and signal nets are routed. Design is now completely implemented. The diagram below shows the routing consideration for different blocks in a design.

LAB 2 contd .

Go to adv_flow -> Route Design, Here unselect Route Clock Tree. The Form will look like:

This will Route The Design. Here the Options Selected is Xtalk Prevent, this will Route the design while taking xtalk into account. The Design after Routing will Look as shown:

Now Check the Final Utilization by running Query -> List PR Summary. Check there is no DRC and LVS issues. These can be checked by running verify -> LVS ( For LVS) and Route Utility -> Router Verify for checking DRC. Astro flow for routing is shown below , refer astro user guide for further details