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FQP9N50C/FQPF9N50C

QFET
FQP9N50C/FQPF9N50C
500V N-Channel MOSFET
General Description
These N-Channel enhancement mode power field effect transistors are produced using Fairchilds proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switched mode power supplies, active power factor correction, electronic lamp ballasts based on half bridge topology.

TM

Features
9 A, 500V, RDS(on) = 0.8 @VGS = 10 V Low gate charge ( typical 28 nC) Low Crss ( typical 24 pF) Fast switching 100% avalanche tested Improved dv/dt capability

D
!

G! G DS

TO-220
FQP Series

GD S

TO-220F
FQPF Series
!

Absolute Maximum Ratings


Symbol VDSS ID IDM VGSS EAS IAR EAR dv/dt PD TJ, TSTG TL

TC = 25C unless otherwise noted

Parameter Drain-Source Voltage - Continuous (TC = 25C) Drain Current - Continuous (TC = 100C) Drain Current - Pulsed
(Note 1)

FQP9N50C 500 9 5.4 36

FQPF9N50C 9* 5.4 * 36 * 30 360 9 13.5 4.5

Units V A A A V mJ A mJ V/ns W W/C C C

Gate-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TC = 25C)
(Note 2) (Note 1) (Note 1) (Note 3)

- Derate above 25C Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds

135 1.07 -55 to +150 300

44 0.35

* Drain current limited by maximum junction temperature

Thermal Characteristics
Symbol RJC RCS RJA Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Case-to-Sink Typ. Thermal Resistance, Junction-to-Ambient FQP9N50C 0.93 0.5 62.5 FQPF9N50C 2.86 -62.5 Units C/W C/W C/W

2003 Fairchild Semiconductor Corporation

Rev. A, June 2003

FQP9N50C/FQPF9N50C

Electrical Characteristics
Symbol Parameter

TC = 25C unless otherwise noted

Test Conditions

Min

Typ

Max

Units

Off Characteristics
BVDSS BVDSS / TJ IDSS IGSSF IGSSR Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate-Body Leakage Current, Forward Gate-Body Leakage Current, Reverse VGS = 0 V, ID = 250 A ID = 250 A, Referenced to 25C VDS = 500 V, VGS = 0 V VDS = 400 V, TC = 125C VGS = 30 V, VDS = 0 V VGS = -30 V, VDS = 0 V 500 ------0.57 ------1 10 100 -100 V V/C A A nA nA

On Characteristics
VGS(th) RDS(on) gFS Gate Threshold Voltage Static Drain-Source On-Resistance Forward Transconductance VDS = VGS, ID = 250 A VGS = 10 V, ID = 4.5 A VDS = 40 V, ID = 4.5 A
(Note 4)

2.0 ---

-0.65 6.5

4.0 0.8 --

V S

Dynamic Characteristics
Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25 V, VGS = 0 V, f = 1.0 MHz ---790 130 24 1030 170 30 pF pF pF

Switching Characteristics
td(on) tr td(off) tf Qg Qgs Qgd Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDS = 400 V, ID = 9 A, VGS = 10 V
(Note 4, 5)

VDD = 250 V, ID = 9 A, RG = 25
(Note 4, 5)

--------

18 65 93 64 28 4 15

45 140 195 125 35 ---

ns ns ns ns nC nC nC

Drain-Source Diode Characteristics and Maximum Ratings


IS ISM VSD trr Qrr Maximum Continuous Drain-Source Diode Forward Current Maximum Pulsed Drain-Source Diode Forward Current VGS = 0 V, IS = 9 A Drain-Source Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge VGS = 0 V, IS = 9 A, dIF / dt = 100 A/s
(Note 4)

------

---335 2.95

9 36 1.4 ---

A A V ns C

Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 8 mH, IAS = 9A, VDD = 50V, RG = 25 , Starting TJ = 25C 3. ISD 9A, di/dt 200A/s, VDD BVDSS, Starting TJ = 25C 4. Pulse Test : Pulse width 300s, Duty cycle 2% 5. Essentially independent of operating temperature

2003 Fairchild Semiconductor Corporation

Rev. A, June 2003

FQP9N50C/FQPF9N50C

Typical Characteristics

10

ID, Drain Current [A]

ID, Drain Current [A]

VGS 15.0 V 10.0 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom : 4.5 V Top :

10

150 C
o

25 C
10
0

-55 C

10

Notes : 1. 250 s Pulse Test 2. TC = 25

Notes : 1. VDS = 40V 2. 250 s Pulse Test

10

-1

10
-1

-1

10

10

10

10

VDS, Drain-Source Voltage [V]

VGS, Gate-Source Voltage [V]

Figure 1. On-Region Characteristics

Figure 2. Transfer Characteristics

2.0

VGS = 10V

RDS(ON) [ ], Drain-Source On-Resistance

10

1.5

1.0

IDR, Reverse Drain Current [A]

VGS = 20V

10

150 25
10
-1

0.5
Note : TJ = 25

Notes : 1. VGS = 0V 2. 250 s Pulse Test

10

15

20

25

0.2

0.4

0.6

0.8

1.0

1.2

1.4

ID, Drain Current [A]

VSD, Source-Drain voltage [V]

Figure 3. On-Resistance Variation vs Drain Current and Gate Voltage

Figure 4. Body Diode Forward Voltage Variation with Source Current and Temperature

2000
Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd

12

1600

10

VDS = 100V VDS = 250V

Ciss

VGS, Gate-Source Voltage [V]

Capacitance [pF]

1200

VDS = 400V

Coss
800

Crss
400

Notes ; 1. VGS = 0 V 2. f = 1 MHz

2
Note : ID = 9A

0 -1 10

0 10
0

10

10

15

20

25

30

VDS, Drain-Source Voltage [V]

QG, Total Gate Charge [nC]

Figure 5. Capacitance Characteristics

Figure 6. Gate Charge Characteristics

2003 Fairchild Semiconductor Corporation

Rev. A, June 2003

FQP9N50C/FQPF9N50C

Typical Characteristics

(Continued)

1.2

3.0

2.5

BV DSS , (Normalized) Drain-Source Breakdown Voltage

RDS(ON) , (Normalized) Drain-Source On-Resistance

1.1

2.0

1.0

1.5

1.0
Notes : 1. VGS = 10 V 2. ID = 4.5 A

0.9

Notes : 1. VGS = 0 V 2. ID = 250 A

0.5

0.8 -100

-50

50

100
o

150

200

0.0 -100

-50

50

100
o

150

200

TJ, Junction Temperature [ C]

TJ, Junction Temperature [ C]

Figure 7. Breakdown Voltage Variation vs Temperature

Figure 8. On-Resistance Variation vs Temperature

10

Operation in This Area is Limited by R DS(on)

10

Operation in This Area is Limited by R DS(on)

10 s 100 s
10
1

10 s 100 s 1 ms 10 ms 100 ms DC

ID, Drain Current [A]

ID, Drain Current [A]

10

1 ms 10 ms 100 ms DC

10

10

10

-1

Notes : 1. TC = 25 C 2. TJ = 150 C 3. Single Pulse


o o

10

-1

Notes : 1. TC = 25 C 2. TJ = 150 C 3. Single Pulse


o o

10

-2

10
0

-2

10

10

10

10

10

10

10

10

VDS, Drain-Source Voltage [V]

VDS, Drain-Source Voltage [V]

Figure 9-1. Maximum Safe Operating Area for FQP9N50C

Figure 9-2. Maximum Safe Operating Area for FQPF9N50C

10

ID, Drain Current [A]

0 25

50

75

100

125

150

TC, Case Temperature []

Figure 10. Maximum Drain Current vs Case Temperature

2003 Fairchild Semiconductor Corporation

Rev. A, June 2003

FQP9N50C/FQPF9N50C

Typical Characteristics

(Continued)

10

(t), T h e rm a l R e s p o n s e

D = 0 .5

0 .2
10
-1

0 .1 0 .0 5 0 .0 2 0 .0 1 s in g le p u ls e

N o te s : 1 . Z JC t) = 0 .9 3 /W M a x . ( 2 . D u ty F a c t o r , D = t 1 / t 2 3 . T JM - T C = P D M * Z J C t) (

PDM t1 t2

JC

10

-2

10

-5

10

-4

10

-3

10

-2

10

-1

10

10

t 1 , S q u a r e W a v e P u ls e D u r a t io n [ s e c ]

Figure 11-1. Transient Thermal Response Curve for FQP9N50C

(t), T h e rm a l R e s p o n s e

D = 0 .5
10
0

0 .2 0 .1 0 .0 5
10
-1

N o te s : ( 1 . Z JC t) = 2 .8 6 /W M a x . 2 . D u ty F a c t o r , D = t 1 / t 2 3 . T JM - T C = P D M * Z J C t) (

0 .0 2 0 .0 1

PDM t1
s in g le p u ls e

JC

t2

10

-2

10

-5

10

-4

10

-3

10

-2

10

-1

10

10

t 1 , S q u a r e W a v e P u ls e D u r a t io n [ s e c ]

Figure 11-2. Transient Thermal Response Curve for FQPF9N50C

2003 Fairchild Semiconductor Corporation

Rev. A, June 2003

FQP9N50C/FQPF9N50C

Gate Charge Test Circuit & Waveform

50K 12V 200nF 300nF

Same Type as DUT VDS

VGS Qg 10V Qgs Qgd

VGS

DUT
3mA

Charge

Resistive Switching Test Circuit & Waveforms

VDS VGS RG

RL VDD

VDS

90%

10V

DUT

VGS

10%

td(on) t on

tr

td(off) t off

tf

Unclamped Inductive Switching Test Circuit & Waveforms

L VDS ID RG DUT
tp

BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD BVDSS IAS VDD VDD
tp

ID (t) VDS (t) Time

10V

2003 Fairchild Semiconductor Corporation

Rev. A, June 2003

FQP9N50C/FQPF9N50C

Peak Diode Recovery dv/dt Test Circuit & Waveforms

DUT

+ VDS _

I SD L Driver RG
Same Type as DUT

VDD

VGS

dv/dt controlled by RG ISD controlled by pulse period

VGS ( Driver )

Gate Pulse Width D = -------------------------Gate Pulse Period

10V

IFM , Body Diode Forward Current

I SD ( DUT ) IRM

di/dt

Body Diode Reverse Current

VDS ( DUT )

Body Diode Recovery dv/dt

VSD

VDD

Body Diode Forward Voltage Drop

2003 Fairchild Semiconductor Corporation

Rev. A, June 2003

FQP9N50C/FQPF9N50C

Package Dimensions

TO-220
9.90 0.20 1.30 0.10 2.80 0.10 (8.70) 3.60 0.10 (1.70) 4.50 0.20

1.30 0.05

+0.10

9.20 0.20

(1.46)

13.08 0.20

(1.00)

(3.00)

15.90 0.20

1.27 0.10

1.52 0.10

0.80 0.10 2.54TYP [2.54 0.20] 2.54TYP [2.54 0.20]

10.08 0.30

18.95MAX.

(3.70)

(45 )
0.50 0.05
+0.10

2.40 0.20

10.00 0.20

Dimensions in Millimeters
2003 Fairchild Semiconductor Corporation Rev. A, June 2003

FQP9N50C/FQPF9N50C

Package Dimensions

(Continued)

TO-220F
3.30 0.10 10.16 0.20 (7.00) 3.18 0.10 2.54 0.20 (0.70)

6.68 0.20

15.80 0.20

(1.00x45)

MAX1.47 9.75 0.30 0.80 0.10


(3 ) 0

0.35 0.10 2.54TYP [2.54 0.20]

#1 0.50 0.05 2.54TYP [2.54 0.20] 4.70 0.20


+0.10

2.76 0.20

9.40 0.20

Dimensions in Millimeters
2003 Fairchild Semiconductor Corporation Rev. A, June 2003

15.87 0.20

TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.

ACEx FACT ActiveArray FACT Quiet series Bottomless FAST FASTr CoolFET CROSSVOLT FRFET GlobalOptoisolator DOME EcoSPARK GTO E2CMOS HiSeC EnSigna I2C Across the board. Around the world. The Power Franchise Programmable Active Droop DISCLAIMER

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PACMAN POP Power247 PowerTrench QFET QS QT Optoelectronics Quiet Series RapidConfigure RapidConnect SILENT SWITCHER SMART START

SPM Stealth SuperSOT-3 SuperSOT-6 SuperSOT-8 SyncFET TinyLogic TruTranslation UHC UltraFET VCX

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY


FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems 2. A critical component is any component of a life support which, (a) are intended for surgical implant into the body, device or system whose failure to perform can be or (b) support or sustain life, or (c) whose failure to perform reasonably expected to cause the failure of the life support when properly used in accordance with instructions for use device or system, or to affect its safety or effectiveness. provided in the labeling, can be reasonably expected to result in significant injury to the user.

PRODUCT STATUS DEFINITIONS Definition of Terms


Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.

Preliminary

No Identification Needed

Full Production

Obsolete

Not In Production

2003 Fairchild Semiconductor Corporation

Rev. I2

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