Design Techniques of CMOS SCL circuits for Gb/s Applications

Lu Jianhua, Tian Lei, Chen Haitao, Xie Tingting, Chen Zhiheng, Wang Zhigong Institute of RF&OE ICs, Radio Engineering Dept. Southeast Univ., Sipailou 2, Nanjing, 2 10096 Email: 1ujianhua~seu.edu.cn; http://iroi.seu.edu.cn
Abstract This paper presents the design techniques of Gbis CMOS SCL circuits. Basic SCL functional cells including a 2:l multiplexer, a D-latch, and XOR/NXOR, ANDINAND, OR/NOR gates are described in detail. Simulations show that a SCL static fi-equency divider can operate faster than a CMOS static logic one. Experimental results of an SCL 1.4 static frequency divider and an SCL 4:l inultiplexer both in 0.35pm CMOS technology prove that SCL circuits can be used in Gb/s applications.
1. liitroduction

circuitry and design issues of SCL. The detail techniques will be demonstrated. The comparison mentioned above is presented in Section 111. To demonstrate the feasibility of the proposed techniques, an SCL 1:4 static frequency divider and an SCL 4:l inultiplcxer are both designed and realizcd in 0.35~~11 CMOS technology. The experimental results are presented in Section 1V.
11. SCL Circuits

A . General Design Issiies

The counterparts of CMOS SCL circuits in Si Bipolar and GaAs technology are ECL (Emitter Coupled Logic) or CML (Common Mode Logic) circuits and SCFL (Source Coupled FET Logic) circuits separately. The basic topology of SCL is similar with these two types, as it is shown in Fig. 1. However, there are two main differences in SCL because of the features of CMOS devices.

Over the past few years, digital ICs running at Gb/s have been emerging in many electronic systems, especially in optic-fiber transmission systems. As the emergence of microprocessor running over I Gb/s [ 11, the demand for high-speed digital circuits will be increaced greatly. In thc past, such high-speed digital ICs arc often realized in Si Bipolar and 11UV compound technologies. However, as the feature size greatly scaled down. deep submicron CMOS technologics can be used to realize ICs at Gbius. In fact. the traditional CMOS logic circuits can reach Gbit/s in deep submicron technologies[2]. However, if SCL (Source Coupled Logic) circuits are used, a speed of higher than Gb/s can be reached even in a 0.35pn-1 or 0.5pin CMOS technology. This paper presents design techniques of SCL circuits, including the basic circuit design. These techniques are described in the context of several circuit topologies and their performance analysis, namely 2: 1 niultiplexer (MUX), a D-latch, and XORrNXOR, ANDNAND. OWNOR gates. In order to demonstrate the speed advantage of SCL circuits over traditional CMOS logic circuits, the performance of SCL is compared to CMOS static logic circuits. This comparison is based on the speed of a frequency divider. The next section of this paper presents the basic

Fig. 1 Representative CML circuits: inverter (left) and stacked differential pairs (right) Firstly, active loads, such as PMOS, mostly substitute passive resistors. In high-speed cases, the resistance of the loads in a SCL circuit should be very accurate. But the CMOS passive resistors, usually made of poly silicon, suffer a roughly variation due to the process; and this variation could be +20% in most cases. That's the reason why we use active loads more than passive ones. Secondly, the SF (Source Followers) in SCL can be omitted. Although SFs exhibit high input impedance

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and moderate output impedance, the drawbacks of SFs, namely, nonlinearity due to body effect, voltage headroom consuniption due to level shift, and poor driving capability, limit the use of this topology [3]. Perhaps the most cominon application of SFs is in performing voltage level shift. However, this function of SFs may be meaningless if the voltage level can be set appropriately. The voltage levels and signal swings of SCL circuits can be set flexibly. We can see that lower swings can make the circuits faster, from the following expression,
TDclay

multiplexer. It consists of two symmetric differential 1 pairs MI-M2 and M3- M4 that sample the inputs D and D2 and they are controlled by CK through the lower-level differential pair M5 and M6, respectively. The output currents of the high-level two pairs are suinnied at nodes Q and Qn. and flow through MPI and MP2. The circuit operates as follows. When CK is positive, M5 is on, allowing MPI and MP2 to draw current from M1 and M2. At this time, M6 is turned off, the pair M3-M4 is disabled. Thus, the input D1 is transferred to output. Similarly, When CK becomes negative, the pair M1-M2 is disabled, the pair M3-M4 is enabled, and the input D2 is transferred to output. The gates of MPI and MP2 are connected with ground to make these two PMOS operating in linear region. Thus, we can get a more linear effective resistance. The tail current is usually produced by an NMOS operating in saturated region by rightly setting the gate voltage.
C. D-Latch

cc -

CA V
IS

(1)

where TDCl,, the delay of a current pair, such as (Ml, is M2) in Fig.1, C is the total capacitor at point Q or Qn, AV is signal swing, and IS is the bias current. From (I), we can also see that if we can increase the speed of the circuits by increasing the bias current. That is why we often say high-speed at the cost of power consumption. According to our experience, it is appropriate to set the single ended swings in 200-300mV, that is, 400-600niV in difYerential. Thus, the output of the circuits should also generate signals with such swings. The effective resistance R of the load (passive or active) and the bias current Is co-determine the output signal swings if all the devices of current pairs operate in saturated region. And this condition is easy to meet by carefully setting the voltage levels. However, it is difficult to set the input voltage levels equal to output. If a voltage level shift is necessary, SFs can be used to cascade the cells. B. 2: 1 Multiplexer
VDD

If one of the differential pairs in the MUX is reconfigured into a cross-coupled pair, then a D-latch results, as shown in Fig.3. This circuit comprises an input sampling pair Ml-M2 and a latching pair M3-M4, which are controlled by CK and CK in a manner similar to that described for the MUX of Fig. 2. When CK+ is high, the sampling pair is enabled, nodes Q and Qn track the input D, and M3 and M4 are off. When CK+ goes low, the sampling pair turns off, the latching pair turns on, and the instantaneous state at Q and Qn is stored in the loop around M3 and M4.
VDD

Qn

x+Fig. 2 2: 1 Multiplexer Shown in Fig. 2 is the circuit diagram of a 2:1

&
Fig. 3 D-Latch

~-

Contrasting with the symmetric sized pairs, the latching pair of D-Latch is sometime designed smaller than the sampling pair in gate width, just to increase

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its operating speed. [ ] 4

VDD

D. Logic guks ufXONNXOR. AND/NAND, ONNOR

The MUX of Fig.2 can perforin an XOR function if configured as in Fig. 4. Here, both of the diffcrential pairs sample the input A but with anti-phase, while the clamp devices sample the input B. When B is high, the pair M 1-M2 is enabled, thus, X = A and Y = A . When B is low, the pair M3- M4 is enabled, thus X = A and Y

A . ~n results, the logical output is equal to A O B (or can be A @ B , for the output is
=

Fig. 6 OR/NOR gate

111. Comparison with CMOS Logic Circuits

differential). According to the analysis above, we can easily find out the logic function of the ANDNAND circuit shown in Fig.5. Using the same topology of ANDNAND, we can get OWNOR circuits by siniply changing the polarity of both A and B, as shown in Fig. 6. Note that, there is a Mx connected with M6 in series. Adding this device here is just to keep M5 and M6 in balance in voltage level.
VDD

SCL circuits have the speed advantage than other logic circuits using MOSFETs. In order to perform a meaningful, easy-to-produce comparison, we present one simple benchmark: a static frequency divider. To obtain comparable speeds, we compare the speed of these circuits both in TSMC 0.35pin CMOS technology by using siinulations at the room temperature. TSMC provides the BSIM3v3 model; and the simulator is Smartspice@.

Fig. 4 XOR/NXOR gate

VDD

DLatch

SLlUrc* Follower

Fig. 7 Schematic of an SCL static frequency divider

Fig. 8 CMOS static logic static frequency divider

f
Fig. 5 AND/NAND gate

The SCL and CMOS static logic dividers are illustrated in Fig.7 and 8 respectively. They are both composed by a MS-DFF (Master-Slave Delay Flip-Flop) with its output negatively feedback to its

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input. A differential signal can easily get reversed, while the single-ended single have to use an inverter to get a negative one, as shown in Fig.8. To inake the simulation results close to real case at the best, another stage of divider is connected to the output as a load and stage; all the device capacitance, including CDMIN CSOUKCt, and all key parasite capacitors are back-annotated to netlists after the layout is finished. With a 3.3V supply, circuit simulations indicate that, the SCL divider achieves a inaximuin operation frequency of 4.8GHz when the input level is not less than 0 SV, whereas the CMOS static logic divider can operate only up to 1.3 GHz. Even if we increase the voltage supply to 5V. it cannot operate faster than 1.XGHz. From the simulation results, we can see that SCL circuits runs much faster than CMOS static logic. In addition, SCL circuits can easily inake interface with most high-speed IC family, since they use ECL or CML voltage level. Furthermore, since the power consuii~ptionof single ended CMOS logic circuits is proportional to the square of operating frequency, the power consumption of SCL circuits are not necessarily larger at high-speed.
1V. Experimental Results

designed and fabricated in standard 0.35pn CMOS tcchnology. The 1 :4 static frequency dividcr includes two identical I :2 divider cells, which use the schematic shown in Fig.7. The measured results are similar with siniulations results. With a 3.3V supply, the divider can operate up to 5GHz if the input level is no less than 0.8V. Each 1:2 divider cell consumes a power dissipation of 3mW. Fig.9 presents its die photograpli and measured waveforms when it operates at 5GHz. Thc 4:1 MUX consists a group of 2:l MUXs and latches, whose schematics are similar with that are shown in Fig2 and Fig.3 respectively. Fig.10 shows its die photograph and measured output eye diagram at 2.5Gb/s with a supply of 5V.

V. Conclusion
Design techniques of CMOS SCL circuits have been presented. Described in ihe context of several building blocks such as a 2:l MUX, a D-Latch, and XORNXOR, AND/NAND, OR/NOR gates. These techniques allow gigahertz speeds in the 0.35pin CMOS technology. Simulations and cxperiinental results indicate that the proposed SCL topologies and design techniques can be used in multigigahertz applications. References of a 1.2GHz 1A64 microprocessor , ISSCC, Feb. 200 1. 121 Masakazu Kurisu, et al., 2.8-Gbls 176-nib byte-Interleaved and 3.0-Gbk 118-inW bit-Interleaved 8: 1 Multiplexers with a 0.1 5-pin CMOS technology IEEE JSSCC, Vol. 3 I , No. 12, December 1996. [3] Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill Higher Education, 2000 [4] Koichi Murata, et al. a novel high-speed latching operation Flip-flop (HLO-FF) circuits and its application to a 19-Gb/s decision circuit using a 0.2-ttrn GaAs MESFET , IEEE, JSSCC, Vol. 30, No. 10, Oct. 1995

[I]

S. Naffziger, G.Harnmond, The implementation

a b Fig.9 Static frequency dividers (a) die photograph and (h) measured waveforms of 5GHz input & 1.25GHz output.

a b Fig.10 4:l Multiplexers (a) die photograph; (b) measured output eye diagram at 2.5Gb/s

As exainples oE SCL circuits, an SCL 1:4 static frequency divider and an SCL 4:l multiplexer are

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