0S4 0000 00100H Chili Module Datasheet

CHILIdevices International
Doc. No 0S4-0000-00100H 22-02-2010
CHILImodule CDM1540x
Hardware Datasheet
Copyright CHILIdevices International 2010. All Rights Reserved.
1 (90)
Doc. No 0S4-0000-00100H 22-02-2010
CONTENTS CONTENTS ..............................................................2 FIGURES .................................................................5 TABLES ...................................................................7 REVISION HISTORY ................................................8 DATA SHEET STATUS ..............................................9 DEFINITIONS AND ABBREVIATIONS ....................10 GENERAL DESCRIPTION .......................................11 DEVICE DETAILS................................................... 13 PRINCIPLES OF OPERATION .................................15
Power Supply ............................................................................ 15 Wireless Communications ......................................................... 15 Processor and Memory .............................................................. 16 Fixed Interfaces ........................................................................ 16 Field Programmable Logic Array (FPGA) ................................... 17 Software ................................................................................... 18
APPLICATIONS ..................................................... 19 ORDERING INFORMATION ....................................20 FUNCTIONAL BLOCK DIAGRAM .............................21 HARDWARE .......................................................... 22
Terminal Functions .................................................................... 22
Pin Diagrams ........................................................................................ 22 Pin Descriptions .................................................................................... 22 General ............................................................................................... 30
Functional Description............................................................... 30 Reset Input / Output................................................................. 33 Power Supply ............................................................................ 34 Processor .................................................................................. 38
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Direct Connections from Processor ........................................... 38 FLASH........................................................................................ 39 SDRAM ...................................................................................... 40 EEPROM..................................................................................... 40 REAL TIME CLOCK ..................................................................... 40 FPGA ......................................................................................... 41
I/O Standards....................................................................................... 42 FPGA Clock Signals ................................................................................ 43 FPGA GPIO Specifications ....................................................................... 44 FPGA Configuration Loader ..................................................................... 44 Using External Configuration Memory ....................................................... 45 Using ByteBlaster II Download Cable ....................................................... 45 USB .................................................................................................... 46 I2C ..................................................................................................... 47 SDIO ................................................................................................... 47 WLAN (IEEE 802.11b) ............................................................................ 48 Integrated Antenna ......................................................................... 49 External Antenna ............................................................................ 49 WEP Encryption/Decryption and AES Security Algorithms ...................... 49 ZigBee (IEEE 802.15.4) ......................................................................... 49 External Batteries ................................................................................. 51 Li Battery Charging ............................................................................... 52 Charger operation ........................................................................... 52 Charge current and safety timer ........................................................ 52 Maximum charge current.................................................................. 54 Current threshold setting ................................................................. 55 Temperature qualified charging ......................................................... 55 Status outputs ................................................................................ 55 Battery Charge Monitoring ................................................................ 56 System Clocks ...................................................................................... 57 JTAG/Debugging (PXA270) ..................................................................... 57 JTAG/Debugging (FPGA)......................................................................... 59
Module Interfaces ..................................................................... 46
Absolute Maximum Ratings ....................................................... 60 Recommended Operating Conditions ......................................... 61 Electrical Characteristics ........................................................... 61 Package Outline ........................................................................ 62
ADDITIONAL INFORMATION ................................65

Chemical Content ...................................................................... 65 Contact Information .................................................................. 65
APPLICATION GUIDELINES ..................................66

Application Examples ................................................................ 66
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Getting Started with the CHILImodule .................................................... 66 FPGA Recovery Image............................................................................ 67 MMC/SD Card Interface.......................................................................... 68 USB Client Device Interface .................................................................... 71 USB Host Controller Interface ................................................................. 72
Application Notes ...................................................................... 73
Using Custom Clock Frequencies with FPGA .............................................. 73 Using External Antennas ........................................................................ 73 Lithium Battery Considerations................................................................ 73 Using External Ethernet Devices .............................................................. 75 Using External CAN Devices .................................................................... 76 System Debugging and Driver Development Guidelines .............................. 76
Boot Device Selection Guidelines .............................................. 77 Printed Circuit Board Design Guidelines .................................... 77
Base Substrate Selection ........................................................................ 77 Land Pattern Recommendations .............................................................. 77 Escape Pattern for CHILImodule............................................................. 78 Layout Guidelines .................................................................................. 78 Via Design ........................................................................................... 79 PCB Finish ............................................................................................ 79 Paste Stencil Design .............................................................................. 80 General ............................................................................................... 80 Unpack the Module .......................................................................... 80 Solder Base Board to the Application Board......................................... 80 Insert Radio Board .......................................................................... 81 Mount Enclosure ............................................................................. 82 Moisture Preconditioning ........................................................................ 82 Solder Paste ......................................................................................... 83 Reflow Profile ....................................................................................... 83 Rework and Component Removal ............................................................ 86
Assembly Guidelines ................................................................. 80
DISCLAIMERS ....................................................... 87 APPENDIX ............................................................ 88

CHILImodule - FPGA Connections Cross Reference ................. 88
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FIGURES
Figure 1 Functional Block Diagram - CHILImodule Professional .................................... 21 Figure 2 Pin Diagram .............................................................................................. 22 Figure 3 Antennas and RF Connectors ....................................................................... 30 Figure 4 Simple Application Examples........................................................................ 31 Figure 5 Network Gateway / Router Applications ......................................................... 32 Figure 6 Ethernet Connectivity by External MAC + PHY Device ...................................... 32 Figure 7 Multimedia Application Examples .................................................................. 32 Figure 8 System Controller Application ...................................................................... 33 Figure 9 Advanced Measurement System ................................................................... 33 Figure 10 Power Supply Options for the CDM15400 Devices.......................................... 37 Figure 11 RDY Connections for Variable Latency I/O Interface ....................................... 39 Figure 12 Memory Map - CDM15400/CDM15401 ......................................................... 40 Figure 13 FPGA Clock Options .................................................................................. 43 Figure 14 Connecting External Configuration Device .................................................... 45 Figure 15 Connecting ByteBlaster II Download Cable ................................................... 46 Figure 16 WLAN (IEEE 802.11b) Interface .................................................................. 48 Figure 17 Star topology ........................................................................................... 50 Figure 18 cluster tree topology ................................................................................. 50 Figure 19 Mesh topology ......................................................................................... 51 Figure 20 Built-In Battery Charger ............................................................................ 53 Figure 21 Charge Current Setup ............................................................................... 53 Figure 22 Built-In Battery Charger ............................................................................ 56 Figure 23 Boundary Scan Connections ....................................................................... 58 Figure 24 External Debugger Interface ...................................................................... 58 Figure 25 External JTAG Controller Interface .............................................................. 59 Figure 26 The CHILImodule 324-Pin Package ............................................................ 63 Figure 27 Example of Simple System ........................................................................ 66 Figure 28 Adding Li+ Battery to the System ............................................................... 66 Figure 29 Enabling Boundary Scan/JTAG Debugger ..................................................... 67 Figure 30 Using SDA and Memory Card for FPGA Image Control .................................... 68 Figure 31SD / SDIO Interface................................................................................... 69 Figure 32 Example of the SD Card Interface (Comm pin connected to DGND).................. 70 Figure 33 MMC Card Interface .................................................................................. 71 Figure 34 USB Client Device Interface ....................................................................... 71
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Figure 35 USB Host Device Interface ......................................................................... 72 Figure 36 Typical Lithium Cell Charge Profile .............................................................. 74 Figure 37 Example of the Lithium Cell Capacity Vs. Temperature ................................... 75 Figure 38 External Ethernet MAC + PHY ..................................................................... 75 Figure 39 Using External CAN Transceiver .................................................................. 76 Figure 40 Pad Style Definitions ................................................................................. 77 Figure 41 Padstack Recommendation ........................................................................ 78 Figure 42 Package Layout Pattern ............................................................................. 78 Figure 43 Land Pattern And Via Design ...................................................................... 79 Figure 44 Paste Stencil Recommendation ................................................................... 80 Figure 45 Base Board .............................................................................................. 81 Figure 46 Examples of Reflow Profiles........................................................................ 84 Figure 47 Another Reflow Profile Example .................................................................. 85
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TABLES
Table 1 Ordering Information ................................................................................... 20 Table 2 Pin Descriptions .......................................................................................... 22 Table 3 MR# Input Specifications .............................................................................. 33 Table 4 Master Reset MR# ....................................................................................... 34 Table 5 RSO# Output Specifications .......................................................................... 34 Table 6 Power Source in Use .................................................................................... 35 Table 7 Power Source Selection by External Signal ...................................................... 35 Table 8 BATT_LOW# and BATT_FAULT# Specifications ................................................ 36 Table 9 VCC_OUT and VCC_BAT Specifications ........................................................... 36 Table 10 RTC_PWR Specifications ............................................................................. 37 Table 11 FPGA Configurations .................................................................................. 41 Table 12 I/O Standards of the CHILImodule / Altera FPGA .......................................... 42 Table 13 I/O Specifications of Altera Cyclone .............................................................. 44 Table 14 Altera Serial Configuration Devices ............................................................... 45 Table 15 WLAN Interface Specifications ..................................................................... 48 Table 16 Antenna Selection (WLAN, ZigBee) ............................................................... 48 Table 17 ZigBee Interface Specifications .................................................................... 51 Table 18 Charge Currents ........................................................................................ 53 Table 19 Battery Charging Specifications ................................................................... 54 Table 20 Status Output Specifications (VCC = 5V)....................................................... 56 Table 21 Absolute Maximum Ratings ......................................................................... 60 Table 22 Recommended Operating Conditions ............................................................ 61 Table 23 Module Electrical Characteristics .................................................................. 61 Table 24 The CHILImodule Package Information ........................................................ 63 Table 25 The CHILImodule Package Properties .......................................................... 64 Table 26 Recommended Baking Procedure ................................................................. 83 Table 27 Reflow Profile Recommendations.................................................................. 83 Table 28 Heating Zone Temperatures (Example) ......................................................... 85
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REVISION HISTORY
Data Sheet Revision A B C D Date 02.10.2005 14.03.2006 20.06.2006 23.08.2006 29.01.2007 22.08.2007 5.12.2007 Description Objective Data Preliminary Data Preliminary Data Preliminary Data Product Data Product Data Battery charger operation revised Product Data Antennas and RF connectors identification added Note of FPGA I/O leakage currents during configuration and pull-down resistor values added 3.3V output voltage off switching during reset and sleep conditions added Baking procedure recommendation added Fixed application guidelines for USB host pin names corrected (USBC_* to USBH_*) fixed USB host figure caption text Module assembly instructions/guidelines updated Humidity indicator information fixed, Assembly guidelines refined Note numbers [2] and [4] fixed to match actual pins (table 2)
24.2.2009
F G H
2.3.2009 18.5.2009 22.2.2010
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DATA SHEET STATUS

Data Sheet Status Objective Data Product Status Development Definition The data sheet contains from the objective specification for product development. CHILIdevices reserves the right to change the specification in any manner without notice. The data sheet contains data from preliminary specification. Supplementary data will be published at a later date. CHILIdevices reserves right to change the specification without notice, in order to improve the design and supply the best possible product The data sheet contains data from the product specification. CHILIdevices reserves right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the CHILIdevices Customer Product/Process Change Notification procedure.
Preliminary Data
Qualification
Product Data
Production
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DEFINITIONS AND ABBREVIATIONS

AES BCD BGA BST EEPROM FFD FPGA GPIO GPS HDI HDI IOE IP JTAG LVCMOS LVTTL MMC NSMD OSP OTG RF RFD RoHS RTC SiP SMD SoC USB VHDL WEP WLAN Advanced Encryption Standard Binary-Coded Decimal Ball Grid Array Boundary Scan Test Electrically Erasable Programmable Read Only Memory Full Function Device Field Programmable Gate Array General Purpose I/O Global Positioning System High Density Interconnect High Density Interconnect (Altera) Input/Output Element Intelligent Property Joint Test Action Group Low Voltage CMOS Low Voltage TTL MultiMedia Card Non-Soldermask Defined Pads Organic Solder Protective On-the-Go Radio Field Reduced Function Device Restriction of Hazardous Substances Real Time Clock System-in-Package Surface Mounted Device; Soldermask Defined Pads System-on-Chip Universal Serial Bus Vlsic Hardware Description Language Wireless Equivalent Privacy Wireless Local Area Network
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GENERAL DESCRIPTION
The CHILImodule is an advanced, highly flexible system core module built in a small 2.0 mm pitch Ball Grid Array (BGA) System-in-Package (SiP). The module types available are CHILImodule Professional (CDM15400) CHILImodule Standard (CDM15401) The main features of the CDM15400/15401 are as follows
Power Supply Single Power Supply (+3.5V...+5VDC) Low Power (1...3W typ.) Operation Regulated Supply Voltage Output (+3.3V/700mA max.) Battery Support (CDM15400 only) Built-In Li-Ion/Li-Polymer Battery Charger Built-In Fuel Gauge (Battery Monitor) Processor Intel XScale PXA270, ARM9 Based 32-bit RISC CPU of 312MHz (CDM15401) or 416MHz (CDM15400) Memory FLASH for Program Memory o CDM15401: 16MBytes o CDM15400: 64MBytes SDRAM for Program & Data Memory o CDM15401: 16MBytes o CDM15400: 64MBytes Wireless Interfaces (CDM15400 only) Built-In WLAN (IEEE 802.11b) Built-In ZigBee (IEEE 802.15.4) Programmable Logic Field Programmable Gate Array (FPGA) with 4kLE (CDM15401) or 12kLE (CDM15400) Capacity Mass Storage Support for Memory Cards (Compact Flash, MMC, SD) System Peripherals Real Time Clock (RTC) EEPROM Interfaces 116 Programmable General Purpose I/O Pins 32-Bit Processor Bus (via FPGA device) PCMCIA / PC Card / Compact Flash LCD (STN, TFT) Up to SVGA Resolution 16-Bit Audio I/O I2C SPI I2S SDIO USB 1.1 Host/Client + USB 2.0 OTG Support Software Support Built-In Self Diagnostics UBoot Bootloader Built-In FPGA Configuration Loader Linux V2.6 Operating System JFFS2 File System Qt Graphics Library Drivers for Various Peripherals FPGA IP Support Processor Resource Routing Wishbone Bus Interface for IP Extensions UART 16550 Serial Peripheral Interconnect (SPI) Controller Inter Integrated Circuit (I2C) Controller Ethernet MAC 10/100 MBit/s Additional Features High Speed / Low Power Operation (No Forced Cooling or Fan Required) Support for Boundary Scan (IEEE 1149.1) Test, Debug and Program (Processor and FPGA) Robust and Easy-to-Route 2.0 mm Pitch Ball Grid Array (BGA) Package
The CHILImodule provides embedded system designer a rich set of features to utilize in a commercial product. By hiding the implementation details inside of the module interface, the CHILImodule helps to reduce the development risks and allows the designer to stay within time and budget limits during the actual design process. The device comprises of ARM9 based CPU (Intel XScale PXA270) with FLASH (up to 64MBytes) and SDRAM (up to 64MBytes) memories required for the application software, Field Programmable Gate Array (FPGA) for flexible and configurable module interface, integrated wireless communication interfaces (only in CDM15400) for both wireless local area networks (WLAN; IEEE 802.11) and for power efficient control networks based on
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ZigBee (IEEE 802.15.4). Module contains integrated antennas for both of the RF interfaces as well as miniature RF coaxial connectors for using external antennas as applicable. By utilizing either the CPU resources or FPGA intelligent property (IP) peripherals, the system level design may be efficiently created. FPGA resources can be used for extending the CPU peripheral set, further interfacing custom devices to the CHILImodule, or simply for gaining more performance due to hardware acceleration (signal processing applications etc.). In addition to wireless interfaces, the CHILImodule is capable for providing wide range of standard wired interfaces like Ethernet, USB 1.1 (Client, Host) including USB 2.0 OTG Support, CAN, UART (RS-232, RS-485, RS422), SPI, I2C... In addition to various communication interfaces, the CHILImodule devices also support memory cards (MMC/SD/SDIO) for implementing local storage capability for the embedded system. The support for multimedia applications and various user interface solutions is comprehensive: the CHILImodule can drive small, character based COG LCD displays as well as full color (up to SVGA/800x600 pixels) TFT LCD displays. Adding audio (in/out) interface to the solution is matter of only adding simple AC97 compatible codec to the system. The power management and supervisory including the power-down mode support have been fully incorporated in the CHILImodule resulting small form factor module implementation that can be run from single +3.5...+5VDC power supply (+4.5...+5VDC for Lithium-Ion or Lithium-Polymer battery charging). In addition to using external power supply, the CHILImodule can be run from the LithiumIon or Lithium-Polymer batteries. The built-in Lithium battery charger of the CHILImodule can be used to charge battery fast and easy. Remaining battery capacity can be read from integrated fuel gauge (battery monitor). For stand-alone applications, the module provides +3.3V/700mA power supply for the surrounding circuitry for design simplicity. Thanks to the large pitch (2.0 mm) and small dimensions (70.5 x 46.5 x 10 mm) the CHILImodule can easily designed-in to the application - typically, a 4-layer printed circuit board with 0.5 mm via holes will be sufficient for most of the designs. From the software point of view, the CHILImodule comes pre-installed bootloader, FPGA configuration loader and operating system. The software bundle includes the device drivers for built-in peripherals and for some external peripherals. The CHILImodule supports using open source FPGA IP blocks based on Wishbone bus interface as well as creating your very own FPGA IPs. The FPGA may be used for either signal routing, for extending system with new peripheral types or even for hardware acceleration to gain more system performance. The bootloader, Linux operating system, FPGA configuration loader and the ready-to-use FPGA IP blocks come with full source code (C, VHDL) to make it easier for an application designer to create custom designs. In addition to Linux based systems, other bootloader and operating system versions available for the CHILImodule will be released either in source code or in binary format, depending on the licensing model.
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DEVICE DETAILS
Features CHILImodule Standard CDM15401 CHILImodule Professional CDM15400 Basic Hardware Features Power Supply Processor Program Memory (Flash) Data Memory (SDRAM) Data Memory (SRAM; included in the PXA270) Field Programmable Gate Array (FPGA) Programmable I/O Ports Direct Battery Support Battery Charger with Built-In Charge Timer Battery Monitor (Fuel Gauge) EEPROM Real Time Clock with External 3.0V Backup Battery Fixed Interfaces
+3.5...5.5DC Intel XScale PXA270 312 MHz 16MBytes 16MBytes 256kBytes Altera Cyclone EP1C4 Totally 116 I/O NA NA NA 32kBits Yes I2C MMC/SD/SDIO USB Client
+3.5...5.5VDC Intel XScale PXA270 416 MHz 64MBytes 64MBytes 256kBytes Altera Cyclone EP1C12 Totally 116 I/O Lithium-Ion/Lithium-Polymer 4.2V 4.2V/1.35A max. Yes 32kBits Yes I2C MMC/SD/SDIO USB Client
Wireless Features ZigBee Interface WLAN Interface
NA NA
IEEE 802.15.4 (Int./Ext. Antenna) IEEE 802.11b (Int./Ext. Antenna)
Mechanical Specifications Package Dimensions FPGA IP Features Wishbone Compatible Bus Interface Ethernet MAC 10/100 CAN 2.0 MAC UART 16550 SPI Controller I2C Controller (CPU Resource Routing) Custom IP External Peripheral Support Power Supply Output Resistive Touchscreen LCD Interface (COG, STN/TFT, QVGA, VGA, SVGA...) Audio Interface (AC97 Codec: Sp, Mic, Line Out, Line In) Compact Flash Card Interface (PCMCIA) MMC/SD Card Interface SDIO Interface I2C Interface Ethernet Controller (LAN91C111) CAN 2.0 Controller (PCP2515) GPIO (CPU GPIO) Software Features Built-In Self Diagnostics Bootloader
324 Pin BGA (2.0 mm Pitch) 70.5 x 46.5 x 10 mm
324 Pin BGA (2.0 mm Pitch) 70.5 x 46.5 x 10 mm
Yes NA NA Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes Yes Yes Yes
+3.3VDC/700mA Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
+3.3VDC/700mA Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Yes Yes
Yes Yes
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Features FPGA Configuration Loader Operating System Device Drivers for Peripherals, External Devices File System Graphical User Interface
IPs
and
CHILImodule Standard CDM15401 Yes Yes Yes Yes Yes
CHILImodule Professional CDM15400 Yes Yes Yes Yes Yes
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PRINCIPLES OF OPERATION
The CHILImodule is a complete ready-to-use, commercial off-the-self (COTS) system core for building embedded systems and applications. All the primary functions of an embedded system have been included in the high density system-in-package (SiP) of the CHILImodule. In addition to wired communication standards, like RS232/422/485, Ethernet or USB, the possibilities of wireless communication interfaces (WLAN and ZigBee) are available in the CHILImodule Professional version of the device.
Power Supply
For the operation, the CHILImodule device (CDM15400, 15401) requires only single power supply voltage of +3.5...5VDC. In addition to main power supply, optional backup battery (3.0V Lithium battery) can be connected to the CHILImodule for preserving the real time clock (RTC) time keeping during the sleep or power-down modes of the CPU. The CHILImodule contains all the circuitry needed for generating, sequencing and controlling internal power supplies as needed without any user intervention. The CHILImodule is powered-up by connecting the external power supply to the device if device is run from external power only. The internal power supply of the CHILImodule also supports the dynamic power control features of the processor for battery-powered applications. In addition to the external power supply, the CHILImodule Professional can also be powered from a single 4.2V Lithium-Ion or Lithium-Polymer cell. The CHILImodule Professional contains built-in battery charger that controls the recharging of the battery if the VCC power supply is available, and battery monitor (fuel gauge) for tracking the remaining capacity of the battery. The charge current and safety timer timeout period can be set according to the desired battery cell type. For design simplicity, the CHILImodule devices provide regulated +3.3VDC supply voltage (up to 700mA) for the surrounding circuitry and external peripherals, and thus eliminating the need of additional supply voltage regulators. The continuous power output of 3.3V (10 mA max.) may be used for powering up debugger interface. Continuous power output is available when either VCC or battery cell voltage is present.
Wireless Communications
The CHILImodule Professional (CDM15400) contains ready-to-use radio transceivers and MACs for both Wireless LAN (WLAN; IEEE 802.11b) and ZigBee (IEEE 802.15.4) communications. Standard WLAN interface offers the benefits of wireless local area network connections that previously were available only for the more expensive devices and computers. The WLAN enables connecting the embedded device to the common local area network infrastructure via wireless access points, gateways and routers. The high bandwidth of the WLAN interface allows transferring large amounts of data quickly from the embedded device to another device or computer and vice versa. The ZigBee communication standard is aimed for cost-efficient, low power sensor and control networks. As the CHILImodule has capability of ZigBee Full Function Device (FFD), it can easily be configured either as a member of the ZigBee network or even the ZigBee
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network Coordinator. With all the resources of the CHILImodule it can easily function as a network gateway or router to interface ZigBee networks to standard local area networks and even Internet. The CHILImodule system software includes device drivers and protocol stacks for both of these wireless communications. The WLAN interface provides the modern encryption/decryption standards (WEP, AES) for secure wireless network communications. The ZigBee interface that is aimed for cost effective sensor and control networks, and the implementation provides AES encryption/decryption.
Processor and Memory

The CHILImodule is based on low power, high performance Intel XScale PXA270 processor designed for embedded applications. The CPU has rich set of integrated peripherals, including support for example USB, serial ports, mass media (like memory cards), audio and various displays. In addition to this, many processor pins may be configured as general purpose I/O lines. The power dissipation of the processor is typically below 500mW, and the processor supports dynamic frequency and voltage management for saving power in battery powered applications. The CHILImodule contains 16MBytes (CDM15401) or 64MBytes (CDM15400) FLASH memory for the program code storage or Flash data file system and 16MBytes (CDM15401) or 64MBytes (CDM15400) SDRAM memory for data storage or fast program execution.
Fixed Interfaces
In addition to completely configurable digital I/O interfaces, the CHILImodule provides a few fixed interfaces for easy system design and for enabling fail-safe system configurations. Fixed interfaces that have not been routed via the built-in FPGA device comprise of I2C Interface (for FPGA fail-over handling) SDIO Interface (for connecting SDIO compatible SD/MMC Cards to the system without hassle) USB 1.1 Client Interface (for implementing USB 1.1 Full Speed Client application with no extra devices) As failures in FPGA design may prevent some system designs from booting properly, the CHILImodule devices support fail-over functionality. Driving the I2C bus SDA-line low during the power-up sequence forces the CHILImodule to fall back to the 'known good configuration' of the FPGA. This allows system designer to provide a minimum FPGA configuration as a fail-over backup configuration. SDIO interface signals may be routed directly to external SD/MMC Card connector (socket) . This allows system to use SD/MMC Card for system update during boot sequence. The main system updates images include FPGA image upload - for uploading new FPGA configuration to the module Linux Kernel image upload - for uploading new Linux Kernel image to the module Linux RootFS image upload - for uploading new Linux RootFS image to the module Thanks to the CHILImodule design, implementing a simple USB 1.1 interface is only matter of connecting USB signals to USB client connector.
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Field Programmable Logic Array (FPGA)

The CHILImodule device interface comprises of large Field Programmable Logic Array (FPGA) device that has great impact of the CHILImodule's flexibility and adaptability in various systems - the move from 'hard' to 'soft' design content opens up new horizons for a system designer. Totally, there are 116 freely programmable I/O lines in the CHILImodule, in addition to the fixed interfaces already mentioned. The direction, operation and functionality of these I/O lines are defined by the actual FPGA configuration (aka FPGA image) that can be uploaded from an external device to the CHILImodule during the boot-up sequence. Depending on the CHILImodule device type, there are two FPGA logic capacities available Altera Cyclone EP1C4 (4kLE, up to 78 336 RAM Bits): CHILImodule Standard (CDM15401) Altera Cyclone EP1C12 (12kLE, up to 239 616 RAM Bits): CHILImodule Professional (CDM15400) The FPGA logic of the CHILImodule forms a flexible ('soft') interface between the CHILImodule internal circuitry and the external systems. The Altera Cyclone FPGA provides all the benefits of large programmable logic to the system designer. In addition to this, the FPGA logic device allows deciding the CHILImodule component pinout by means of routing signals in the FPGA logic to the appropriate device pins. This may further reduce printed circuit board design complexity and therefore save design costs. Using simple printed circuit board also saves money compared to complex HDI (high density interconnect) PCB boards. Both FPGA devices (EP1C4 and EP1C12) support a variety of single-ended I/O standards such as LVTTL, LVCMOS, PCI etc. They also offer differential I/O support via LVDS and RSDS I/O standards. Each channel is capable of operating LVDS signals at up to 640 MBit/s. The FPGA I/O lines also support hot-swap functionality. With up to six outputs from two phase-locked loops (PLLs) per device and a hierarchical clocking structure, Cyclone FPGAs offer extensive clock management circuitry for complex designs as well as fast and easy signal pass-through routing. By means of utilizing the configurable and programmable FPGA I/O interface of the CHILImodule, the system developer can optionally Arrange the CHILImodule device pinout for making the base board routing easy and straightforward Route the CPU resources to selected external peripherals and connectors as required by the rest of the system Control the system performance by sharing the system load between the CPU peripherals and FPGA IP block implemented peripherals Extend or upgrade system capabilities by moving the required digital hardware into FPGA domain by means of soft IP blocks Interface custom circuitry directly to the CHILImodule without using external glue-logic devices Increase performance of the system by allocating selected functionality to FPGA IP blocks (hardware acceleration) The clock signal for the FPGA device is generated internally in the CHILImodule. In addition to this default clocking mode, two external clock signals can be connected to the CHILImodule FPGA device.
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The integrated FPGA device can be programmed by Altera ByteBlaster programmer interface connected directly to the CHILImodule uploading the FPGA image to the module directly from external source (Ethernet, MMC Card etc.)
Software
In addition to the module hardware, the CHILImodule devices come with an extensive set of software, including Bootloader FPGA configuration loader software Operating system File system Device drivers for built-in peripherals and a few external devices FPGA IP blocks (with source code) For further information, please consult the CHILImodule software documentation.
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APPLICATIONS
The application of the CHILImodules (CDM15400 or 15401) include Wireless Mobile Communication Devices Industrial Measurement Systems User Interfaces Machine Interfaces Home Automation Handhelds (GPS, POS Terminal) Consumer Electronics Office Equipment System Routers and Gateways Telecommunications Note that the list above is not meant to be extensive or exclusionary. Thanks to their flexibility, configurability and the rich set of features, the CHILImodule devices fit into a broad range of applications across various product areas. See also section GENERAL DESCRIPTION starting from page 11 and section APPLICATIONS starting from page 19 for more information.
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ORDERING INFORMATION
TABLE 1 ORDERING INFORMATION CHILImodule Device Type CDM15401 (CHILImodule Standard) (Tray of 6 devices) CDM15400 (CHILImodule Professional) (Tray of 6 devices) Antennas (NA) (NA) Built-In Built-In Temperature Range -25C...+70C -40C...+85C -25C...+70C -40C...+85C Ordering Code CDM15401-A000-C000-B00-C-1 CDM15401-A000-C000-B00-I-1 CDM15400-A001-C001-B01-C-1 CDM15400-A001-C001-B01-I-1
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FUNCTIONAL BLOCK DIAGRAM

The CHILImodule devices comprise of mixed embedded design implemented in high density interconnect (HDI) substrates. The design contains mixed type signaling, including power supplies, high-speed digital signals and RF-signals at 2.4GHz.
CHILImodule Professional
CDM15400
I2C EEPROM 32kbit RTC_PWR (3.0V) Real Time Clock (RTC) SRAM 56Bytes Field Programmable Gate Array (FPGA) (Signal Routing) 48MHz SDRAM 32/64MBytes CLK Opt. Wishbone Bus IP IP IP JTAG/IEEE 1149.1 SDIO
RDY Altera ByteBlaster II JTAG/IEEE 1149.1 Ext. CLK1 Ext. CLK2 Totally 116 Programmable I/O Pins USB 1.1 (Client, Host, OTG) Int. Ant. ZigBee IF To Ext. Antenna WLAN IF To Ext. Antenna
Backup Batt Reg. Fuel Gauge I, U EEPROM Temp Li-Ion/Li-Polymer Battery ADJ_CHRG_TIME ADJ_CHRG_CURR CHRG# FAULT# NTC EN_CCHRG_CURR CHRG_RATE_DET PWR_CTL
V(BKBT) Capacity Temp ID Status
Adj. Li Battery Charger Charge_EN
Intel XScale PXA270 416MHz/312MHz
FLASH 16/32/64MBytes PWR_STAT Address Bus Data Bus
Power Control Power Path
SRAM 256kB
Wishbone Bus IF USB 1.1 + USB 2.0 OTG Support ZigBee (802.15.4) Zi:Zo Int. Ant. Zi:Zo
USB VBUS VCC (3.5...5.5V) VCC_OUT (3.3V/0.7A) VCC_BAT (3.3V) MR# RSO#
Power Supply
Internal Supply Voltages
Supervisory, Reset
System Reset PWR Reg
WLAN (802.11b)
ZigBee_EXT# WLAN_EXT#
FIGURE 1 FUNCTIONAL BLOCK DIAGRAM - CHILIMODULE PROFESSIONAL
The CHILImodule Standard (CDM15401) is similar to the CHILImodule Professional except the following main differences The CPU operating frequency is lower (312MHz) The size of the FPGA is smaller (EP1C4) The FLASH memory capacity is limited to 16MBytes The SDRAM memory capacity is limited to 16MBytes There are no wireless interfaces (WLAN, ZigBee) available There is no Lithium battery support (charger, fuel gauge) available Due to the smaller memory and FPGA resources, the CHILImodule Standard support for FPGA/IP peripherals and graphics libraries may be somewhat limited compared to the CHILImodule Professional.
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HARDWARE
Terminal Functions
Pin Diagrams
The I/O pins (BGA ball pads) have been dispersed across the CHILImodule device according to their functionalities to provide an easy-to-route land pattern for the base substrate (printed circuit board) layout design.
Pins Reserved for Future RFU 1 29 58 88 119 127 135 143 Device Control and Status Interface Cont. Pwr Interface +3.3V (Cont.) Li Battery Interface Li+ Li151 159 167 175 183 191 199 207 238 268 297 300 305 RDY 310 315 320 +3.3V Output +3.3VOUT FPGA External Clock Inputs ByteBlaster II Interface 5 10 +3.3V Output +3.3VOUT 15 20 FPGA_IO Bidirectional FPGA I/O Digital Ground DGND 25 28 57 87 118 126 131 139 147 155 163 171 179 187 195 134 142 150 158 166 174 182 190 198 206 237 267 296 324
95 130 138 146 154 162 170 178 186 194
100
105
110
+3.3V Output +3.3VOUT
Top View
USB Host/Client Interface I2C Interface +3.3V Output 215 220 PXA JTAG Interface
225
230
Power Supply Input (+5V) +5V MMC/SD/SDIO Interface
RSO# FPGA JTAG Interface
FIGURE 2 PIN DIAGRAM
Digital ground (DGND) is common for both power supply and I/O signals. Note also, that the pins that have been reserved for future should be left floating.
Pin Descriptions
The pin / signal descriptions of the CHILImodule device are in the following table. See the notes [1], [2], [3] below the table.
TABLE 2 PIN DESCRIPTIONS Not Connected Pins Symbol Pin NC 1 NC 2 NC 3 NC 4 NC 5 NC 6 NC 7 NC 8 NC 29 NC 30 NC 32
Type
Reset
Description Reserved for Reserved for Reserved for Reserved for Reserved for Reserved for Reserved for Reserved for Reserved for Reserved for Reserved for
future future future future future future future future future future future
use use use use use use use use use use use
leave leave leave leave leave leave leave leave leave leave leave
pin pin pin pin pin pin pin pin pin pin pin
unconnected unconnected unconnected unconnected unconnected unconnected unconnected unconnected unconnected unconnected unconnected
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NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
34 36 58 60 62 64 88 89 91 92 93 94 95 119 121 122 127 128 130 135 137 138 146 153 154 162 322
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
for for for for for for for for for for for for for for for for for for for for for for for for for for for
future future future future future future future future future future future future future future future future future future future future future future future future future future future
use use use use use use use use use use use use use use use use use use use use use use use use use use use
leave leave leave leave leave leave leave leave leave leave leave leave leave leave leave leave leave leave leave leave leave leave leave leave leave leave leave
pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin
unconnected unconnected unconnected unconnected unconnected unconnected unconnected unconnected unconnected unconnected unconnected unconnected unconnected unconnected unconnected unconnected unconnected unconnected unconnected unconnected unconnected unconnected unconnected unconnected unconnected unconnected unconnected
Power Supply Outputs Symbol Pin VCC_OUT 9 VCC_OUT 66 VCC_OUT 96 VCC_OUT 97 VCC_OUT 123 VCC_OUT 124 VCC_OUT 126 VCC_OUT 131 VCC_OUT 133 VCC_OUT 134 VCC_OUT 212 VCC_OUT 213 VCC_OUT 225 VCC_OUT 226 VCC_OUT 227 VCC_OUT 255 VCC_OUT 312 Continuous Pwr Output VCC_BAT 178
Type O O O O O O O O O O O O O O O O O
Reset
Description +3.3V supply +3.3V supply +3.3V supply +3.3V supply +3.3V supply +3.3V supply +3.3V supply +3.3V supply +3.3V supply +3.3V supply +3.3V supply +3.3V supply +3.3V supply +3.3V supply +3.3V supply +3.3V supply +3.3V supply
voltage voltage voltage voltage voltage voltage voltage voltage voltage voltage voltage voltage voltage voltage voltage voltage voltage
output output output output output output output output output output output output output output output output output
+3.3V continuous low power output
Module Supply Voltage Input VCC 202 P VCC 210 P VCC 239 P VCC 269 P VCC 297 P VCC 298 P Digital Ground DGND DGND DGND
Module Module Module Module Module Module
supply supply supply supply supply supply
voltage voltage voltage voltage voltage voltage
input input input input input input
main main main main main main
power power power power power power
supply supply supply supply supply supply
of of of of of of
+5V +5V +5V +5V +5V +5V
31 33 35
G G G
Digital ground - common for all power supplies Digital ground - common for all power supplies Digital ground - common for all power supplies
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DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND
37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 86 87 90 116 117 118 120 125 129 132 136 141 145 148 152 157 161 164 168 173 177 180 184 186 189 193 194 196 200 205 209 211 222 235 238 240 241
G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G
Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital
ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground
common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common
for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for for
all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all
power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power power
supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies
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DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND
242 244 246 248 250 252 253 254 256 258 260 262 264 266 268 270 272 274 278 280 282 284 286 288 290 292 294
G G G G G G G G G G G G G G G G G G G G G G G G G G G
Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital
ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground ground
common common common common common common common common common common common common common common common common common common common common common common common common common common common
for for for for for for for for for for for for for for for for for for for for for for for for for for for
all all all all all all all all all all all all all all all all all all all all all all all all all all all
power power power power power power power power power power power power power power power power power power power power power power power power power power power
supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies supplies
Battery Connections Symbol Pin LI 185 LI 192 LI 201 LI 208 LI + 183 LI + 191 LI + 199 LI + 207
Type P P P P P P P P
Reset
Description Negative terminal of Li-Ion/Li-Polymer battery (4.2V battery) Negative terminal of Li-Ion/Li-Polymer battery (4.2V battery) Negative terminal of Li-Ion/Li-Polymer battery (4.2V battery) Negative terminal of Li-Ion/Li-Polymer battery (4.2V battery) Positive terminal of Li-Ion/Li-Polymer battery (4.2V battery) Positive terminal of Li-Ion/Li-Polymer battery (4.2V battery) Positive terminal of Li-Ion/Li-Polymer battery (4.2V battery) Positive terminal of Li-Ion/Li-Polymer battery (4.2V battery)
Real Time Clock (RTC) Power Supply Symbol Pin Type Reset RTC_PWR 176 P Battery Charger I/O Symbol Pin ADJ_CHRG_CURR 167
Description Real Time Clock (RTC) power supply input (3.0V)
Type X
Reset
Description Battery charge current adjustment pin. Charge current may be set to desired value by connecting a resistor from this pin to DGND. The valid charge current rates are set as follows: 463 mA (default: EN_CCHRG_CURR = DGND, USB VBUS disconnected) 93 mA (default: EN_CCHRG_CURR = DGND, USB VBUS connected) Custom rate (EN_CCHRG_CURR = 'H') selected by an external resistor. See also note [2]. Timer capacitor connection. Maximum charge time may be increased from the default value (1.36 hours) by connecting an external capacitor from this pin to DGND Open drain charge status output. When the battery is being charged, CHRG# is pulled low. When the charge current drops below the IDET detection threshold, the CHRG# pin starts sinking 30uA current from pin to ground. When the charge
ADJ_CHRG_TIME
159
CHRG#
143
OD
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FAULT
144
IDET
151
NTC
169
EN_CCHRG_CURR
170
timer runs out or the input supply of the device is removed, the CHRG# pin is forced to high impedance state. A temperature fault causes this pin to blink. Battery fault status output. This pin is logic high if a shorted battery is detected or if temperature fault is detected. A temperature fault occurs with the temperature monitor circuit is enabled and the thermistor temperature is either below 0C or above 50C (typical). Charge rate detection threshold. Connecting a resistor from this pin to DGND programs the charge rate detection threshold. If IDET is left floating, charge rate detection threshold is 100mA. Input to NTC (negative temperature coefficient) thermistor temperature monitoring circuit. NTC shall be tied from this pin to DGND and a resistor of equal value from NTC pin to VCC. The NTC function may be disabled by connecting this pin to DGND. This signal programs the charge current. If EN_CCHRG_CURR is driven low, the charge current depends on parallel connection of internal and external resistors. If the EN_CCHRG_CURR is driven high, the external resistor connected to the ADJ_CHRG_CURR pin defines the charge current.
Power Path Selection Symbol Pin PWR_CTL 175
Type I
Reset
Description Power supply path selection signal. Driving CTL signal high forces the main power supply (+5V) to be selected as a power supply. If CTL is driven low or left floating, the CHILImodule uses the higher voltage of the main power supply or battery cell.
ByteBlaster II Connections Symbol Pin Type FPGA_CE# 311 I FPGA_CONFIG# FPGA_CSO# 308 283 I O
Reset
FPGA_ASDO FPGA_CONF_DONE FPGA_DATA0 FPGA_DCLK
307 310 281 309
O OD I I/O
Description Output control signal from Cyclone FPGA that drives low when configuration is complete. Cyclone FPGA configuration control input Output control signal from Cyclone FPGA to serial configuration device in AS configuration for enabling the serial configuration device Output control signal from Cyclone FPGA to serial configuration device in AS configuration Open drain FPGA configuration status output (internally pulledup with 10k) Cyclone FPGA data input Cyclone FPGA clock signal (input in Cyclone PS configuration, output in Cyclone AS configuration)
FPGA Clock Signals Symbol Pin FPGA_CLK1 223 FPGA_CLK2 224
Type I I
Reset
Description External FPGA clock signal input (connected to Cyclone CLK1 pin) External FPGA clock signal input (connected to Cyclone CLK2 pin)
FPGA I/O Signals Symbol FPGA_IO000 FPGA_IO001 FPGA_IO002
Pin 315 314 313
Type B B B
Reset
FPGA_IO003
285
Description Programmable I/O signal from the FPGA [4] Programmable I/O signal from the FPGA [4] NOTE: Optional DEV_OE input pin for overriding all tri-states on the device in addition to general purpose I/O pin. 1.8V only logic levels. [4] NOTE: Optional DEV_CLRn input pin for overriding all clears on all device registers in addition to general purpose I/O. 1.8V only logic levels. [4]
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FPGA_IO004 FPGA_IO005 FPGA_IO006 FPGA_IO007 FPGA_IO008 FPGA_IO009 FPGA_IO010 FPGA_IO011 FPGA_IO012 FPGA_IO013 FPGA_IO014 FPGA_IO015 FPGA_IO016 FPGA_IO017 FPGA_IO018 FPGA_IO019 FPGA_IO020 FPGA_IO021 FPGA_IO022 FPGA_IO023 FPGA_IO024 FPGA_IO025 FPGA_IO026 FPGA_IO027 FPGA_IO028 FPGA_IO029 FPGA_IO030 FPGA_IO031 FPGA_IO032 FPGA_IO033 FPGA_IO034 FPGA_IO035 FPGA_IO036 FPGA_IO037 FPGA_IO038 FPGA_IO039 FPGA_IO040 FPGA_IO041 FPGA_IO042 FPGA_IO043 FPGA_IO044 FPGA_IO045 FPGA_IO046 FPGA_IO047 FPGA_IO048 FPGA_IO049 FPGA_IO050 FPGA_IO051 FPGA_IO052 FPGA_IO053 FPGA_IO054 FPGA_IO055 FPGA_IO056 FPGA_IO057 FPGA_IO058 FPGA_IO059 FPGA_IO060 FPGA_IO061 FPGA_IO062 FPGA_IO063 FPGA_IO064 FPGA_IO065
320 319 324 323 321 291 318 296 295 293 261 317 316 267 265 263 232 289 259 287 237 236 234 233 231 229 257 206 197 204 203 230 228 198 190 188 195 139 182 181 179 187 115 174 172 171 166 165 156 158 150 149 142 147 155 163 28 27 56 84 26 54
B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B
Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal
from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from
the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the
FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA
[4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4]
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FPGA_IO066 FPGA_IO067 FPGA_IO068 FPGA_IO069 FPGA_IO070 FPGA_IO071 FPGA_IO072 FPGA_IO073 FPGA_IO074 FPGA_IO075 FPGA_IO076 FPGA_IO077 FPGA_IO078 FPGA_IO079 FPGA_IO080 FPGA_IO081 FPGA_IO082 FPGA_IO083 FPGA_IO084 FPGA_IO085 FPGA_IO086 FPGA_IO087 FPGA_IO088 FPGA_IO089 FPGA_IO090 FPGA_IO091 FPGA_IO092 FPGA_IO093 FPGA_IO094 FPGA_IO095 FPGA_IO096 FPGA_IO097 FPGA_IO098 FPGA_IO099 FPGA_IO100 FPGA_IO101 FPGA_IO102 FPGA_IO103 FPGA_IO104 FPGA_IO105 FPGA_IO106 FPGA_IO107 FPGA_IO108 FPGA_IO109 FPGA_IO110 FPGA_IO111 FPGA_IO112 FPGA_IO113 FPGA_IO114 FPGA_IO115 SDIO Interface Symbol PXA_MMC_CLK PXA_MMC_CMD PXA_MMC_DAT0 PXA_MMC_DAT1 PXA_MMC_DAT2/ CS0 PXA_MMC_DAT3/ CS1
82 112 113 114 140 25 24 52 80 110 111 23 22 50 78 108 109 21 48 20 107 19 18 46 76 105 106 17 16 44 74 102 103 104 15 14 13 42 72 100 101 12 40 70 99 11 38 68 98 10
B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B
Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal
from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from from
the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the the
FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA
[4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4]
Pin 271 243 273 301 300 299
Type O O B B B B
Reset
Description SDIO interface SDIO interface up) SDIO interface SDIO interface SDIO interface
clock signal for MMC/SD Card command signal for MMC/SD Card (internal pulldata signal 0 for MMC/SD Card (internal pull-up) data signal 1 for MMC/SD Card (internal pull-up) data signal 2 for MMC/SD Card (internal pull-up)
SDIO interface data signal 3 for MMC/SD Card (internal pull-up)
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I2C Interface Symbol PXA_SCL PXA_SDA
Pin 216 215
Type OD OD
Reset
Description Open drain I2C bus clock signal (internal pull-up) Open drain I2C bus data signal (internal pull-up)
FPGA JTAG Interface FPGA_TCK 276 FPGA_TMS 304 FPGA_TDI 303 FPGA_TDO 302 PXA JTAG Interface Symbol Pin PXA_TRST# 249 PXA_TDO 251 PXA_TCK 279 PXA_TDI 305 PXA_TMS 277 USB Client Interface Symbol Pin USB_VBUS0 214 USB_VBUS1 245 PXA_USBC_N 221 PXA_USBC_P 220 PXA_USBH_N 219 PXA_USBH_P 218 PXA_USBHPEN1 217 PXA_USBHPWR1 247
I I I O
Boundary Boundary Boundary Boundary
Scan Scan Scan Scan
(IEEE (IEEE (IEEE (IEEE
1149.1) 1149.1) 1149.1) 1149.1)
clock signal to FPGA mode selection signal for FPGA data input to FPGA data output from FPGA
Type I O I I I
Reset
Description Boundary Scan Boundary Scan Boundary Scan Boundary Scan Boundary Scan
(IEEE (IEEE (IEEE (IEEE (IEEE
1149.1) 1149.1) 1149.1) 1149.1) 1149.1)
reset signal to PXA270 data output from PXA270 clock signal to PXA270 data input to PXA270 mode selection signal for PXA270
Type P P B B B B O O
Reset
Description External USB bus voltage (+5V) for battery charger External USB bus voltage (+5V) for battery charger USB Client port negative pin of differential pair USB Client port positive pin of differential pair USB Host controller port positive pin of differential pair USB Host controller port positive pin of differential pair Signal to control external USB bus power supply for USB Host implementations Signal to monitor USB bus power supply faults
Module Control Signals Symbol Pin PXA_RDY 275
Type I
Reset
MR# RSO#
160 306
I OD
Description Variable latency input signal of the PXA270 for inserting wait states (internal pull-up). Also connected to FPGA device L Wait H VLIO is ready Master reset input signal for the device (internal pull-up) Open drain reset output signal (internally pulled up by 1M to VCC_BAT)
Notes: [1] [2] [3] [4] Pins named as PXA_* have been routed directly to the PXA270 device pins To avoid permanent damages, the charge current is limited to 1.35A. If operating temperature is high, you should probably decrease the charge current rate. P = Power, G = Ground, I = Input, O = Output, OD = Open-drain, B = Bi-directional, X = Passive Pins named as FPGA_* have been routed directly to the Altera Cyclone device pins
Note The I/O pin leakage current of Altera Cyclone before and during configuration may be higher than during the normal operation. In order to ensure low level at FPGA driven I/O signals before and during configuration, Altera recommends using pull-down resistors (2k max.). Please, consult Altera Cyclone documentation for further details.
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In addition to the BGA ball pad connections at the bottom of the CHILImodule devices, the CHILImodule Professional (CDM15400) offers built-in wireless connections (WLAN, ZigBee). Following antenna options are available for the system designer Built-In chip type antenna for WLAN Built-In chip type antenna for ZigBee Coaxial antenna connector (Hirose U.FL) for connecting external WLAN antenna Coaxial antenna connector (Hirose U.FL) for connecting external ZigBee antenna
ZigBee (IEEE 802.15.4)
WLAN (IEEE 802.11)

FIGURE 3 ANTENNAS AND RF CONNECTORS
Chip type antennas are good solution for compact system designs and for relatively short operating ranges. An external antenna may be connected to the CHILImodule device to further extend the operating range or for the applications that require sealed conductive enclosures. The antenna connections (coaxial connectors) locate under the top cover of the package. Software device drivers control antenna selection. Note, that due to antenna multiplexer both internal and external antennas cannot be used at the same time.
Functional Description
General
The CHILImodule combines the high performance ARM9 based 32-bit RISC processor (Intel XScale PXA270), FLASH/SDRAM memories with the flexible FPGA device and complete power management in a small size surface mounted SiP package. The device requires only single supply voltage for the operation. The processor is characterized by its low power and high performance in addition to rich set of peripherals and features. In addition to capability of driving wired peripherals the CHILImodule Professional also contains support for Lithium-Ion or Lithium-Polymer batteries and provides modern wireless communication interfaces of IEEE 802.11b (WLAN) and IEEE 802.15.4 (ZigBee). In addition to the integrated antennas, the device provides coaxial connectors for using external antennas. The CHILImodule comes with bootloader, operating system and full set of libraries and device drivers to help the user to get the products on markets fast. Transferring your equipment into mobile domain could not be easier: it is only matter of connecting a Lithium-Ion or Lithium-Polymer battery to the CHILImodule. The CHILImodule contains all battery support circuitry, including battery charger and fuel gauge. External power supply of the CHILImodule is used to provide power for charging the battery.
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The CHILImodule is designed to be used in a wide range of embedded applications, including mobile terminals, user interfaces, measurement systems and automation controllers, industrial and commercial solutions etc. Multiple communication options allow the CHILImodule to be easily used as a smart link between different system levels (like Internet and low level sensor networks, as an example).
+3.3V Binary I/O RS232 Binary I/O
+3.3V
SD Card
Li+
LCD + Touchscreen
Heating Humidity Temperature
WLAN
GPS
LCD + Touchscreen Li+ WLAN
FIGURE 4 SIMPLE APPLICATION EXAMPLES
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The CHILImodule device may be used as a gateway or router between various network infrastructures (wireless or wired configurations). Mass storage card (like SD Card may be used for data logging or reporting applications).
ZigBee Binary I/O WLAN
RS232 SD Card RS485
CAN
FIGURE 5 NETWORK GATEWAY / ROUTER APPLICATIONS
The CHILImodule based applications may access standard Ethernet networks by means of either the IP MAC or external MAC+PHY device depending on the choice.
Actuators
ETH MAC+PHY
Ethernet 10/100Base-T
Sensors
FIGURE 6 ETHERNET CONNECTIVITY BY EXTERNAL MAC + PHY DEVICE
The CHILImodule contains features and peripherals that allow system designer to provide equipment with audio subsystems and/or graphical user interfaces fast and easy.
AMP ZigBee CODEC Li+ USB SP
CMOS Image Sensor
LCD + Touchscreen WLAN
Optics
FIGURE 7 MULTIMEDIA APPLICATION EXAMPLES
In industrial systems, the CHILImodule may function as a system monitor, controller or regulator. The choice of the role is mainly matter of the application software. Thanks to its
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low power, the CHILImodule device does not require heat sinks or fans to keep it cool. Therefore the module may be used in applications that will be used in harsh environments as well as light, portable equipments.
Motor M ZigBee Sensors
DRV USB
ETH MAC+PHY
FIGURE 8 SYSTEM CONTROLLER APPLICATION
The CHILImodule devices may be used in complex networks or measurement systems due to the high performance and adaptability of the device.
+3.3V RS232
Analog Inputs
A D ETH PHY
RS422
Binary I/O
CANOpen
GSM Modem
WLAN
FIGURE 9 ADVANCED MEASUREMENT SYSTEM
As a summary: the CHILImodule devices offer power of high performance CPU with the flexibility of the field programmable gate array logic (FPGA) and the freedom of the wireless communication interfaces of WLAN and ZigBee in a small package.
Reset Input / Output

The CHILImodule has single external master reset control input (MR#). Driving the MR# line low forces the processor to cold-reset. During the cold reset, the SRAM content of the processor will be maintained.
TABLE 3 MR# INPUT SPECIFICATIONS Symbol VinL(MR#) VinH(MR#) Parameter MR# Input Low Voltage MR# Input High Voltage Conditions Input leakage current < 1A Input leakage current < 1A Min 1.6 Typ Max 0.4 5.5 Units V V
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TABLE 4 MASTER RESET MR# MR# Low High Description Driving MR# low forces the processor to reset Keeping the MR# high has no effect to the CHILImodule
The MR# line is internally pulled up by 100k in the CHILImodule, so the MR# input may be left floating. There is an open drain reset output signal (RSO#) available from the CHILImodule. The RSO# signal will be driven low When main power supply (VCC) is first applied to the CHILImodule device with no backup battery When main power supply is removed in configuration with no backup battery If the backup battery voltage falls below 2.25V threshold when the main power supply is off or out of regulation If the MR# input is driven low The reset output RSO# may be used for resetting the external circuitry (peripherals etc.) of the CHILImodule. The open drain signal RSO# has weak (1M) internal pull-up to VCC_BAT in the CHILImodule. Care should be paid to not to load RSO# signal excessively.
TABLE 5 RSO# OUTPUT SPECIFICATIONS Symbol VOL(RSO#) Il(RSO#) Parameter RSO# Output Low Voltage RSO# Output High Leakage Current Conditions Iout < 1mA Min Typ Max 0.4 0.2 Units V A
The RSO# has timer that delays release until 65 ms (typ.) after the battery voltage exceeds 2.3V when the main input voltage is above 2.4V. If main input voltage is below 2.4V, when the battery voltage exceeds 2.3V, RSO# deasserts immediately with no 65 ms delay. When MR# goes low, RSO# asserts for a minimum of 65 ms. The RSO# deassert delay is minimum 61 ms over the specified temperature range.
Power Supply
The CHILImodule (CDM15400/CDM15401) operates from a single supply voltage rail. The device contains all the power management circuitry to create internally needed voltages from the main input voltage. The power supply of the module fully supports dynamical power control options of the processor to further decrease power consumption in powerdown and sleep modes. Note, as the 32kHz crystal is not connected to processor, all processor sleep modes are not supported. Please, consult Intel XScale processor documentation for further details. Lithium-Ion or Lithium-Polymer battery (4.2V) can be directly connected to the CHILImodule Professional (CDM15400) for implementing battery-powered systems. The CHILImodule Professional selects automatically external power supply input (VCC) instead of the battery, if the voltage is present for maintaining the battery capacity. The processor of the CHILImodule can resolve the automatically voltage source by reading the internal PWR_STAT signal level.
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TABLE 6 POWER SOURCE IN USE PWR_STAT Low High Description VCC input is selected as power supply (wall adapter or external power supply is supplying load current) Battery is selected as power supply (battery is supplying load current)
The power source to be used may be selected (forced) by the external signal PWR_CTL (see the table below).
TABLE 7 POWER SOURCE SELECTION BY EXTERNAL SIGNAL PWR_CTL Float Low High Description See note [2] If the VCC is present, it will be selected to supply load current. If VCC is not connected the battery is selected to supply load current Battery is forced to be disconnect from the system and VCC input is selected to supply load current [1]
[1] [2]
Only when the battery voltage is higher than the VCC voltage, will taking PWR_CTL low switch back to battery power, otherwise the VCC stays connected A 3.5 A internal pull-down current on the PWR_CTL pin will insure a logical low level input if the PWR_CTL is left floating
The VCC input voltage of the CHILImodule is continuously monitored. Two separate VCC input voltage thresholds have been defined for adjusting system response for low input voltage levels BATT_LOW# (higher threshold level) BATT_FAULT# (lower threshold level) Signal BATT_LOW# (active-low) is connected to PXA270 GPIO103, and this signal may be used to detect low input voltage levels by the software. Note, that the BATT_LOW# signal does not automatically create any system events, but desired operations may be initialized by software. Active-low output BATT_FAULT# indicates that the main power is low or has been removed from the system. BATT_FAULT# is connected to nBATT_FAULT pin of the CPU, and it indicates that the main regulator of the CHILImodule may go out of regulation due to low input voltage.
Assertion of the BATT_FAULT# signal causes CPU to enter sleep mode1 or, if CPU register PMCR[BIDAE] is set, forces an imprecise-data abort, which cannot be masked (for more
1
Note though, that the CHILImodule has no 32.768kHz oscillator available for the sleep modes, but all operation is based on 13MHz oscillator.
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information, please consult the PXA270 documentation). Once BATT_FAULT# has been asserted, the CPU recognizes only GPIO0 or GPIO1 as wake-up sources.
TABLE 8 BATT_LOW# AND BATT_FAULT# SPECIFICATIONS Symbol BATT_LOW# BATT_FAULT# Parameter VCC Input Threshold VCC Input Threshold Conditions Voltage Voltage Low Fault Min 3.51 3.02 Typ 3.6 3.15 Max 3.69 3.28 Units V V
The CHILImodule provides regulated 3.3V output voltage (VCC_OUT) for powering the surrounding circuitry. The maximum current of the VCC_OUT is 700mA. Note The 3.3V output voltage is turned off when CHILImodule device enters one of the following operating modes Reset asserted (by driving the MR# pin) Internal watchdog reset asserted Entering various sleep modes When device returns to normal mode operation, the 3.3V output is turned on again. Turning power off and on again typically resets external devices. Turning power automatically off during the sleep modes helps saving energy thus extending operation time in battery powered systems. Additionally, the VCC_BAT pin of the CHILImodule sources continuous 3.3V output for powering up the debugger interface (see later in this document). The VCC_BAT is capable of providing up to 15 mA source current. The VCC_BAT voltage is present, when the CHILImodule is powered from either VCC (primary voltage source) or Lithium battery cell. If primary voltage is disconnected, the VCC_BAT is automatically generated from battery voltage. Note, that typically debugger interface should be powered from VCC_BAT instead of the VCC_OUT, as the VCC_BAT voltage is present and independently of the CHILImodule internal power supply regulator state.
TABLE 9 VCC_OUT AND VCC_BAT SPECIFICATIONS Symbol VVCC_OUT VVCC_BAT Parameter Regulated Power Supply Output Voltage Continuous 3.3V Power Supply Output Conditions IVCC_OUT < 500mA IVCC_BAT < 10mA Min 2.97 3.2 Typ 3.3 3.3 Max 3.63 3.4 Units V V
The CDM15400 device offers integrated power management and charge monitor for the external battery. In addition to this, the CHILImodule has built-in battery charger that is capable for supplying up to 1.35A charge current to the battery from the external power supply. The CHILImodule may provide charge current while powered from the USB interface, but the charge current rate is lower because of the limitations of USB interface. Note, that the maximum allowable charge current rate depends on the system operating temperature range. Typically, maximum charge current output falls in the range of 1.0...1.35A.
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Default charge current rate depends on the power supply in use If the power is drawn from the external power supply, the CHILImodule provides 463mA default charge current If the power is drawn from the USB interface only, the CHILImodule provides 93mA default charge current depending on the application software from the connected USB bus supply voltage (VBUS). These default charge current rate may be modified with an external resistor (see chapter Li Battery Charging starting from page 52). Note, that the input voltage (VCC) should be in the range of +4.5V...+5.5V in order to be able to charge the Lithium-Ion battery.
CHILImodule CDM1540x Processor VCC (+3.5...5.5VDC) PWR_CTL 3.0V Li VUSB 3.7/4.2V Lithium Cell (for the CDM15400 only) VCC PWR_CTL RTCPWR VUSB LI+ LIGND
PWR_STAT Power Supply VCC_OUT VCC_BAT +3.3VDC/700mA +3.3VDC/10mA
Battery Charger
(CDM15400)
FIGURE 10 POWER SUPPLY OPTIONS FOR THE CDM15400 DEVICES
The CHILImodule contains real-time clock/calendar for time keeping applications. The RTC requires external 3.0V battery (for example a coin cell battery) backup to maintain the time during power-down and sleep modes.
TABLE 10 RTC_PWR SPECIFICATIONS Symbol VRTC_PWR IRTC_PWR IR_RTC_PWR Il_RTC_PWR Parameter Input Voltage RTC_PWR Current Data Retention Current Leakage Current Conditions VCC OFF; Oscillator ON VCC OFF; Oscillator OFF VCC ON Min 1.3 Typ 3.0 10 25 Max 3.7 1.4 100 100 Units V A nA nA
Note, that the RTC_PWR power supply is used for maintaining time and calendar information only if the main power supply (VCC) is not in use. Low power consumption of the real time clock allows using small size batteries for timekeeping during power-down. As an example, the lifetime of the battery (1632 type battery with 120mAh capacity) would be in a range of about 10 years, depending mainly on the temperature.
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Processor
The CHILImodule is based on low power, high performance Intel XScale processor. The main features of the PXA270 processor are Based on Intel XScale Microarchitecture with Intel Wireless MMXTM Technology 7 stage pipeline 32kB data and instruction cache Extensive data buffering 256kBytes internal SRAM (Static RAM) for high speed code or data storage preserved during low-power states Integrated hardware debug features (IEEE JTAG interface with boundary scan) Real time clock (RTC) Operating system timers Integrated LCD controller Low power (less than 500mW typical internal dissipation) Dynamic frequency and voltage management Intel XScale is capable of providing rich peripheral set for both industrial and mobile applications, including AC97 audio port I2S audio port USB Client/Host/OTG controller Three high speed UARTs (two with hardware control) FIR and SIR infrared communications port SD/MMC Card support PC Card/Compact Flash Card support Memory Stick card controller SPI bus Two I2C controllers Four pulse-width modulators (PWM) Keypad interface with both direct and matrix keys support Most peripheral pins double as GPIOs
Direct Connections from Processor

Some of the processor interfaces have been connected directly to the CHILImodule pin interface for easiness. Direct interface connections include I2C bus signals (SDA, SCK) SDIO bus signals (for direct interface to MMC/SD Card socket) USB bus signals (for direct interface to USB Client type connector) RDY signal (for fast asynchronous interfaces) The I2C bus signals are open drain type signals (SDA, SCK) for connecting external peripherals to the CHILImodule. The I2C SDA signal have been used for system recovery functionality as described in the section FPGA Recovery on page 67. The processor SDIO interface signals have not been connected to FPGA but provide direct glueless module interface for the SD/MMC Memory card connectors. The RDY signal may be utilized for fast asynchronous accesses to external devices (for example, to external Ethernet MAC/PHY devices). The RDY signal is also connected to the
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FPGA device so, that the RDY signal of the CPU may be controlled by both external device and FPGA (e.g. by FPGA IP devices).
CHILImodule CDM1540x +3.3 tPD=5ns 1 1k PXA_RDY
RDY
CPU
FPGA
FIGURE 11 RDY CONNECTIONS FOR VARIABLE LATENCY I/O INTERFACE
FLASH
The CHILImodule devices offer up to 64MBytes Intel Strata NOR Flash memory capacity for program code storage and Flash file system. The Common Flash Interface (CF) compatible Flash memory is connected to processor by 32-bit wide data bus. The initial access speed of the Flash memory is 85 ns. Synchronous burst-read mode clockto-data output delay is 17s, and asynchronous-page read cycle is 25 ns. Programming speed of the Flash is 7 s/byte (typ.). The Flash memory offers following security features for the applications 128-bit protection register 64-bit unique factory device identifier 64-bit user programmable OTP registers Additional 2048 user-programmable OPT bits Selectable OTP space in main array Individual block lock-down Block erase/program lockout during power transitions Flash memory has asymmetrically-blocked architecture with four 32kByte parameter blocks and 128kByte main blocks. The Flash memory has guaranteed minimum of 100K erase cycles per block. Flash memory has been connected to XScale PXA270 processor address space to provide following memory map for user applications.
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CDM15400
CDM15401
0xA400 0000
SDRAM 64 MBytes
0xA100 0000
0xA000 0000
SDRAM 16 MBytes
0xA000 0000
0x0400 0000
FLASH 64 MBytes
0x0100 0000
0x0000 0000
FLASH 16 MBytes
0x0000 0000
FIGURE 12 MEMORY MAP - CDM15400/CDM15401
SDRAM
For data storage and program code execution, the CHILImodule devices offer up to 64MBytes of SDRAM memory. The SDRAM memory is connected to processor by 32-bit wide data bus. The access speed of the SDRAM memory is 10 ns. For system memory map, please refer the Figure 12 Memory Map - CDM15400/CDM15401.
EEPROM
The CHILImodule contains totally 32kBits non-volatile, electrically erasable memory (EEPROM) for application software data and configuration storage. EEPROM memory has been connected to I2C bus, and the device slave address is 0x00.
REAL TIME CLOCK

The CHILImodule contains fully binary-coded decimal (BCD) real-time clock/calendar (RTC). The leap year compensation of the real time clock is valid up to year 2100.The RTC contains 56 bytes of battery-backed, non-volatile RAM memory (NVRAM) for additional data storage. An external 3.0V power supply (battery) is needed for timekeeping during the power-down (see also section Power Supply on page 15). RTC device has been connected to I2C bus, and the device 7-bit slave address is x1101000.
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FPGA
The CHILImodule device interface comprises of large Field Programmable Logic Array (FPGA) device that has great impact of the CHILImodule's flexibility and adaptability in various systems - the move from 'hard' to 'soft' design content opens up new horizons for the designer. Totally, there are 116 freely programmable I/O lines in the CHILImodule in addition to the fixed interface already mentioned. The direction, operation and functionality of these I/O lines is defined by the FPGA configuration (e.g. FPGA image), that can be loaded/updated in the CHILImodule during the boot sequence. All programmable I/O lines operate on 3.3V logic levels, except FPGA_IO002 and FPGA_IO003 that operate on 1.8V logic levels. Depending on the CHILImodule device type, there are two FPGA sizes available according to the following table.
TABLE 11 FPGA CONFIGURATIONS CHILImodule Device CHILImodule Standard CDM15401 CHILImodule Professional CDM15400 FPGA Device Altera Cyclone EP1C4 (4 kLE, up to 78 336 RAM Bits) Altera Cyclone EP1C12 (12 kLE, up to 239 616 RAM Bits)
The FPGA device of the CHILImodule forms a flexible interface between the CHILImodule internal circuitry and external peripherals. The built-in Altera Cyclone FPGA provides all the benefits of programmable logic to the system designer. Both FPGA devices (EP1C4 and EP1C12) support a variety of single-ended I/O standards such as LVTTL, LVCMOS, PCI etc. They also offer differential I/O support via LVDS and RSDS I/O standards. Each channel is capable of operating LVDS signals at up to 640 MBit/s. With up to six outputs from two phase-locked loops (PLLs) per device and a hierarchical clocking structure, Cyclone FPGAs offer extensive clock management circuitry for complex designs as well as fast and easy signal pass-through routing. By means of utilizing the configurable and programmable interface of the CHILImodule, the system developer can optionally Arrange the CHILImodule device pinout for easy and straightforward routing of base board Route the CPU resources to selected external peripherals and connectors as required by the system Control the system loading by sharing peripherals between the CPU and FPGA IP block implemented peripherals Extend or upgrade system capabilities by moving the required digital hardware into FPGA domain by means of soft IP blocks Interface custom devices directly to the CHILImodule with no glue-logic Increase performance of the system by allocating selected functionality to FPGA IP blocks (hardware acceleration) The default clock signal for the FPGA device (CLK0 = 48MHz) is generated internally in the CHILImodule. In addition to this default clocking, external clock signal can be connected to the CHILImodule.
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Note: As always with programmable devices, attention should be paid to checking the I/O configuration of the FPGA device (especially signal directions). False configuration of FPGA may prevent the CHILImodule device from booting or updating the FPGA configuration (deadlock) (see also section I2C starting on page 47). Loading CPU or other devices connected to FPGA device excessively (e.g. connecting CPU outputs to FPGA outputs) may cause permanent damages to the CHILImodule device.
I/O Standards
Altera Cyclone device I/O blocks (IOE) can support many features, including: Differential and single-ended I/O standards 3.3V, 64- and 32-bit, 66- and 33-MHz PCI compliance Output drive strength control Weak pull-up resistors during configuration Slew-rate control Tri-state buffers Bus-hold circuitry Programmable pull-up resistors in user mode Programmable input and output delays Open-drain outputs JTAG (Joint Test Action Group) boundary scan test (BST) support Cyclone device input / output element (IOE) contain a bidirectional I/O buffer and three registers for complete embedded bidirectional single data rate transfer. The VCCIO pins of the Altera Cyclone device have been internally connected to +3.3VDC. This arrangement allows the IOEs of the device to support the I/O standards described in the following table.
TABLE 12 I/O STANDARDS OF THE CHILIMODULE / ALTERA FPGA 1.5V 1.8V X[5] Input Signal 2.5V 3.3V X[1] X 5.0V X[2] 1.5V X[3] 1.8V X[3] Output Signal 2.5V 3.3V X[3] X 5.0V X[4]
[1] [2] [3] [4] [5]
With this arrangement, the VCCIO supply current will be slightly larger than expected External resistor and the internal PCI clamp diode are required for the Cyclone device to be 5V tolerant 3.3V tolerant inputs are required for the 1.5V, 1.8V and 2.5V devices. Note, that CHILImodule pins FPGA_IO002 and FPGA_IO003 use 1.8V logic levels. Cyclone device can drive a device with 5V LVTTL inputs but no 5V LVCMOS inputs Note, that CHILImodule pins FPGA_IO002 and FPGA_IO003 use 1.8V logic levels
For more information about the Altera Cyclone I/O levels and features, please consult the Altera Cyclone documentation.
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FPGA Clock Signals

There are three main options for using clocks with the FPGA device Built-in default clock of 48MHz External clock signal FPGA_CLK1 External clock signal FPGA_CLK2 The built-in default 48MHz clock signal is connected to dedicated EP1C04/EP1C12 FPGA clock input CLK0. There are two dedicated clock inputs in the CHILImodule device (FPGA_CLK1 and FPGA_CLK2) that have been connected to FPGA clock inputs CLK1 and CLK2 respectively.
GPIO
Altera Cyclone FPGA 48 MHz CLK0 FPGA_CLK1 FPGA_CLK2

External Clock Oscillator
CLK1 CLK2
FIGURE 13 FPGA CLOCK OPTIONS
Although clock signals can be connected to module via standard I/O pins of the FPGA device, using dedicated clock signal inputs (FPGA_CLK1, FPGA_CLK2) is recommended since these clock inputs drive the global clock network in Altera Cyclone device. The global clock network can provide clocks for all resources within the device (IOEs, LEs, and memory blocks). The global clock lines can also be used for control signals, such as clock enables and synchronous and asynchronous clears, fed from the external pin, or DQS signals for DDR SDRAM or FCRAM interfaces. For more information, please consult the Altera Cyclone FPGA documentation. Note also, that any FPGA I/O pin (FPGA_IO[00...115]) may be used to connect external clock signal to FPGA internal structure, but using these pins may lead to increased delays in clock signal routing.
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FPGA GPIO Specifications

The main Altera Cyclone device I/O specifications are shown in the following table. For additional information, please consult the Altera Cyclone documentation.
TABLE 13 I/O SPECIFICATIONS OF ALTERA CYCLONE Symbol II IOZ Rconf VIH VIL VOH VOL VIH VIL VOH VOL VIH VIL VOH VOL LVTTL Parameter Input pin leakage current Tri-stated I/O pin leakage current Value of I/O pin pull-up resistor before and during configuration High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Conditions VI = 0...VCCIO(max) VI = 0...VCCIO(max) Min -10 -10 15 1.7 -0.5 2.4 1.7 -0.5 2.93 1.56 -0.5 2.8 Typ Max 10 10 50 4.1 0.7 0.45 4.1 0.7 0.2 3.46 0.94 0.35 Units A A k V V V V V V V V V V V V
25
IOH < -24 mA IOH < 24 mA
LVCMOS
IOH < -0.1 mA IOH < 0.1 mA
PCI 3.3V
IOH < -500 A IOH < 1500 A
Note, that the recommended value of the I/O pin external pull-down resistor before and during configuration is 2k (max.).
FPGA Configuration Loader

The Altera Cyclone FPGA device is based on SRAM technology, and the device loses the configuration during power-down. The integrated FPGA device can be configured during system development either by Altera ByteBlaster programmer interface connected directly to the CHILImodule JTAG based production test/programming equipment However, these configurations will be lost when power supply of the device is turned off. For permanent configuration setup, the FPGA configuration shall be stored in either An external serial configuration memory or FLASH memory of the module The FPGA device may be programmed during boot-up by: Uploading the FPGA configuration from the system Flash memory to the FPGA (requires FPGA loader software) or Uploading the FPGA configuration from the external serial configuration device (requires additional configuration device) The CHILImodule comes with the built-in FPGA Configuration Loader software that is capable of loading the FPGA configuration from the system FLASH memory to FPGA device automatically before device boot-up. Therefore, no external configuration memory device is required for the system. The FPGA configuration is permanently stored in the system FLASH memory, and the FPGA configuration image may be updated from an external device (like from a memory card, Ethernet channel, serial bus) by the bootloader.
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Using External Configuration Memory

Sometimes, the system designer desires to use external configuration memory, and skip the FLASH based FPGA image storage and software based FPGA configuration concept. This requires adding an external serial configuration device to the system and using automatically FPGA configuration scheme instead as shown in the following figure. Note Using external memory device for FPGA configuration is not supported as default. Being able to use external configuration memory requires custom version of the CHILImodule. Please, consult CHILIdevices International for such a customization if needed. Typically, using built-in Flash memory and associated FPGA configuration loader software should be the most cost efficient method for FPGA configuration.
Altera Cyclone FPGA Device
FPGA_CONF_DONE FPGA_CONFIG# FPGA_CE# FPGA_DATA0 FPGA_DCLK FPGA_CSO# FPGA_ASDO DGND 3.3V
Altera Serial Configuration Device DATA0 DCLK CSO# ASDO GND VCC
FIGURE 14 CONNECTING EXTERNAL CONFIGURATION DEVICE
Serial configuration devices for the CHILImodule have specified in the following table.
TABLE 14 ALTERA SERIAL CONFIGURATION DEVICES Module Type CDM15401 CDM15400 Serial Configuration Device EPCS1 (1 MBit capacity) for EP1C4 FPGA device EPCS4 (4 MBit capacity) for EP1C12 FPGA device
Using ByteBlaster II Download Cable

The Altera ByteBlaster II download cable may be used to program the FPGA device inside of the CHILImodule. As mentioned above, note that due to SRAM technology of the FPGA, this configuration will be lost during power-down. To keep the configuration, make sure it will be stored in either FLASH memory of the module, or in external serial configuration memory device.
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Altera Cyclone FPGA Device
FPGA_DCLK FPGA_CONF_DONE FPGA_CONFIG# FPGA_DATA0 FPGA_ASDO FPGA_CE# FPGA_CSO#
Altera ByteBlaster II Connector 2 1 4 3 6 5 8 7 10 9
DGND 3.3V
DGND
FIGURE 15 CONNECTING BYTEBLASTER II DOWNLOAD CABLE
Note: For preparing your application for the external serial device or Altera ByteBlaster II download cable, please consult the documentation provided by Altera Corporation.
Module Interfaces
The following pages discuss in details of the CHILImodule interface options. Note, that in addition to the presently available interfaces wide range of custom interfaces may be implemented in the FPGA logic and IP blocks.
USB
The CHILImodule devices comply with the Universal Serial Bus Specification 1.1. The USB Client is a full-speed device that operates half-duplex at a baud rate of 12Mbps as a slave only, not as a Host or Hub controller. The USB Host controller of the CHILImodule supports the USB 1.1 specification and the USB 2.0 OTG (On-the-Go) supplement. The following USB 1.1 interface connections have been routed directly from the processor USB interface to the following CHILImodule pins USB_VBUS PXA_USBC_N PXA_USBC_P PXA_USBH_N PXA_USBH_P PXA_USBHPEN1 PXA_USBHPWR1 Note, that there are no pull-ups or pull-downs in these USB connections. The lines have been routed directly from the module BGA ball connection to the corresponding PXA270 CPU pins. The CHILImodule design allows using these lines directly for implementing USB Client interface without external transceivers (please see section APPLICATION GUIDELINES starting from page 66).
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Implementing the USB Host or USB OTG (On-The-Go) interface may require using external power switches and / or transceiver devices (see more information on section APPLICATION GUIDELINES starting from page 66).
I2C
The following I2C interface connections have been routed directly from the processor I2C interface to the CHILImodule pins PXA_SCL PXA_SDA The CHILImodule has built-in 10k pull-ups in the SCL and SDA lines. As explained elsewhere, the I2C SDA line is used as a FPGA recovery image control in the CHILImodule default configuration. Driving SDA line low during boot-up, allows system software to recover from faulty FPGA image, that could either prevent booting the device or updating a new FPGA configuration (deadlock). This system configuration may be easily overridden by custom routines. As the processor functions as a I2C bus master, the I2C data transfers will always initiated by the processor and there is no data communication during the boot time. After booting up, the I2C interface may be used as normally. External I2C devices may be connected to the I2C bus as long as external devices will not drive the SDA line low during the boot-up time.
SDIO
The following SDIO interface connections have been routed directly from the processor SDIO interface pins to the CHILImodule pins PXA_MMC_CLK PXA_MMC_CMD (internal pullup of 10k) PXA_MMC_DAT0 (internal pullup of 82k) PXA_MMC_DAT1 (internal pullup of 82k) PXA_MMC_DAT2 (internal pullup of 82k) PXA_MMC_DAT3 (internal pullup of 82k) Internal pullups have been included in the CHILImodule for design convenience to simplify MMC/SD card interface construction. Implementing the SD/MMC Card interface is straightforward. Please consult section APPLICATION GUIDELINES starting from page 66).
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WLAN (IEEE 802.11b)

The CHILImodule Professional (CDM15400) contains built-in wireless local area network (WLAN) interface including both IEEE 802.11b PHY and MAC. For antennas and antenna connector locations, see chapter Pin Diagrams starting on page 22.
TABLE 15 WLAN INTERFACE SPECIFICATIONS Specification WLAN Type Frequency Range Receiver Sensitivity (8% PER) at 11 MBit/s Data Rate Receiver Only Power Consumption Transmitter Maximum Output Power (with 15dB Adj. Gain) Transmitter Only Power Consumption (+17dBm Output) Data Rates Encryption/Decryption Values IEEE 802.11b 2400...2483.5MHz -83dBm 480mW (typ.) +17dBm 750mW (typ.) up to 11MBit/s WEP TKIP CCM AES GigaAnt 3030A6111-01 Hirose U.FL-R-SMT Comments
Integrated Antenna Type External Antenna Connector
Chip type antenna Impedance 50
For design convenience and flexibility, there are two options for using antennas with the CHILImodule Professional Integrated chip antenna (built-in the CHILImodule, default antenna) External antenna connected to the CHILImodule through miniature coaxial connector
CHILImodule CDM1540x Processor
Built-In Antenna WLAN IEEE 802.11b Coax Connector External Coax Cable Antenna
FIGURE 16 WLAN (IEEE 802.11B) INTERFACE
The CHILImodule system software and device drivers control the antenna multiplexing according to the following table.
TABLE 16 ANTENNA SELECTION (WLAN, ZIGBEE) Specification WLAN Antenna ZigBee Antenna Antenna Selection Control 0 CPU/GPIO12 1 0' CPU/GPIO13 1 External WLAN Antenna Selected Internal (Built-In) WLAN Antenna Selected External ZigBee Antenna Selected Internal (Built-In) ZigBee Antenna Selected
Note, that both internal and external antennas cannot be used at the same time.
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Integrated Antenna The built-in antenna is an easy solution for compact device construction and instant WLAN connections in light applications. Built-in antenna is surface mounted chip type antenna that provides moderate gain and operating range for the WLAN connections. Due to the limitations of small size antenna, the RF field homogenity and strength might be somewhat limited compared to the external antenna that can also used together with the CHILImodule. External Antenna There are some applications that require conductive enclosures or cases with thick walls. Since the RF field of the WLAN connection (2.4GHz) might be attenuated due to the enclosure construction, the built-in antenna might not be adequate for all applications. The CHILImodule offers coaxial connector for using external antennas with the applications that require extended operating range or flexibility in antenna selection. External antenna may be connected to the CHILImodule by means of flexible, miniature coaxial cable and the antenna type can be selected to match the application requirements. The removable cover is designed to Protect the coaxial connectors from dirt Fix the antenna connectors in their places in harsh environment (vibration, shocks etc.) Guide the coaxial cables in controllable manners to the right direction WEP Encryption/Decryption and AES Security Algorithms The CHILImodule supports both 64 and 128-bit WEP encryption/decryption for safe WLAN connections. There is also a random number generator available to assist in generation of encryption keys. In addition to WEP encryption/decryption there is support available for AES security algorithms.
ZigBee (IEEE 802.15.4)

For using the CHILImodule as a controller for the ZigBee networks the CHILImodule device contains built-in ZigBee (IEEE 802.15.4) compatible RF interface (MAC + PHY). Basically, ZigBee is a home-area network designed to replace individual sensors and controls. ZigBee was specified to offer wireless network to support low data rates, security and reliability. The ZigBee implementation would be Cost-effective Standards-based Low power ZigBee networks may be used instead of non-standard solutions (specially ISM band wireless point-to-point and network communications). The ZigBee network topology may be selected according to the application requirements as Star topology Cluster tree topology Mesh topology
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There are two types of devices in the ZigBee network: One of the network nodes should be coordinator that controls the operation of the network. Coordinator should be so called full function device (FFD). Other network nodes (reduced-function device; RFD) may have somewhat limited functionality. Simplest version of the network is star topology that requires only one FFD device.
Reduced-function Coordinator
FIGURE 17 STAR TOPOLOGY
Larger network system may be formed by cluster tree topology that requires using multiple FFD devices. There may be RFD devices in the network, but they will be connected to the system by means of FFD devices.
Coordinator Full-function Reduced-function
FIGURE 18 CLUSTER TREE TOPOLOGY
The communications speed or reliability may be further increased by the mesh topology shown in the following figure. Again, RFD devices may be connected to the network, but only by means of FFD devices.
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Coordinator Full-function Reduced-function
FIGURE 19 MESH TOPOLOGY
Normally, the RFD devices will be used to implement simple and cost-effective functions like measuring various quantities (temperature, pressure, humidity etc.) or to control external devices (lighting, heating, cooling etc.). These devices may have up to years run-time from single AA cell. As the CHILImodule is a high performance device that has the capability for functioning as a FFD or coordinator device, the CHILImodule is a natural choice for ZigBee network controller or router / gateway.
TABLE 17 ZIGBEE INTERFACE SPECIFICATIONS Specification ZigBee Interface Frequency Range Receiver Sensitivity Receiver Only Power Consumption Transmitter Maximum Output Power (in 8 Steps) Transmitter Only Power Consumption Data Rates Encryption/Decryption Integrated Antenna Type External Antenna Connector Values IEEE 802.15.4 2400...2483.5MHz -94dBm 65mW (typ.) +0dBm 57mW (typ.) up to 250kBit/s AES-128 GigaAnt 3030A6111-01 Hirose U.FL-R-SMT Comments
Chip type antenna 50 Impedance Matching
As with the WLAN interface, there are two options for using antennas with the CHILImodule Professional Integrated chip antenna (built-in the CHILImodule) External antenna connected to the CHILImodule through miniature coaxial connector (default antenna) ZigBee antenna selection is also controlled by software (see Table 16 Antenna Selection (WLAN, ZigBee). Note also, that both internal and external ZigBee antennas cannot be used at the same time.
External Batteries
There are two battery types to be used with the CHILImodule Lithium-Ion / Lithium-Polymer 4.2V rechargeable battery (for backup battery or for battery powered applications) Lithium non-rechargeable 3.0 battery (coin cell) for real time clock backup battery (for keeping the RTC in time during power-downs)
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The CHILImodule can be run from the single Lithium-Ion or Lithium-Polymer cell. The maximum cell voltage should be 4.2V (nominal voltage is 3.7V typ.). Note, that the CHILImodule does not contain any Lithium battery protection devices. For safety, please use only Lithium cell types that have built-in protection circuitry. The real time clock backup power may be provided from ordinary Lithium coin cell battery of 3.0V. If desired, the super-capacitors (capacitors with extremely high capacitance) can be provided for RTC backup instead of battery to minimize future service. For the battery connections, see also section Power Supply on page 15.
Li Battery Charging
The CHILImodule Professional fully supports external Lithium-Ion/Lithium-Polymer battery charging/monitoring. For the charging, the external power supply (VCC input of the module or the USB bus power) can be utilized. Note, that the charger operates from the nominal CHILImodule input voltages of 4.35 to 5.5V (USB bus power, external power) - if the input voltage of the CHILImodule is below 4.0V, the charger will not charge the battery. Charging may begin, when the VCC is supplied for the CHILImodule. The processor of the CHILImodule can control charger operation by driving the CHARGE_EN signal as described later. Charger operation At the beginning of the charge cycle, if the battery voltage is less than the trickle charge threshold, 3V, the charger goes into trickle charge mode and delivers approximately 50mA to the battery using a linear charger. If the battery voltage stays low for more than one quarter of the charge time, the battery is considered faulty, the charge cycle is terminated and the FAULT pin produces a logic high output. When the battery voltage exceeds the trickle charge threshold, the low rate linear charger is turned off and the high rate PWM charger ramps up reaching its full-scale constant current. When the battery approaches the float voltage, the charge current will start to decrease. When the charge current drops below the charge rate detection threshold (set via the IDET pin of the CHILImodule) for more than 5ms, charger connects a weak current source (30A typical) from CHRG# pin to ground to indicate a near end-of-charge condition. After a charge cycle is completed and if the VCC is still connected, a new charge cycle will begin if the battery voltage drops below 4.1V due to self-discharge or loading. This will keep the battery near maximum capacity at all times without manually restarting the charge cycle. Charge current and safety timer The charge current and charge time have been set to default values, but the values can be modified by external components Rcadj and Ctadj.
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CHILImodule CDM15400 Processor CHARGE_EN

ADJ_CHRG_CURR ADJ_CHRG_TIME
CAPACITY FPGAIO Li Battery Charger (CDM15400 only) FAULT CHRG
Rcadj Ctadj EN_CCHRG 3.7/4.2V Lithium Cell
EN_CCHRG LI+ LINTC
RNTC -T
FIGURE 20 BUILT-IN BATTERY CHARGER
Charge current rate may be externally controlled by combination of external resistor and control signal EN_CCHRG according to the following figure and Table 18 Charge Currents.
CHILImodule CDM15400 EN_CCHRG EN_CCHRG
0 = OFF 1 = ON
CHARGE_EN
ADJ_CHRG_CURR Rcadj
ON OFF
To Charger
12k
2k4
Supply
VUSB VCC Li Battery Charger (CDM15400 only)
FIGURE 21 CHARGE CURRENT SETUP
Values for the charge current have been summarized in the following table.
TABLE 18 CHARGE CURRENTS Specification Charging Disabled Charge Current (defaults) H Programmable Charge Current (external Rcajd connected) H L H
[1]
CHARGE_EN L
EN_CCHRG X
Charge Current 0mA 93mA 463mA See note [2]
Comments Setting internal control signal CHARGE_EN = 0 disables charging VUSB connected to battery powered system (VCC not present) System powered from an external power supply (VCC present) External resistor defines charging current
[1]
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[1]
The EN_CCHRG_CURR is an analog signal that needs to be driven to 1.8V...3.6V for ensuring correct operation. The voltage in pin EN_CCHRG_CURR shall not exceed 3.6V. Low level of the signal is < 0.5V. The programmable charge current rate depends on the Rcadj value according to the following equation. The maximum charge current (Rcadj = 0) is 1.35A.
[2]
Ich arg e =
1110 A Rcadj + 820
As the USB bus limits the available charge current to 100mA or 500mA depending on the source, the default charge current is limited to 93mA. Note also, that if CPU does not drive the CHARGE_EN (PXA270 GPIO9 high impedance), then Charging is enabled by default when VCC is connected Charging is disabled by default when the CHILImodule is running from battery and VUSB only is connected (VCC is not present) Safety timer controls the maximum charge time (charge period). Maximum time can be increased from the default value by connecting capacitor Ctadj from ADJ_CHRG_TIME pin to ground. The safety timer timeout is set as follows
Tch arg e =
C tadj + 100nF 0.0733 F
hours
TABLE 19 BATTERY CHARGING SPECIFICATIONS Specification Battery Voltage Charge Voltage Accuracy Charge Current Charger PWM Frequency Charge Time (default) Charge Timer Accuracy Trickle Charge Current Values 4.2V (3.7V nom.) 1% 1.35A max. 1.5MHz typ. 1.36 hours typ. 10 % 50mA typ. Comments Li-Ion or Li-Polymer See note [2]. See also Table 18 Charge Currents See note [1]
[1] [2]
Charge timer period may be adjusted by placing an external Ctadj capacitor from pin CADJ to DGND In typical operating conditions, the charge current should be limited to 1.0...1.35A in order to avoid excessive heating of the charger and the CHILImodule device. If operating temperature is high, decreasing current further should be considered.
Maximum charge current The maximum allowable charge current of the CHILImodule is 1.35A. However, the maximum charge current for your application depends on the operating environment (the operating temperature of your system). The charger (and the CHILImodule device respectively) generates heat depending on the charge current rate. Typically, temperature of the internal circuitry of CHILImodule will rise of +30C (1.0A charge current) and +40C (1.35A charge current) over the operating
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ambient temperature. This means, that using charge current of 1.0A, the internals of the CHILImodule device will reach about 70C in the ambient temperature of 40C. In order to prevent permanent device damages, make sure to limit the charge current to safe operating temperature range depending on your application. Note also, that the internal temperature of the CHILImodule may be read from the battery monitor device (see Battery Charge Monitoring on page 56) for controlling the charge current dynamically with the software and associated circuitry. Current threshold setting The IDET threshold (a charge current threshold used to determine when the battery is nearly fully charged) set by connecting external resistor RIDET from IDET pin of the CHILImodule to DGND. IDET threshold is 91.5 times the current delivered to IDET pin.
As the nominal voltage at IDET pin is 1.213V, the threshold current Ithreshold is
Ithreshold =
91.5 1.213V A RIDET ||1.1k
Temperature qualified charging NTC pin of the CHILImodule allows adding an external NTC thermistor for monitoring temperature of the battery cell or battery environment. Under normal operation, tie a thermistor from the NTC pin to the DGND and a resistor of equal value from NTC to VCC. When the voltage on this pin is above 0.74VIN (Cold, 0C) or below 0.29VIN (Hot, 50C), charging is disabled and the CHRG# pin blinks. When the voltage on NTC comes back between 0.74VIN and 0.29VIN, the timer continues where it left off and charging resumes. There is approximately 3C of temperature hysteresis associated with each of the input comparators. If the NTC function is not used connect the NTC pin to DGND. This will disable all of the NTC functions. NTC pin should never be pulled above VCC. Status outputs There are two charger status outputs available in the CHILImodule for driving external indicators (like LEDs) or for interfacing the signals to the rest of the system CHRG# (open drain output) FAULT When the battery is being charged, the signal CHRG# is pulled low. When the charge current drops below the IDET threshold for more than 5ms, 30A current source will be connected to CHRG# pin. When the timer runs out or the VCC power supply of the CHILImodule is removed, CHRG# is forced to high impedance state. A temperature fault will cause this pin to blink.
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If the CHRG# pin is connected to two FPGAIO pins of the CHILImodule, the software can detect three states (charging, end-of-charge and charging stopped) from this pin by using two different value resistors.
CHILImodule CDM15400 Processor CHARGE_EN FPGAIO VCC
390 k typ Li Battery Charger (CDM15400 only) CHRG INPUT OUTPUT 2k typ.
FIGURE 22 BUILT-IN BATTERY CHARGER
To detect the charge mode, configure the FPGAIO output pin high and read the signal level on the CHRG pin. The charger status output CHRG# will pull the pin low even with a 2k pullup resistor during charge. Once the charge current drops below the end-of-charge threshold, active driver of the CHRG# output is turned off and replaced by a 30A current source. The FPGIO input pin will then be pulled high by the 2k resistor connected to output. Now force the FPGAIO output pin into a high impedance state, the current source will pull the pin low through the 390k resistor. When charging eventually stops, the CHRG# pin changes to a high impedance state and the 390k resistor will then pull the pin high to indicate charging has stopped. Alternatively, you can use CHRG# output to drive a single LED to indicate charging is ON.
TABLE 20 STATUS OUTPUT SPECIFICATIONS (VCC = 5V) Symbol V(CHRG#) I(CHRG#) V(FAULT) Parameter CHRG# Pin Output Low Voltage CHRG# Pin Weak Output Current FAULT Pin Output Voltages Conditions I(CHRG#) = 5mA V(CHRG#) = 1V Low I(FAULT) = 1mA High I(FAULT) = 1mA Min 15 4.6 Typ 30 Max 0.4 50 0.4 Units V mA
Note, that using the NTC input is recommended for monitoring the temperature of the battery back in order to limit the battery charging in extremely cold or warm conditions. However, designer may select use other methods for limiting charging at the temperatures exceeding the selected Li battery specifications. In this case, the system software is responsible of controlling the CHARGE_EN signal for preventing charging in invalid conditions. Battery Charge Monitoring The CHILImodule contains an advanced battery fuel gauge device for measuring the voltage, temperature and current, and estimating available capacity of the battery cell. Cell
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characteristics and application parameters may be stored in the built-in EEPROM of the fuel gauge. The processor of the CHILImodule reads the fuel gauge to provide remaining capacity of an external battery cell for the application software. The fuel gauge is capable of automatically compensate the self-discharging of the battery cell during equipment storage periods. The built-in fuel gauge has an internal temperature sensor for measuring the ambient temperature of the system. Notice, that due to the mass and volume of the CHILImodule the temperature changes are rather slow and may not be exactly the same as the temperature of the battery cell. The temperature reading of the fuel gauge may deviate from the temperature of charger chip or other internal components. Using a device driver allows you for example to read the temperature from the fuel gauge device and to control the battery charging according to the internal temperature of the CHILImodule.
System Clocks
The CHILImodule contains clock generators and oscillators for internal circuitry, so no external system clock signals are required for correct operation either for the CPU or FPGA devices. All the mandatory clock signals including the real time clock signals have been generated and utilized internally. As default, the FPGA device of the module uses an internal 48MHz clock signal. However, the FPGA device can also use the external CLK1 and CLK2 clock signals as described earlier.
JTAG/Debugging (PXA270)
The following boundary scan (JTAG; IEEE 1149.1) signals from the XScale PXA270 processor have been connected directly to the CHILImodule pins PXA_TRST# PXA_TMS PXA_TCK PXA_TDO PXA_TDI In addition to these lines, the open drain reset signal (RSO#) has been connected to the CHILImodule pins. As the CHILImodule is factory pre-tested, there should be no need for internal testing of the device after manufacturing. However, there are two options for utilizing the JTAG interface Production test for the complete system (driven by the boundary scan device connected to the CHILImodule) Software debugging during the development process
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PXA_TMS PXA_TRST#
Intel XScale PXA270
PXA_TCK PXA_TDI PXA_TDO RSO#
Altera Cyclone FPGA
FPGA_TMS FPGA_TCK FPGA_TDI FPGA_TDO
FIGURE 23 BOUNDARY SCAN CONNECTIONS
Providing standard headers to connect debugger and/or boundary scan controller to the system is recommended. The pinout of the boundary scan/debugger connector depends on what tools will be used during the system development and manufacturing tests. Some adapter may be needed to connect various tools to the system. The recommended ARM/JTAG Tools connection for the external debugger (like ARM compatible Lauterbach Trace32) is shown in the following figure.
CHILImodule Power Supply 3.5...5V
CPU JTAG Interface
VCC
VCC_BAT
+3.3VDC
+3.3VDC DGND
+3.3VDC PXA_TRST# PXA_TDI PXA_TMS
2 +3.3VDC DGND DGND DGND DGND DGND
CPU_TCK CHILImodule CDM1540x
TCK MR# 10k RST# VCC 200R 68R 100p TMS TRST# TDI TDO RSO#
CPU_TMS CPU_TRST# CPU_TDI CPU_TDO CPU_RSO#
MAX811SEUS
PXA_TCK
22R
PXA_TDO RSO#
DGND DGND DGND
Optional components for some ARM compatible debuggers
DGND 19 20
FIGURE 24 EXTERNAL DEBUGGER INTERFACE
Note, that the Lauterbach Trace32 works without the optional components marked in the figure above. The recommended connector pinout for the external JTAG controller (like JTAG Corporation systems, see www.jtag.com) is shown in the following figure.
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+3.3V +3.3VDC DGND 3k AWR TCK 68R 100p TMS TRST# TDI TDO 22R
1 TRST# TDO TDI TMS TCK VPP# AWR User0 RDY/BUSY User1 19 20 2 DGND DGND DGND DGND DGND DGND DGND DGND DGND +3.3VDC
+3.3V
FIGURE 25 EXTERNAL JTAG CONTROLLER INTERFACE
The JTAG Corporation AWR (Auto-Write) signal may be utilized in FPGA logic, if system designer wishes to implement customized routines in FPGA. Typically, AWR signal will be left unconnected.
JTAG/Debugging (FPGA)
The following boundary scan (JTAG; IEEE 1149.1) signals from the Cyclone FPGA have been connected directly to the CHILImodule pins FPGA_TMS FPGA_TCK FPGA_TDO FPGA_TDI As the CHILImodule is factory pre-tested, there should be no need for internal testing of the actual CHILImodule device after manufacturing process. However, there are two options for utilizing the FPGA JTAG interface Production test for the complete system (driven by the boundary scan device connected to the CHILImodule) FPGA configuration programming during the development process See the Figure 23 Boundary Scan Connections for the FPGA IEEE 1149.1 connections.
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Absolute Maximum Ratings

Note: Stresses beyond those listed under 'Absolute Maximum Ratings' may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these and any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum ratings conditions for extended period may affect the device reliability.
TABLE 21 ABSOLUTE MAXIMUM RATINGS Symbol VCC V(CHRG#, FAULT#, ACPR#) VPWR_CTL VBAT VUSB_VBUS VRTC_PWR IBAT IVCC_OUT IVCC_BAT PXA_IOIOUT PXA_IOVIN FPGA_IOIOUT FPGA_IOVIN VIL, IH TA TASTG TSOLDERING Parameter Input Voltage Battery Charger Status Outputs (CHRG#, FAULT, ACPR#) Power Control Input Voltage Lithium-Ion/Lithium-Polymer Battery Voltage (Cell Voltage) USB Bus Voltage Real Time Clock Backup Battery Voltage Battery Charge Current [1] Regulated Power Supply Output Current Continuous Regulated Power Supply Output Current PXA270 I/O pin output current [2] PXA270 I/O pin input voltage [2] FPGA GPIO pin output current [3] FPGA GPIO input voltage [3] All I/O Lines Except the FPGA_ and PXA_ I/O Operating temperature Storage temperature Lead temperature Conditions Min -0.3 Typ Max +6.0 +6.0 Units V V
-0.3
+36 +6.0 +7.0 +6.0 1.3 700 15
V V
-0.3 Limited/set by an external resistor Rcadj
V A mA mA mA V mA V V C C C
-5 -0.3 -25 -0.5 -0.3 -25 -50 Soldering, 10 s
+5 +4.0 +25 +4.6 +5.5 +85 +85 +300
[1] [2] [3]
Built-in thermal shutdown and short circuit current protection. Note, that the maximum charge current depends on the ambient temperature. Apply to all signals connected directly to the PXA270 device (signals with the prefix PXA_) Specification apply to all signals connected directly to the FPGA device (signals with the prefix FPGA_. Signal PXA_RDY connects directly to FPGA device)
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Recommended Operating Conditions

Recommended operating conditions for the CHILImodule (CDM15400, CDM15401) have been expressed in the following table.
TABLE 22 RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Input voltage for operation Input voltage for charging VRTC_PWR VUSB_VBUS TA TASTG TSOLDERING Real time clock backup battery voltage USB Bus Voltage Operating temperature Storage temperature Lead temperature Conditions Battery disabled Battery enabled charging charging Min +3.5 +4.5 +1.3 +4.25 -25 -50 Soldering, 10 s Typ Max +5.5 +5.5 +3.7 +6.5 +70 +85 +300 Units V V V V C C C
Electrical Characteristics
Electrical characteristics TA = 0C to +70C, unless otherwise notified. Typical values are at TA = +25C. VCC = +4.5...+5.5V.
TABLE 23 MODULE ELECTRICAL CHARACTERISTICS Symbol V(CHRG#) I(CHRG#) V(EN_CCHRG) V(FAULT) VBAT VUV VUV VIHPWR_CTL VILPWR_CTL PXAVIH PXAVIL PXAVOH PXAVOL VVCC_OUT VVCC_BAT S48MHz f48MHz A48MHz J48MHz tr, tf Parameter CHRG# Pin Output Low Voltage CHRG# Pin Weak Output Current Charge Control Voltage FAULT Pin Output Voltages Regulated Battery Float Voltage Charger VCC Undervoltage Lockout Voltage Charger VCC Undervoltage Lockout Hysteresis PWR_CTL Signal Input High Voltage PWR_CTL Signal Input Low Voltage PXA270 Input High Voltage PXA270 Input Low Voltage PXA270 Output High Voltage PXA270 Output Low Voltage Regulated Power Supply Output Voltage Continuous 3.3V Power Supply Output Symmetry of the 48MHz Internal Clock Signal Frequency of the 48MHz Internal Clock Signal Accuracy of the 48MHz Internal Signal Jitter of the 48MHz Internal Clock Signal Rise and Fall time of the 48MHz Internal Clock Signal Conditions I(CHRG#) = 5mA V(CHRG#) = 1V Low High Low High Min Typ Max 0.4 50 0.5 3.6 0.4 4.2 4.24 2 2.82 Units V mA V V
15
30
1.8 I(FAULT)=1mA I(FAULT)=1mA 4.6 4.158 2.7V 100 0.9
V V mV V
VCC Rising
0.35 2.5 1.1 IOH < -3mA IOL < 3mA IVCC_OUT < 500mA IVCC_BAT < 10mA 2.8 2.97 3.2 30/70 48.0 -200 -20 +20 0 +20 15 3.3 3.3 0.3 3.63 3.4 70/ 30
V V V V V V V % MHz ppm ps ns
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Symbol VOL(RSO#) Il(RSO#) VIH(MR#) VIL(MR#)
Parameter RSO# Output Low Voltage RSO# Output High Leakage Current MR# Input High Voltage MR# Input Low Voltage
Conditions Iout < 1mA
Min
Typ
Max 0.4 0.2 5.5 0.4
Units V A V V
Input leakage current < 1A Input leakage current < 1A
1.6
Package Outline
The CHILImodule device has the following characteristics: Ball pitch 2.0 mm Ball diameter 1.27 mm The CHILImodule device is packaged in a 46.5-by-70.5 mm, 324-pin, 2.0 mm pin pitch BGA (Ball Grid Array) package as shown in the Figure 26 The CHILImodule 324-Pin Package. Pin 1 corner of the device is marked by a dot in the CHILImodule package. Pin numbering (1...324) of the package has been defined in the Figure 26. Refer to Table 24 The CHILImodule Package Information for package configuration information for Figure 26. See also the guidelines later in this document for detailed information about solder pad design application board design assembly/solder process
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FIGURE 26 THE CHILIMODULE 324-PIN PACKAGE
The specifications of the package are shown in the following table.

TABLE 24 THE CHILIMODULE PACKAGE INFORMATION Dimension Package Height BGA Ball Height Package Body Thickness BGA Ball Diameter Bottom Package Body Width Bottom Package Body Length Pitch Outer Ball (Lead) Column Distance Outer Ball (Lead) Row Distance Ball (Lead) Count Corner to Ball 1 Distance Along D and E Center to Mounting Screw (hole center) Center to Mounting Screw (hole center) Symbol A A1 A2 b D E e e1 e2 N L1 L2 L3 Min Typ 11.9 1.27 10 1.27 46.5 70.5 2.0 36.0 60.0 324 3.8 17.0 29.0 Max Units mm mm mm mm mm mm mm mm mm mm mm mm
45.5 69.5
47.5 71.5
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TABLE 25 THE CHILIMODULE PACKAGE PROPERTIES Item Printed Circuit Board Enclosure Mold Compound Solder Balls Package Label Material FR-4/RCC, NiAu Coating PPS (Polyphenylene Sulfide), Black Two Component, Elastomeric, Un-filled Polyurethane SnAgCu Polyimide Film
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ADDITIONAL INFORMATION
Chemical Content
CDM1540x devices are RoHS 2006 compliant and lead free.
Contact Information
For additional information, please visit http://www.chilidevices.com For sales office addresses, send e-mail to sales@chilidevices.com
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APPLICATION GUIDELINES
Application Examples
Getting Started with the CHILImodule
To be fully functional, the CHILImodule Standard (CDM15401) Professional (CDM15400) devices require only a power supply. or CHILImodule
Typically, the supply voltage of 5VDC is applied to the device's VCC and DGND connections. The Lithium-Ion or Lithium-Polymer battery may be connected to the CHILImodule in order to provide backup power supply during external supply power-downs. The CHILImodule contains power supply circuitry that even allows system to run from the battery in case of mobile equipment. If supply voltage is in the range of 4.5...5.5VDC, the external main power supply may also be used for charging the battery. In addition to the power supplies, the real time clock backup battery (3V) or super-capacitor would typically be added to the system configuration for maintaining time and date information during power-down modes (when neither the main power supply or Lithium battery are not connected). Although the CHILImodule devices contain built-in power supplies for generating all internal voltages, it is recommended to provide an external regulator or similar and associated protection devices for the CHILImodule power supply in order to avoid voltage dips and damages due to ESD transients and surges. As the CHILImodule Professional device contains wireless interfaces (ZigBee, WLAN), it may be used as stand-alone system without any other peripherals or connections. However, typically an application requires adding some external peripherals or connectors to the system for connecting system to other devices or networks to complete the design.
+3.3V
+5VDC RTC_PWR 3.0V Binary I/O
RS232
WLAN
FIGURE 27 EXAMPLE OF SIMPLE SYSTEM
+5VDC RTC_PWR 3.0V Li+ 4.2V/1100mAh Binary I/O
+3.3V
RS232
CHILImodule Standard
FIGURE 28 ADDING LI+ BATTERY TO THE SYSTEM
It is also recommended, that the system designer will providing a connector for the PXA270 processor boundary scan/JTAG interface for connecting an external software debuggers to the system during software development.
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+5VDC RTC_PWR 3.0V Binary I/O
IEEE 1149.1 (PXA270) USB
FIGURE 29 ENABLING BOUNDARY SCAN/JTAG DEBUGGER
FPGA Recovery Image

As explained previously, almost all the internal system signals have been connected to the built-in FPGA device, and the FPGA I/O pins form mainly the external interface of the CHILImodule. Because the FPGA is a totally programmable device, attention should be paid to device configuration design and test. Three system components need to be designed to work correctly together Bootloader software (that configures processor I/O pin functions and pin directions and loads the software from the booting device) FPGA device configuration (that determines the FPGA I/O pin functions and pin directions) Application software and drivers (that may alter the processor pin functions and pin directions at run time) There are two possible errors in the system configuration that may lead to either system hang-up or damage: First, user may select to use a boot device that will be interfaced directly to the FPGA I/O interface of the CHILImodule (for example Compact Flash/PCMCIA). If user then uploads a FPGA configuration that fails to enable the boot device interface for the software, the system will not be able to upload new configuration from that point forward. Secondly, there may be severe signal/bus conflicts due to misconfiguration of the either processor registers or FPGA I/O. Processor I/O pins that have been set to outputs may drive FPGA pins that also have defined as outputs resulting excessive power consumption and/or even device damages. Note: Excessive loading of CPU and/or FPGA due to misconfiguration in either FPGA or processor pin configuration may lead to permanent damage of the device. Following precautions should be taken into consideration Make sure that the FPGA synthesis tool defines unused FPGA pins as inputs or highimpedance (disabled) outputs (driving unused pins to either high or low may load the processor pins) Make sure that the FPGA pin configuration is correct to guarantee right interface between the processor and the FPGA device Make sure that the bootloader software configures the processor pin functions and directions according to your actual FPGA configuration Make sure your application will not override the processor I/O configuration during run time
If you use boot device that interfaces directly to FPGA I/O pins, it is recommended to
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Provide a FPGA recovery configuration Provide some way to control whether the system uses normal FPGA image or the FPGA recovery image Note: The default CHILImodule software uses the I2C SDA line to control whether to select normal FPGA configuration (a.k.a FPGA image) or recovery configuration (a.k.a FPGA recovery image): Should the SDA line be driven low during the boot-up sequence of the CHILImodule, the recovery image is uploaded to FPGA device Should the SDA line be left floating (pulled-up internally in the CHILImodule) during the boot-up sequence, the normal FPGA image is uploaded to FPGA device Note: The SDA line should be driven low for minimum of 500ms during the power-up in order to select the recovery image.
FPGA Recovery Image FPGA Image
SDIO
SD/MMC Card Slot
Intel XScale PXA270
SCL SDA
To I2C Devices
Use_Recovery_FPGA
FIGURE 30 USING SDA AND MEMORY CARD FOR FPGA IMAGE CONTROL
MMC/SD Card Interface

The CHILImodule contains a MMC/SD/SDIO controller that has two modes of operation MMC/SD/SDIO Mode (supports MMC, SD and SDIO Card communication protocols for data transfers. Note that only one protocol is active at a time) SPI Mode (provides capability to communicate with MMC, SD Card and SDIO Card devices) The CHILImodule provides a glueless MMC/SD Card interface for the system designer. Designer may select using either SD Card or MMC Card in the system (SD or MMC protocol), depending on the requirements and software driver availability.
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+PWR
GPIO
3.3 Opt. Regulator
+3.3V
SD Card Socket VCC COMM GND CLK CMD
MMCCLK MMCCMD Intel XScale PXA270 MMCDAT0 MMCDAT1 MMCDAT2 MMCDAT3 GPIO GPIO
100k 100k
DAT0 DAT1 DAT2 DAT3 WP CD
NOTE: Pullups or pulldowns depending on COMM pin connection
FIGURE 31SD / SDIO INTERFACE
All the pull-ups or pull-downs (CD) should be in range of 10k...100k to prevent bus floating. The write protection signal (WP) can be pulled-down with any value sufficient to prevent bus floating. Placing 100nF capacitor as close as possible to the MMC card socket pins (VCC and GND) is recommended. Note also, that the COMM signal is optional and not required by the SD/SDIO card specifications), so some card sockets may not have this signal. When a SD/SDIO device is inserted to the socket, the CD signal will be connected to the COMM signal using mechanical switches inside the socket. Write protect tab is optional for the SD/SDIO device. Depending on the position of the tab, the WP signal is either connected or not connected to COMM signal. Therefore, a rising edge will occur in WP signal when the SD card or optionally SDIO card is in the write protect position. The WP signal remains low when the write protect tab is in read/write position. The mechanical CD switch of the socket generates a rising edge signal on CD line, when a device is inserted in the socket. Write protect (WP) and card detect (CD) signals should either have de-bounce circuitry, or the signals should be handled correctly by the software.
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FIGURE 32 EXAMPLE OF THE SD CARD INTERFACE (COMM PIN CONNECTED TO DGND)
Note, that the COMM pin of the card socket may be optionally connected to DGND or VDD pins of the socket. The pull-up or pull-down resistors shall be connected accordingly. The SDIO interface may operate in 1-bit or 4-bit mode, or with SPI bus based communications. The maximum data rate for 1-bit SDIO and SPI interface is 19.5MBit/s and 78MBit/s for 4bit SDIO interface. To satisfy the interface requirements, Provide clean +3.3V power supply for the memory card socket Make sure that there is a short circuit protection in the power supply output (to protect your system from being shorted or damaged by defective MMC/SD Card) In addition to this, it is recommended to provide ability to power down the MMC/SC Card socket without having to power down the 3.3V main regulator of the system. The system designer determines whether to implement a dedicated regulator or simple pass-transistor for supplying 3.3V for the card socket. If only MMC protocol will be used, the minimum configuration (see the following figure) can be used. Note, that typically MMC card interface will be slower than SD card interface due to 1-bit data bus width (compared to 1-bit or 4-bit data bus widths with SD cards).
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+PWR
GPIO
+3.3V 3.3 Opt. Regulator
MMC Card Socket VDD VSS1 VSS2 CLK CMD
MMCCLK MMCCMD Intel XScale PXA270 MMCDAT0 MMCDAT2/MMCCS0
DAT0 CS (for SPI Mode)
FIGURE 33 MMC CARD INTERFACE
Placing 100nF capacitor as close as possible to the MMC card socket pins (VDD and VSS1) is recommended. Note, that MMC card socket is not equipped with card detect switch/signal, so the card should be detected by means of software application. Use SD card socket if card detect and write protection signals are required by the application.
USB Client Device Interface

Implementing an USB Client device with the CHILImodule is straightforward (see following figure).
Battery Charger Intel XScale PXA270 GPIO

Signal level adj. 3.3 5 +3.3V Opt. 1.5k
USB Client Connector (Type B Connector) VBUS (+5V) GND
USBC_P USBC_N
USB D+ USB D-
FIGURE 34 USB CLIENT DEVICE INTERFACE
Some designs use the optional 1.5k pull-up in the D+ line to indicate host controller that a fast USB client device is connected per Universal Serial Bus Specification, Revision 1.1. If GPIO pin of the CHILImodule is used for monitoring the bus voltage (VBUS), the voltage level of +5V needs to be reduced to 3.3V voltage range before connecting to the CHILImodule pin.
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Notice, that the USBC_P and USBC_N (D+ and D-) form a differential pair. Follow these layout guidelines Route D+ and D- signals close to each others as parallel traces on the printed circuit board Match the trace lengths as closely as possible (within 0.5 inches or 12.7 mm)
USB Host Controller Interface

The CHILImodule may be used to implement simple USB Host controller application (see the following figure). The external voltage switch (or regulator) may be controlled by the USBHPEN1 signal. Correspondingly, the voltage switch/regulator status should be monitored by the USBHPWR1 signal. Notice, that the USBH_P and USBH_N (D+ and D-) form a differential pair. Follow these layout guidelines Route D+ and D- signals close to each others as parallel traces on the printed circuit board Match the trace lengths as closely as possible (within 0.5 inches or 12.7 mm)
+5V USB Host Connector (Type A Connector) +5V VBUS (+5V) GND
USBHPEN1 USBHPWR1 Intel XScale PXA270

FAULT
USB Power Switch
USBH_P USBH_N
2 x 10...25
Optional Termination, Filtering and ESD Protection USB D+ USB D -
2 x 68..75pF Locate as close as possible to the device ball pins
2 x 15k
FIGURE 35 USB HOST DEVICE INTERFACE
The RC filters of the USBH_P and USBH_N lines are required by the USB Host controller for the USBH_P and USBH_N signal compliance with the USB specification. These components should be placed as close as possible to the CHILImodule ball pads. The resistive 15kOhm pull-downs for the USBH_P and USBH_N are required by the USB specification. The USB power supply must be +5V (as stated in the USB specification). Note, that the USBHPEN1 and USBHPWR1 signals are 3.3V logic signals, and they should be interfaced to the external power switch or regulator signal levels as applicable. Termination, filtering and ESD protection requirements depend on the application. However, implementing this circuitry is recommended for signal integrity and system protection. Note, that USB Host controller may be implemented also with the external USB transceiver circuitry.
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Application Notes
Using Custom Clock Frequencies with FPGA
The built-in FPGA device (Altera Cyclone) uses clock inputs CLK0, CLK1 and CLK2. The default clock signal CLK0 is always available, and the frequency of the CLK0 signal is 48MHz. The external clock signals may be used for Implementing high-speed IP functions Implementing custom IP blocks that require special clock frequencies User may optionally provide external clock signals CLK1 and/or CLK2 by connecting clock signal to the CHILImodule clock inputs (FPGA_CLK1 and FPGA_CLK2 respectively).
Using External Antennas

Some embedded devices and systems may utilize the built-in antennas of the ZigBee and WLAN interfaces. There are also applications that could benefit from using external antennas: some applications may require heavy, conductive shielding or sealing (enclosure) that suppresses the RF field of the built-in antennas. Using external antenna could also increase the operating range due to better antenna gain or due to fact that antenna could be located to better position (enclosures, walls, other equipment etc.). There are miniature RF connectors for both ZigBee and WLAN antennas of type U.FL (Hirose). The impedance of the antenna connections is 50. The antenna connectors locate under the removable top cover of the CHILImodule device package. The top cover fixes the connectors in their places, and also guides the antenna cables to the right directions.
Lithium Battery Considerations

The CHILImodule can run from a single 4.2V Lithium-Ion (Li-Ion) or Lithium-Polymer (LiPol). Lithium cells are somewhat different compared to the NiCd and NiMh cells. Lithium cells require a dedicated charger to control charge and discharge of the cell Lithium cells do not tolerate overcharge Lithium cells do not tolerate over-discharge (usually, the cells should not be discharged below 2.5V cell voltage to prevent permanent damages) The maximum charge current of the Lithium cell should be C/2 Lithium cells do not suffer from memory effect - they do not need to be cycled periodically in order to maintain capacity The energy density by weight and volume of the Lithium cells is superior The self-discharge of the Lithium cells is typically round 10% per month. The working lifetime of the Lithium cells is typically 3 years from the day of manufacture. Most of the Lithium cells are sold with the built-in safety and protection circuitry to prevent both over-charging and over-discharging. Additionally, the protection circuitry may offer protection for over-heating, short circuits etc. It is recommended to study carefully the
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Lithium cell specifications before either using the cell in prototypes or selecting battery cell for production equipment. Note, that incorrect battery usage may lead to leakage of battery fluid, a bursting of the battery, or ignition of the battery. To prevent such accidents, observe the following precautions: Do not short circuit the battery cell Do not disassemble or modify the battery cell Note that the temperature range over which the battery can be charged is typically 0C (32F) to 45C (113F) - charging battery at temperatures outside of this range may cause severe damage to the battery or may reduce its life expectancy Note that the temperature over which the battery can be used is typically -20C (-4F) to 60C (140F) - use of the battery outside of this temperature range may damage performance of the battery or may reduce its life expectancy Note that the battery capacity may be reduced in cold conditions The Lithium cell specifications vary to some extent depending on the manufacturer and the type of the Lithium cell - check the specifications of the specific cell you are going to use in your system. The charger of the CHILImodule is capable of charging the lithium battery up to its full capacity with the maximum charge current of 1.35A, depending on the ambient temperature.
Cell Voltage (V) Cell Voltage 4 Capacity 100 Capacity (%)
50
1 Charge Current 1 2 3 4
Time (hours)
FIGURE 36 TYPICAL LITHIUM CELL CHARGE PROFILE
The available capacity of the Lithium cell depends on the temperature. Thanks to the builtin temperature sensor of the CHILImodule battery charger, the module software is able to compensate/calculate the actual capacity to some extent.
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Cell Voltage (V) 4.2V 4 +45C 3.5 0C -20C 3
2.5 Capacity (%) 50 100
FIGURE 37 EXAMPLE OF THE LITHIUM CELL CAPACITY VS. TEMPERATURE
Note thought, that since the temperature measurement locates on the module, the temperature reading may be different from actual battery cell temperature. This may limit temperature compensation accuracy in some applications.
Using External Ethernet Devices

In addition to the FPGA / IP Ethernet MAC, an external MAC+PHY device may be connected to the CHILImodule. Interfacing the Ethernet MAC + PHY device (like SMSC LAN91C111) to the CHILImodule is straightforward.
FIGURE 38 EXTERNAL ETHERNET MAC + PHY
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Note, that the external MAC + PHY device connects to the parallel data and address busses of the CPU via FPGA device and therefore it reserves large amount of FPGA I/O pins for the device connection.
Using External CAN Devices

Controller Area Network (CAN) interfaces may be built by using either FPGA/IP block or external CAN transceiver. CAN is a control network protocol from Bosch that has found wide use in industrial automation and automotive industry. Note, that most of the patents of CAN bus are owned by Bosch, and there are no restrictions on developing and using an open source CAN IP. However, the protocol license from Bosch is an indispensable prerequisite of any commercial use of the protocol. Using an external transceiver with the CHILImodule for implementing the CAN interface is easy (see the following figure).
FIGURE 39 USING EXTERNAL CAN TRANSCEIVER
System Debugging and Driver Development Guidelines

Thanks to the dense design of modern electronics, the system debugging, measuring and software device driver development may be tough task. Typically, some of the circuit nodes may be inaccessible and there are only few points for connecting measurement equipments (oscilloscopes, logic analyzers etc.). Using spare pins and logic gates of the CHILImodule FPGA device may help sometimes... Connecting few spare pins of the CHILImodule FPGAIO to a simple pin header allows routing (or 'mirroring') desired signals to the pin header for further connecting them to measurement device. Similarly, you may wish to use signals connected to header for controlling directly your external device via FPGA logic. Programmable logic of the CHILImodule device often allows you to use novel methods for system debugging without needing to solder any extra wires or connectors to your board.
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Boot Device Selection Guidelines

System designer may select using the MMC/SD Card as a boot device. This card interface uses the SDIO peripheral of the processor. The SDIO interface will always be available, and these lines have not been connected to the FPGA device. That way, the FPGA misconfiguration cannot prevent the software to access the boot device. If system designer ends up using a boot device that interfaces to FPGA I/O pins of the CHILImodule, the designer will be instructed to provide FPGA recovery control to the system (like the I2C SDA signal grounding) FPGA recovery image (to reverse to working FPGA configuration in case of FPGA design error)
Printed Circuit Board Design Guidelines

Base Substrate Selection
All the high density design details and extremely fast interconnect signals have been hidden inside of the CHILImodule device for making the base substrate selection easy. Many times, standard low-speed peripheral interconnections (like signals to/from a serial port etc.) are all that is needed. For case of simplicity, normal 1.6 mm FR-4 base substrate material is cost efficient and reliable selection for most of the designs. As with all layout designs, care should be paid into balancing the printed circuit board copper areas and wiring on the boards equally to avoid extensive PCB warping.
Land Pattern Recommendations

CHILIdevices recommends non-soldermask defined (NSMD) pads for use with the CHILImodule devices.
Copper Pad PCB - Substrate Solder Mask Defined Pad (SMD)
Copper Pad PCB - Substrate Non-Solder Mask Defined Pad (NSMD)
FIGURE 40 PAD STYLE DEFINITIONS
The requirements for the base substrate design are quite relaxed. Commonly used FR-4 laminate should be fine for the CHILImodule in most cases. A recommendation for the device land pattern is described in the following figures.
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CHILImodule
BGA Solder Ball (SnAgCu) Electroless Nickel / Immersion Gold (NiAu) Copper Pad Solder Mask PCB Substrate (FR-4)
1.0 mm 0.125 mm
FIGURE 41 PADSTACK RECOMMENDATION
Land pattern for the CHILImodule package shall be designed according to the package dimensions (see Figure 26).
Pin 1 Package Outline (Do not install any components inside of this area)
Top View
Non-Plated Through Hole D=3.0 mm (2 pcs)
FIGURE 42 PACKAGE LAYOUT PATTERN
Ensure to include two non-plated through holes (diameter of 3.0 mm) into your application board design. Most assembly processes benefit from assembling the CHILImodule to application board in separate phases. These phases include The two non-plated holes are used for mounting and fixing the CHILImodule parts to your application board.
Escape Pattern for CHILImodule

The pad pitch of the CHILImodule is large (2.0 mm), so there are no special escape pattern requirements. Routing signals from the device pads is easy even with moderate via sizes. There are no high density interconnect (HDI) rules to follow, nor there are no special requirements for the base substrate layer count. For most designs, a typical 4-layer printed circuit board should be adequate.
Layout Guidelines
The actual pinout of the CHILImodule can be quite freely selected, thanks to the FPGA device built-in the CHILImodule.
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For efficient base substrate design, see the device pin out (Figure 2 Pin Diagram on page 21). All interfaces (signal, power and ground pads) of the CHILImodule devices have been grouped to help the designer to create layouts fast and easy. The I/O connectors of the system can be placed on the base substrate according to the system / embedded device requirements and specifications. When the initial placement of the connectors and interfaces is done, the CHILImodule is placed on the layout. Finally, the CHILImodule pinout is designed to allow easy routing and short trace lengths. Note, that in the CHILImodule there are some fixed interfaces in addition to the freely programmable FPGA I/O pins (power supply and battery connections, SDIO and I2C interface etc.). Implementing and placing these connections and utilities should be taken into consideration before laying out other devices. Also, fast and critical signals (external FPGA clock signals, interrupt signals etc.) should be routed before other connections. All ESD protection devices should be placed close to the adjacent connectors and interfaces. Typically, ESD devices should be tied to the embedded device chassis ground to provide low impedance return path for large transient currents.
Via Design
The I/O pin count of the CHILImodule package is high to support extensive connection capacity for the applications. However, due to the low-density (2.0 mm pitch) pin design of the CHILImodule, routing the base substrate is easy and straightforward. In addition to relatively coarse pitch, most of the I/O pins may be programmed (FPGA) to help to make the base substrate even less difficult to route. The cost effective vias of 1.0 mm pad diameter and 0.5 mm finished drill hole size should be sufficient for most designs.
1.25 mm Copper Pad 1.0 mm Opening in Solder Mask Via (1.0/0.5 mm) 2.0 mm
FIGURE 43 LAND PATTERN AND VIA DESIGN
Since there are only four rows / columns of pins in the package, designing the escape pattern for routing is easy compared to the fine pitch BGA packages. Note: There are passive components installed at the bottom of the CHILImodule device. In order to avoid short circuits, please ensure, that all copper objects (including printed circuit board traces and via pads) are covered with solder mask/solder resist under the device.
PCB Finish
The CHILImodule packages may be used on a variety of printed circuit board finishes as immersion gold (NiAu) or organic surface protective (OSP).
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CHILIdevices recommends using immersion gold finish with CHILImodule devices due to NiAu flat surface and high co-planarity.
Paste Stencil Design

The CHILImodule can be considered as normal surface mounted component. The stencil opening for terminal pads of the CHILImodule should be undersized compared to substrate pad size to avoid printing paste over the solder mask.
0.1 mm 0.15...0.20 mm Copper Pad Paste Stencil Solder Mask PCB Substrate (FR-4)
FIGURE 44 PASTE STENCIL RECOMMENDATION
Note, that the paste stencil thickness depends on the other devices on the substrate in addition to the CHILImodule requirements.
Assembly Guidelines
General
The CHILImodule is delivered as tested complete component (the two internal boards installed inside of the enclosure, and fixed with two screws). Although this package could be installed in single reflow process, we strongly recommend executing the assembly in the phases shown in the following figures. This will help you to better control the reflow temperature profile as well as reduces the stress of the CHILImodule. Unpack the Module First, unpack the CHILImodule components just before assembly process. Note the moisture preconditioning information on page 82. Open the two screws located at the bottom of the CHILImoduledevice, unmount the enclosure and separate CHILImodule base board and radio board. Solder Base Board to the Application Board Install CHILImodule base board (manually, or with pick-and-place machine) to your application board after applying solder paste.
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Ensure to position base board correctly on your application board (notice the pin 1 location, see also Figure 26 The CHILImodule 324-Pin Package on page 63).
Pin 1
FIGURE 45 BASE BOARD
Reflow solder the CHILImodule base board along with the rest of your application board components following the guidelines starting at page 83 (solder paste, reflow profile). You may also rely on own experience for finding the correct temperature profile for the reflow oven you are using.
STEP 1
Solder CHILImodule Base Board to Application Board (Standard Reflow Process)
Insert Radio Board After successful reflow soldering of your application board you may snap the CHILImodule radio board into its position (surface mounted connectors). You can now test the whole assembly using boundary scan methods, if needed. Or you may choose to test the assembly later.
STEP 2
Insert CHILImodule Radio Board (Connectors)
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Mount Enclosure Next step is to insert the plastic enclosure into its position.
STEP 3
Insert Module Enclosure (Case)
Insert the two screws to the bottom of the CHILImodule (through the application board holes).
STEP 4
Insert Screws (2 pcs) (Phillips Steel TRI-MET Black Cr3 are included in delivery)
Finally, tighten the screws (torque of 10 cNm 1 cNm).
STEP 5
Tighten Screws (2 pcs); 10 cNm 1 cNm
Thats all. You may now move on to final inspection or configuration of your application board.
Moisture Preconditioning
The package, internal components and substrate materials absorb moisture. JEDEC specification J-STD-020 shall be observed in order to prevent cracking and delamination during solder reflow. Baking before processing is required in the following cases Humidity indicator card indicates moisture over 10% Floor life or environmental requirements after opening the seal has been exceeded, e.g. exposure to excessive seasonal humidity Ensure that only active devices will be baked, not the cartoon package and electrostatic padding inside of the package. Package will not stand baking temperature.
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TABLE 26 RECOMMENDED BAKING PROCEDURE Parameter Before work Oven Type Baking Duration Baking Temperature Humidity After work Value Separate active components from the delivery package Convection Flow Oven 48 hours 125C < 5% (Put desiccant pack into the oven to keep humidity low) Put the baked components with desiccant and moisture indicator into a humidity proof bag and use a vacuum hot barrier sealing machine for sealing if not processed within specified floor time. Storage in a nitrogen cabinet or dry box is also a possible approach to prevent moisture intake.
Note, that a repeated baking process will reduce the wetting effectiveness of solder ball contacts. This applies to all surface mounted devices.
Solder Paste
Standard no-clean SnPb (63% / 37%) or Pb-free solder pastes may be used for soldering the package. Solder pastes should be selected according to their printing and reflow behavior. For Pb-free solder paste it is recommended to use SnAg3.8Cu0.7 with melting point of 217C.
Reflow Profile
Standard convection reflow oven may be used to mount the CHILImodule packages. The profile depends on the design of printed circuit board and other components on the base substrate. The CHILImodule device shall be soldered on the top side of the application board. During the solder process always ensure that the module is on the top side: This is in order to avoid malfunction due to melt solder joints inside of the device. For maximum peak temperature JEDEC specification should be followed to avoid overheating the components.
TABLE 27 REFLOW PROFILE RECOMMENDATIONS Parameter Average Ramp-Up Rate Preheat Minimum Temperature Maximum Temperature Time Time maintained above Temperature Time Maximum Peak Temperature Minimum Peak Temperature Time Within 5C of Actual Temperature Ramp-Down Rate Time 25C Temperature to Maximum Eutetic SnPb 2C/second max. 100C 150C 60-120 seconds 183C 60-90 seconds 240C (+0/-5C) 205C 10-30 seconds >180C: 2C/second max. <180C: 6C/second max. 4-5 minutes Pb-free 2C/second max. 150C 200C 75-90 seconds ( 0.75C/second) 219C 70-90 seconds 250C (+0C) 235C 20-30 seconds >180C: 2C/second max. <180C: 6C/second max. 4-5 minutes
Peak
Peak
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Typical SAC solder alloy melting point is 217C, and the minimum peak reflow temperature is 235C. Examples of reflow profiles are shown in the following figures.
FIGURE 46 EXAMPLES OF REFLOW PROFILES
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FIGURE 47 ANOTHER REFLOW PROFILE EXAMPLE
Note Due to total weight of the CHILImodule boards, the ramp-up and ramp-down speeds may need to be slower than specified in JEDEC JSTD-020C. In order to heat the board to a peak temperature that is well above the melting point of the solder, but below the temperature at which the components and printed circuit boards are damaged the profile should be set with care. Typically, the conveyer speed should be set slower than in normal reflow process. Also, the preheating time should be longer and the temperature ramp-up speed slower. Starting cooling-down phase early helps to keep maximum temperature within the specified limits. In the Figure 46 Examples of Reflow Profile the heating zone temperatures were adjusted according to the following table.
TABLE 28 HEATING ZONE TEMPERATURES (EXAMPLE) Heating Zone # Zone Zone Zone Zone Zone Zone Zone Zone 1 2 3 4 5 6 7 8 Up 150C 190C 240C 240C 260C 270C 275C 275C Zone Temperature Down 150C 190C 240C 240C 260C 270C 275C 275C
Note also, that the reflow oven settings depend on the oven type and manufacturer, and the reflow profile should be set carefully according to the oven in use.
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Rework and Component Removal

If rework is needed, the CHILImodule devices may be removed or reworked using ball grid array (BGA) repair station. The rework process involves the following steps: Component removal Site redress Solder paste application Component placement Component attachment Note, that using the BGA repair station may require ordering special nozzle for the CHILImodule device in order to control hot air flow properly during the rework process. Please, consult the rework station tool provider for details.
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DISCLAIMERS
CHILIdevices International and its subsidiaries (CHILIdevices) reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. CHILIdevices reserves the right to discontinue any product or service without notice, and advice customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. CHILIdevices assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. CHILIdevices customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify CHILIdevices for any damages resulting from such application. CHILIdevices warrants performance of its products to the specifications applicable at the time of sale in accordance with CHILIdevices's standard warranty. Testing and other quality control techniques are utilized to the extent CHILIdevices deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using CHILIdevices components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. CHILIdevices assumes no liability for applications assistance or customer product design. CHILIdevices does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of CHILIdevices covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. CHILIdevices's publication of information regarding any third party's products or services does not constitute CHILIdevices's approval, warranty or endorsement thereof. Copyright 2010, CHILIdevices International
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APPENDIX
CHILImodule - FPGA Connections Cross Reference
Following table describes the signal routing from CHILImodule device pins to built-in Altera Cyclone 324-pin package pins. Note, that associated reference voltage banks for the Cyclone pins have been referred by Vx_IOBy (= VREFxBy).
CHILImodule - Altera Cyclone Connections CHILImodule Signal Pin FPGA_IO000 315 FPGA_IO001 314 FPGA_IO002 313 285 Signal Description Programmable I/O signal Programmable I/O signal NOTE: Optional DEV_OE input pin for overriding all tri-states on the device in addition to general purpose I/O pin. 1.8V only logic levels NOTE: Optional DEV_CLRn input pin for overriding all clears on all device registers in addition to general purpose I/O. 1.8V only logic levels Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Programmable I/O signal Altera Cyclone Signal CLKUSR/V0_IOB1_54 V0_IOB1_55/INIT_DONE V2_IOB2_56/DEV_OE
Pin D3 C3 B3
FPGA_IO003
C4
V2_IOB2_57/DEV_CLRn
FPGA_IO004 FPGA_IO005 FPGA_IO006 FPGA_IO007 FPGA_IO008 FPGA_IO009 FPGA_IO010 FPGA_IO011 FPGA_IO012 FPGA_IO013 FPGA_IO014 FPGA_IO015 FPGA_IO016 FPGA_IO017 FPGA_IO018 FPGA_IO019 FPGA_IO020 FPGA_IO021 FPGA_IO022 FPGA_IO023 FPGA_IO024 FPGA_IO025 FPGA_IO026 FPGA_IO027 FPGA_IO028 FPGA_IO029 FPGA_IO030 FPGA_IO031 FPGA_IO032 FPGA_IO033 FPGA_IO034 FPGA_IO035 FPGA_IO036 FPGA_IO037 FPGA_IO038 FPGA_IO039
320 319 324 323 321 291 318 296 295 293 261 317 316 267 265 263 232 289 259 287 237 236 234 233 231 229 257 206 197 204 203 230 228 198 190 188
T5 R5 V7 U7 T7 R7 P7 V8 U8 T8 R8 N8 M8 V9 U9 T9 R9 P9 N9 M9 V10 U10 T10 R10 P10 N10 M10 V11 U11 T11 R11 N11 M11 V12 U12 T12
V2_IOB4_6 V2_IOB4_58/VREF2B4 V2_IOB4_16 V2_IOB4_15 V2_IOB4_17 V2_IOB4_18 V2_IOB4_12 V1_IOB4_20 V1_IOB4_19 V1_IOB4_21 V1_IOB4_22 V2_IOB4_1 V2_IOB4_0 V1_IOB4_24 V1_IOB4_23 V1_IOB4_26 V1_IOB4_25 V1_IOB4_59/VREF1B4 V1_IOB4_28 V1_IOB4_27 V1_IOB4_30 V1_IOB4_29 V1_IOB4_30 V1_IOB4_32 V1_IOB4_33 V0_IOB_45 V0_IOB_47 V1_IOB4_37 V1_IOB4_36 V1_IOB4_35 V1_IOB4_34 V0_IOB_54 V0_IOB_55 V1_IOB4_38 V1_IOB4_39 V0_IOB_40
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CHILImodule - Altera Cyclone Connections CHILImodule Signal FPGA_IO040 FPGA_IO041 FPGA_IO042 FPGA_IO043 FPGA_IO044 FPGA_IO045 FPGA_IO046 FPGA_IO047 FPGA_IO048 FPGA_IO049 FPGA_IO050 FPGA_IO051 FPGA_IO052 FPGA_IO053 FPGA_IO054 FPGA_IO055 FPGA_IO056 FPGA_IO057 FPGA_IO058 FPGA_IO059 FPGA_IO060 FPGA_IO061 FPGA_IO062 FPGA_IO063 FPGA_IO064 FPGA_IO065 FPGA_IO066 FPGA_IO067 FPGA_IO068 FPGA_IO069 FPGA_IO070 FPGA_IO071 FPGA_IO072 FPGA_IO073 FPGA_IO074 FPGA_IO075 FPGA_IO076 FPGA_IO077 FPGA_IO078 FPGA_IO079 FPGA_IO080 FPGA_IO081 FPGA_IO082 FPGA_IO083 FPGA_IO084 FPGA_IO085 FPGA_IO086 FPGA_IO087 FPGA_IO088 FPGA_IO089 FPGA_IO090 FPGA_IO091 FPGA_IO092 FPGA_IO093 FPGA_IO094 FPGA_IO095 FPGA_IO096 FPGA_IO097 Signal Description Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal Altera Cyclone Signal V0_IOB_41 V0_IOB_48 V0_IOB_42 V0_IOB_43 V0_IOB_44 V0_IOB_45 V0IOB4_60/VREF0B4 V0_IOB_49/DPCLK6 V0_IOB_50 V0_IOB_51 V0_IOB_52 V0_IOB_53 V0_IOB_52 V0_IOB_53 V2_IOB3_1 V2_IOB3_0 V2_IOB3_3 V2_IOB3_2 V2_IOB3_5 V2_IOB3_4 V2_IOB3_6 V2_IOB3_58/VREF2B3 V2_IOB3_7/DPCLK5 V2_IOB3_7 V2_IOB3_9 V2_IOB3_10 V2_IOB3_13 V2_IOB3_14 V2_IOB3_8 V2_IOB3_11 V2_IOB3_12 V2_IOB3_15 V2_IOB3_16 V2_IOB3_19 V2_IOB3_18 V2_IOB3_17 V2_IOB3_22 V2_IOB3_20 V2_IOB3_21 V2_IOB3_24 V2_IOB3_25 V2_IOB3_26 V2_IOB3_23 V2_IOB3_27/PLL2_OUTN V2_IOB3_28/PLL2_OUTP V1_IOB3_59/VREF1B3 V2_IOB3_29 V2_IOB3_35 V2_IOB3_34 V2_IOB3_33 V2_IOB3_32 V2_IOB3_31 V2_IOB3_30 V2_IOB3_36 V2_IOB3_37 V2_IOB3_41 V2_IOB3_40 V2_IOB3_39
Pin 195 139 182 181 179 187 115 174 172 171 166 165 156 158 150 149 142 147 155 163 28 27 56 84 26 54 82 112 113 114 140 25 24 52 80 110 111 23 22 50 78 108 109 21 48 20 107 19 18 46 76 105 106 17 16 44 74 102
Pin R12 P12 V13 U13 T13 R13 P13 U14 T14 R14 V15 U15 T15 U16 T17 T16 R18 R17 R16 R15 P17 P16 P15 P14 N18 N17 N16 N15 N14 N13 N12 M18 M17 M16 M15 M14 M13 L18 L17 L16 L15 L14 L13 K16 K15 J14 J13 H18 H17 H16 H15 H14 H13 G18 G17 G16 G15 G14
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CHILImodule - Altera Cyclone Connections CHILImodule Signal FPGA_IO098 FPGA_IO099 FPGA_IO100 FPGA_IO101 FPGA_IO102 FPGA_IO103 FPGA_IO104 FPGA_IO105 FPGA_IO106 FPGA_IO107 FPGA_IO108 FPGA_IO109 FPGA_IO110 FPGA_IO111 FPGA_IO112 FPGA_IO113 FPGA_IO114 FPGA_IO115 FPGA_CLK1 FPGA_CLK2 Signal Description Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal signal Altera Cyclone Signal V2_IOB3_38 V2_IOB3_42 V2_IOB3_44 V2_IOB3_45 V2_IOB3_48 V2_IOB3_49 V2_IOB3_47 V2_IOB3_46 V2_IOB3_43 V2_IOB3_50/DPCLK4 V2_IOB3_51 V2_IOB3_52 V0_IOB3_60/VREF0B3 V2_IOB3_53 V2_IOB3_57 V2_IOB3_54 V2_IOB3_55 V2_IOB3_56 CLK1 CLK2
Pin 103 104 15 14 13 42 72 100 101 12 40 70 99 11 38 68 98 10 223 224
Pin G13 G12 F18 F17 F16 F15 F14 F13 F12 E17 E16 E15 E14 D18 D17 D16 D15 C17 J4 J15
External FPGA clock signal input (connected to Cyclone CLK1 pin) External FPGA clock signal input (connected to Cyclone CLK2 pin) Variable latency input signal of the PXA270 for inserting wait states (internal pull-up). Also connected to FPGA device L Wait H VLIO is ready
PXA_RDY[1]
275
R2
V2_IOB1_50
[1]
Signal PXA_RDY can be driven both by external device and the Altera Cyclone (open drain output) in case of VLIO. Signal is internally pulled up (1k) in the CHILImodule to +3.3V, and it is connected to PXA270 RDY input via voltage level translator.
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CHILIdevices International

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Copyright CHILIdevices International 2010. All Rights Reserved.

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Module Interfaces ..................................................................... 46

ADDITIONAL INFORMATION ................................65

APPLICATION GUIDELINES ..................................66

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Application Notes ...................................................................... 73

Assembly Guidelines ................................................................. 80

DISCLAIMERS ....................................................... 87 APPENDIX ............................................................ 88

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2.3.2009 18.5.2009 22.2.2010

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DATA SHEET STATUS

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DEFINITIONS AND ABBREVIATIONS

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Wireless Features ZigBee Interface WLAN Interface

IEEE 802.15.4 (Int./Ext. Antenna) IEEE 802.11b (Int./Ext. Antenna)

324 Pin BGA (2.0 mm Pitch) 70.5 x 46.5 x 10 mm

324 Pin BGA (2.0 mm Pitch) 70.5 x 46.5 x 10 mm

Yes NA NA Yes Yes Yes Yes Yes

Yes Yes Yes Yes Yes Yes Yes Yes

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CHILImodule Standard CDM15401 Yes Yes Yes Yes Yes

CHILImodule Professional CDM15400 Yes Yes Yes Yes Yes

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Processor and Memory

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Field Programmable Logic Array (FPGA)

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FUNCTIONAL BLOCK DIAGRAM

V(BKBT) Capacity Temp ID Status

Adj. Li Battery Charger Charge_EN